Macros
#define	AAR_INTENSET_NOTRESOLVED_Pos (2UL)

#define	AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos)

#define	AAR_INTENSET_NOTRESOLVED_Disabled (0UL)

#define	AAR_INTENSET_NOTRESOLVED_Enabled (1UL)

#define	AAR_INTENSET_NOTRESOLVED_Set (1UL)

#define	AAR_INTENSET_RESOLVED_Pos (1UL)

#define	AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos)

#define	AAR_INTENSET_RESOLVED_Disabled (0UL)

#define	AAR_INTENSET_RESOLVED_Enabled (1UL)

#define	AAR_INTENSET_RESOLVED_Set (1UL)

#define	AAR_INTENSET_END_Pos (0UL)

#define	AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos)

#define	AAR_INTENSET_END_Disabled (0UL)

#define	AAR_INTENSET_END_Enabled (1UL)

#define	AAR_INTENSET_END_Set (1UL)

#define	AAR_INTENCLR_NOTRESOLVED_Pos (2UL)

#define	AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos)

#define	AAR_INTENCLR_NOTRESOLVED_Disabled (0UL)

#define	AAR_INTENCLR_NOTRESOLVED_Enabled (1UL)

#define	AAR_INTENCLR_NOTRESOLVED_Clear (1UL)

#define	AAR_INTENCLR_RESOLVED_Pos (1UL)

#define	AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos)

#define	AAR_INTENCLR_RESOLVED_Disabled (0UL)

#define	AAR_INTENCLR_RESOLVED_Enabled (1UL)

#define	AAR_INTENCLR_RESOLVED_Clear (1UL)

#define	AAR_INTENCLR_END_Pos (0UL)

#define	AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos)

#define	AAR_INTENCLR_END_Disabled (0UL)

#define	AAR_INTENCLR_END_Enabled (1UL)

#define	AAR_INTENCLR_END_Clear (1UL)

#define	AAR_STATUS_STATUS_Pos (0UL)

#define	AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos)

#define	AAR_ENABLE_ENABLE_Pos (0UL)

#define	AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos)

#define	AAR_ENABLE_ENABLE_Disabled (0x00UL)

#define	AAR_ENABLE_ENABLE_Enabled (0x03UL)

#define	AAR_NIRK_NIRK_Pos (0UL)

#define	AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos)

#define	AAR_POWER_POWER_Pos (0UL)

#define	AAR_POWER_POWER_Msk (0x1UL << AAR_POWER_POWER_Pos)

#define	AAR_POWER_POWER_Disabled (0UL)

#define	AAR_POWER_POWER_Enabled (1UL)

#define	ADC_INTENSET_END_Pos (0UL)

#define	ADC_INTENSET_END_Msk (0x1UL << ADC_INTENSET_END_Pos)

#define	ADC_INTENSET_END_Disabled (0UL)

#define	ADC_INTENSET_END_Enabled (1UL)

#define	ADC_INTENSET_END_Set (1UL)

#define	ADC_INTENCLR_END_Pos (0UL)

#define	ADC_INTENCLR_END_Msk (0x1UL << ADC_INTENCLR_END_Pos)

#define	ADC_INTENCLR_END_Disabled (0UL)

#define	ADC_INTENCLR_END_Enabled (1UL)

#define	ADC_INTENCLR_END_Clear (1UL)

#define	ADC_BUSY_BUSY_Pos (0UL)

#define	ADC_BUSY_BUSY_Msk (0x1UL << ADC_BUSY_BUSY_Pos)

#define	ADC_BUSY_BUSY_Ready (0UL)

#define	ADC_BUSY_BUSY_Busy (1UL)

#define	ADC_ENABLE_ENABLE_Pos (0UL)

#define	ADC_ENABLE_ENABLE_Msk (0x3UL << ADC_ENABLE_ENABLE_Pos)

#define	ADC_ENABLE_ENABLE_Disabled (0x00UL)

#define	ADC_ENABLE_ENABLE_Enabled (0x01UL)

#define	ADC_CONFIG_EXTREFSEL_Pos (16UL)

#define	ADC_CONFIG_EXTREFSEL_Msk (0x3UL << ADC_CONFIG_EXTREFSEL_Pos)

#define	ADC_CONFIG_EXTREFSEL_None (0UL)

#define	ADC_CONFIG_EXTREFSEL_AnalogReference0 (1UL)

#define	ADC_CONFIG_EXTREFSEL_AnalogReference1 (2UL)

#define	ADC_CONFIG_PSEL_Pos (8UL)

#define	ADC_CONFIG_PSEL_Msk (0xFFUL << ADC_CONFIG_PSEL_Pos)

#define	ADC_CONFIG_PSEL_Disabled (0UL)

#define	ADC_CONFIG_PSEL_AnalogInput0 (1UL)

#define	ADC_CONFIG_PSEL_AnalogInput1 (2UL)

#define	ADC_CONFIG_PSEL_AnalogInput2 (4UL)

#define	ADC_CONFIG_PSEL_AnalogInput3 (8UL)

#define	ADC_CONFIG_PSEL_AnalogInput4 (16UL)

#define	ADC_CONFIG_PSEL_AnalogInput5 (32UL)

#define	ADC_CONFIG_PSEL_AnalogInput6 (64UL)

#define	ADC_CONFIG_PSEL_AnalogInput7 (128UL)

#define	ADC_CONFIG_REFSEL_Pos (5UL)

#define	ADC_CONFIG_REFSEL_Msk (0x3UL << ADC_CONFIG_REFSEL_Pos)

#define	ADC_CONFIG_REFSEL_VBG (0x00UL)

#define	ADC_CONFIG_REFSEL_External (0x01UL)

#define	ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling (0x02UL)

#define	ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling (0x03UL)

#define	ADC_CONFIG_INPSEL_Pos (2UL)

#define	ADC_CONFIG_INPSEL_Msk (0x7UL << ADC_CONFIG_INPSEL_Pos)

#define	ADC_CONFIG_INPSEL_AnalogInputNoPrescaling (0x00UL)

#define	ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling (0x01UL)

#define	ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling (0x02UL)

#define	ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling (0x05UL)

#define	ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling (0x06UL)

#define	ADC_CONFIG_RES_Pos (0UL)

#define	ADC_CONFIG_RES_Msk (0x3UL << ADC_CONFIG_RES_Pos)

#define	ADC_CONFIG_RES_8bit (0x00UL)

#define	ADC_CONFIG_RES_9bit (0x01UL)

#define	ADC_CONFIG_RES_10bit (0x02UL)

#define	ADC_RESULT_RESULT_Pos (0UL)

#define	ADC_RESULT_RESULT_Msk (0x3FFUL << ADC_RESULT_RESULT_Pos)

#define	ADC_POWER_POWER_Pos (0UL)

#define	ADC_POWER_POWER_Msk (0x1UL << ADC_POWER_POWER_Pos)

#define	ADC_POWER_POWER_Disabled (0UL)

#define	ADC_POWER_POWER_Enabled (1UL)

#define	AMLI_RAMPRI_CPU0_RAM7_Pos (28UL)

#define	AMLI_RAMPRI_CPU0_RAM7_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM7_Pos)

#define	AMLI_RAMPRI_CPU0_RAM7_Pri0 (0x0UL)

#define	AMLI_RAMPRI_CPU0_RAM7_Pri2 (0x2UL)

#define	AMLI_RAMPRI_CPU0_RAM7_Pri4 (0x4UL)

#define	AMLI_RAMPRI_CPU0_RAM7_Pri6 (0x6UL)

#define	AMLI_RAMPRI_CPU0_RAM7_Pri8 (0x8UL)

#define	AMLI_RAMPRI_CPU0_RAM7_Pri10 (0xAUL)

#define	AMLI_RAMPRI_CPU0_RAM7_Pri12 (0xCUL)

#define	AMLI_RAMPRI_CPU0_RAM7_Pri14 (0xEUL)

#define	AMLI_RAMPRI_CPU0_RAM6_Pos (24UL)

#define	AMLI_RAMPRI_CPU0_RAM6_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM6_Pos)

#define	AMLI_RAMPRI_CPU0_RAM6_Pri0 (0x0UL)

#define	AMLI_RAMPRI_CPU0_RAM6_Pri2 (0x2UL)

#define	AMLI_RAMPRI_CPU0_RAM6_Pri4 (0x4UL)

#define	AMLI_RAMPRI_CPU0_RAM6_Pri6 (0x6UL)

#define	AMLI_RAMPRI_CPU0_RAM6_Pri8 (0x8UL)

#define	AMLI_RAMPRI_CPU0_RAM6_Pri10 (0xAUL)

#define	AMLI_RAMPRI_CPU0_RAM6_Pri12 (0xCUL)

#define	AMLI_RAMPRI_CPU0_RAM6_Pri14 (0xEUL)

#define	AMLI_RAMPRI_CPU0_RAM5_Pos (20UL)

#define	AMLI_RAMPRI_CPU0_RAM5_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM5_Pos)

#define	AMLI_RAMPRI_CPU0_RAM5_Pri0 (0x0UL)

#define	AMLI_RAMPRI_CPU0_RAM5_Pri2 (0x2UL)

#define	AMLI_RAMPRI_CPU0_RAM5_Pri4 (0x4UL)

#define	AMLI_RAMPRI_CPU0_RAM5_Pri6 (0x6UL)

#define	AMLI_RAMPRI_CPU0_RAM5_Pri8 (0x8UL)

#define	AMLI_RAMPRI_CPU0_RAM5_Pri10 (0xAUL)

#define	AMLI_RAMPRI_CPU0_RAM5_Pri12 (0xCUL)

#define	AMLI_RAMPRI_CPU0_RAM5_Pri14 (0xEUL)

#define	AMLI_RAMPRI_CPU0_RAM4_Pos (16UL)

#define	AMLI_RAMPRI_CPU0_RAM4_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM4_Pos)

#define	AMLI_RAMPRI_CPU0_RAM4_Pri0 (0x0UL)

#define	AMLI_RAMPRI_CPU0_RAM4_Pri2 (0x2UL)

#define	AMLI_RAMPRI_CPU0_RAM4_Pri4 (0x4UL)

#define	AMLI_RAMPRI_CPU0_RAM4_Pri6 (0x6UL)

#define	AMLI_RAMPRI_CPU0_RAM4_Pri8 (0x8UL)

#define	AMLI_RAMPRI_CPU0_RAM4_Pri10 (0xAUL)

#define	AMLI_RAMPRI_CPU0_RAM4_Pri12 (0xCUL)

#define	AMLI_RAMPRI_CPU0_RAM4_Pri14 (0xEUL)

#define	AMLI_RAMPRI_CPU0_RAM3_Pos (12UL)

#define	AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos)

#define	AMLI_RAMPRI_CPU0_RAM3_Pri0 (0x0UL)

#define	AMLI_RAMPRI_CPU0_RAM3_Pri2 (0x2UL)

#define	AMLI_RAMPRI_CPU0_RAM3_Pri4 (0x4UL)

#define	AMLI_RAMPRI_CPU0_RAM3_Pri6 (0x6UL)

#define	AMLI_RAMPRI_CPU0_RAM3_Pri8 (0x8UL)

#define	AMLI_RAMPRI_CPU0_RAM3_Pri10 (0xAUL)

#define	AMLI_RAMPRI_CPU0_RAM3_Pri12 (0xCUL)

#define	AMLI_RAMPRI_CPU0_RAM3_Pri14 (0xEUL)

#define	AMLI_RAMPRI_CPU0_RAM2_Pos (8UL)

#define	AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos)

#define	AMLI_RAMPRI_CPU0_RAM2_Pri0 (0x0UL)

#define	AMLI_RAMPRI_CPU0_RAM2_Pri2 (0x2UL)

#define	AMLI_RAMPRI_CPU0_RAM2_Pri4 (0x4UL)

#define	AMLI_RAMPRI_CPU0_RAM2_Pri6 (0x6UL)

#define	AMLI_RAMPRI_CPU0_RAM2_Pri8 (0x8UL)

#define	AMLI_RAMPRI_CPU0_RAM2_Pri10 (0xAUL)

#define	AMLI_RAMPRI_CPU0_RAM2_Pri12 (0xCUL)

#define	AMLI_RAMPRI_CPU0_RAM2_Pri14 (0xEUL)

#define	AMLI_RAMPRI_CPU0_RAM1_Pos (4UL)

#define	AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos)

#define	AMLI_RAMPRI_CPU0_RAM1_Pri0 (0x0UL)

#define	AMLI_RAMPRI_CPU0_RAM1_Pri2 (0x2UL)

#define	AMLI_RAMPRI_CPU0_RAM1_Pri4 (0x4UL)

#define	AMLI_RAMPRI_CPU0_RAM1_Pri6 (0x6UL)

#define	AMLI_RAMPRI_CPU0_RAM1_Pri8 (0x8UL)

#define	AMLI_RAMPRI_CPU0_RAM1_Pri10 (0xAUL)

#define	AMLI_RAMPRI_CPU0_RAM1_Pri12 (0xCUL)

#define	AMLI_RAMPRI_CPU0_RAM1_Pri14 (0xEUL)

#define	AMLI_RAMPRI_CPU0_RAM0_Pos (0UL)

#define	AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos)

#define	AMLI_RAMPRI_CPU0_RAM0_Pri0 (0x0UL)

#define	AMLI_RAMPRI_CPU0_RAM0_Pri2 (0x2UL)

#define	AMLI_RAMPRI_CPU0_RAM0_Pri4 (0x4UL)

#define	AMLI_RAMPRI_CPU0_RAM0_Pri6 (0x6UL)

#define	AMLI_RAMPRI_CPU0_RAM0_Pri8 (0x8UL)

#define	AMLI_RAMPRI_CPU0_RAM0_Pri10 (0xAUL)

#define	AMLI_RAMPRI_CPU0_RAM0_Pri12 (0xCUL)

#define	AMLI_RAMPRI_CPU0_RAM0_Pri14 (0xEUL)

#define	AMLI_RAMPRI_SPIS1_RAM7_Pos (28UL)

#define	AMLI_RAMPRI_SPIS1_RAM7_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM7_Pos)

#define	AMLI_RAMPRI_SPIS1_RAM7_Pri0 (0x0UL)

#define	AMLI_RAMPRI_SPIS1_RAM7_Pri2 (0x2UL)

#define	AMLI_RAMPRI_SPIS1_RAM7_Pri4 (0x4UL)

#define	AMLI_RAMPRI_SPIS1_RAM7_Pri6 (0x6UL)

#define	AMLI_RAMPRI_SPIS1_RAM7_Pri8 (0x8UL)

#define	AMLI_RAMPRI_SPIS1_RAM7_Pri10 (0xAUL)

#define	AMLI_RAMPRI_SPIS1_RAM7_Pri12 (0xCUL)

#define	AMLI_RAMPRI_SPIS1_RAM7_Pri14 (0xEUL)

#define	AMLI_RAMPRI_SPIS1_RAM6_Pos (24UL)

#define	AMLI_RAMPRI_SPIS1_RAM6_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM6_Pos)

#define	AMLI_RAMPRI_SPIS1_RAM6_Pri0 (0x0UL)

#define	AMLI_RAMPRI_SPIS1_RAM6_Pri2 (0x2UL)

#define	AMLI_RAMPRI_SPIS1_RAM6_Pri4 (0x4UL)

#define	AMLI_RAMPRI_SPIS1_RAM6_Pri6 (0x6UL)

#define	AMLI_RAMPRI_SPIS1_RAM6_Pri8 (0x8UL)

#define	AMLI_RAMPRI_SPIS1_RAM6_Pri10 (0xAUL)

#define	AMLI_RAMPRI_SPIS1_RAM6_Pri12 (0xCUL)

#define	AMLI_RAMPRI_SPIS1_RAM6_Pri14 (0xEUL)

#define	AMLI_RAMPRI_SPIS1_RAM5_Pos (20UL)

#define	AMLI_RAMPRI_SPIS1_RAM5_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM5_Pos)

#define	AMLI_RAMPRI_SPIS1_RAM5_Pri0 (0x0UL)

#define	AMLI_RAMPRI_SPIS1_RAM5_Pri2 (0x2UL)

#define	AMLI_RAMPRI_SPIS1_RAM5_Pri4 (0x4UL)

#define	AMLI_RAMPRI_SPIS1_RAM5_Pri6 (0x6UL)

#define	AMLI_RAMPRI_SPIS1_RAM5_Pri8 (0x8UL)

#define	AMLI_RAMPRI_SPIS1_RAM5_Pri10 (0xAUL)

#define	AMLI_RAMPRI_SPIS1_RAM5_Pri12 (0xCUL)

#define	AMLI_RAMPRI_SPIS1_RAM5_Pri14 (0xEUL)

#define	AMLI_RAMPRI_SPIS1_RAM4_Pos (16UL)

#define	AMLI_RAMPRI_SPIS1_RAM4_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM4_Pos)

#define	AMLI_RAMPRI_SPIS1_RAM4_Pri0 (0x0UL)

#define	AMLI_RAMPRI_SPIS1_RAM4_Pri2 (0x2UL)

#define	AMLI_RAMPRI_SPIS1_RAM4_Pri4 (0x4UL)

#define	AMLI_RAMPRI_SPIS1_RAM4_Pri6 (0x6UL)

#define	AMLI_RAMPRI_SPIS1_RAM4_Pri8 (0x8UL)

#define	AMLI_RAMPRI_SPIS1_RAM4_Pri10 (0xAUL)

#define	AMLI_RAMPRI_SPIS1_RAM4_Pri12 (0xCUL)

#define	AMLI_RAMPRI_SPIS1_RAM4_Pri14 (0xEUL)

#define	AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL)

#define	AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos)

#define	AMLI_RAMPRI_SPIS1_RAM3_Pri0 (0x0UL)

#define	AMLI_RAMPRI_SPIS1_RAM3_Pri2 (0x2UL)

#define	AMLI_RAMPRI_SPIS1_RAM3_Pri4 (0x4UL)

#define	AMLI_RAMPRI_SPIS1_RAM3_Pri6 (0x6UL)

#define	AMLI_RAMPRI_SPIS1_RAM3_Pri8 (0x8UL)

#define	AMLI_RAMPRI_SPIS1_RAM3_Pri10 (0xAUL)

#define	AMLI_RAMPRI_SPIS1_RAM3_Pri12 (0xCUL)

#define	AMLI_RAMPRI_SPIS1_RAM3_Pri14 (0xEUL)

#define	AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL)

#define	AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos)

#define	AMLI_RAMPRI_SPIS1_RAM2_Pri0 (0x0UL)

#define	AMLI_RAMPRI_SPIS1_RAM2_Pri2 (0x2UL)

#define	AMLI_RAMPRI_SPIS1_RAM2_Pri4 (0x4UL)

#define	AMLI_RAMPRI_SPIS1_RAM2_Pri6 (0x6UL)

#define	AMLI_RAMPRI_SPIS1_RAM2_Pri8 (0x8UL)

#define	AMLI_RAMPRI_SPIS1_RAM2_Pri10 (0xAUL)

#define	AMLI_RAMPRI_SPIS1_RAM2_Pri12 (0xCUL)

#define	AMLI_RAMPRI_SPIS1_RAM2_Pri14 (0xEUL)

#define	AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL)

#define	AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos)

#define	AMLI_RAMPRI_SPIS1_RAM1_Pri0 (0x0UL)

#define	AMLI_RAMPRI_SPIS1_RAM1_Pri2 (0x2UL)

#define	AMLI_RAMPRI_SPIS1_RAM1_Pri4 (0x4UL)

#define	AMLI_RAMPRI_SPIS1_RAM1_Pri6 (0x6UL)

#define	AMLI_RAMPRI_SPIS1_RAM1_Pri8 (0x8UL)

#define	AMLI_RAMPRI_SPIS1_RAM1_Pri10 (0xAUL)

#define	AMLI_RAMPRI_SPIS1_RAM1_Pri12 (0xCUL)

#define	AMLI_RAMPRI_SPIS1_RAM1_Pri14 (0xEUL)

#define	AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL)

#define	AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos)

#define	AMLI_RAMPRI_SPIS1_RAM0_Pri0 (0x0UL)

#define	AMLI_RAMPRI_SPIS1_RAM0_Pri2 (0x2UL)

#define	AMLI_RAMPRI_SPIS1_RAM0_Pri4 (0x4UL)

#define	AMLI_RAMPRI_SPIS1_RAM0_Pri6 (0x6UL)

#define	AMLI_RAMPRI_SPIS1_RAM0_Pri8 (0x8UL)

#define	AMLI_RAMPRI_SPIS1_RAM0_Pri10 (0xAUL)

#define	AMLI_RAMPRI_SPIS1_RAM0_Pri12 (0xCUL)

#define	AMLI_RAMPRI_SPIS1_RAM0_Pri14 (0xEUL)

#define	AMLI_RAMPRI_RADIO_RAM7_Pos (28UL)

#define	AMLI_RAMPRI_RADIO_RAM7_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM7_Pos)

#define	AMLI_RAMPRI_RADIO_RAM7_Pri0 (0x0UL)

#define	AMLI_RAMPRI_RADIO_RAM7_Pri2 (0x2UL)

#define	AMLI_RAMPRI_RADIO_RAM7_Pri4 (0x4UL)

#define	AMLI_RAMPRI_RADIO_RAM7_Pri6 (0x6UL)

#define	AMLI_RAMPRI_RADIO_RAM7_Pri8 (0x8UL)

#define	AMLI_RAMPRI_RADIO_RAM7_Pri10 (0xAUL)

#define	AMLI_RAMPRI_RADIO_RAM7_Pri12 (0xCUL)

#define	AMLI_RAMPRI_RADIO_RAM7_Pri14 (0xEUL)

#define	AMLI_RAMPRI_RADIO_RAM6_Pos (24UL)

#define	AMLI_RAMPRI_RADIO_RAM6_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM6_Pos)

#define	AMLI_RAMPRI_RADIO_RAM6_Pri0 (0x0UL)

#define	AMLI_RAMPRI_RADIO_RAM6_Pri2 (0x2UL)

#define	AMLI_RAMPRI_RADIO_RAM6_Pri4 (0x4UL)

#define	AMLI_RAMPRI_RADIO_RAM6_Pri6 (0x6UL)

#define	AMLI_RAMPRI_RADIO_RAM6_Pri8 (0x8UL)

#define	AMLI_RAMPRI_RADIO_RAM6_Pri10 (0xAUL)

#define	AMLI_RAMPRI_RADIO_RAM6_Pri12 (0xCUL)

#define	AMLI_RAMPRI_RADIO_RAM6_Pri14 (0xEUL)

#define	AMLI_RAMPRI_RADIO_RAM5_Pos (20UL)

#define	AMLI_RAMPRI_RADIO_RAM5_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM5_Pos)

#define	AMLI_RAMPRI_RADIO_RAM5_Pri0 (0x0UL)

#define	AMLI_RAMPRI_RADIO_RAM5_Pri2 (0x2UL)

#define	AMLI_RAMPRI_RADIO_RAM5_Pri4 (0x4UL)

#define	AMLI_RAMPRI_RADIO_RAM5_Pri6 (0x6UL)

#define	AMLI_RAMPRI_RADIO_RAM5_Pri8 (0x8UL)

#define	AMLI_RAMPRI_RADIO_RAM5_Pri10 (0xAUL)

#define	AMLI_RAMPRI_RADIO_RAM5_Pri12 (0xCUL)

#define	AMLI_RAMPRI_RADIO_RAM5_Pri14 (0xEUL)

#define	AMLI_RAMPRI_RADIO_RAM4_Pos (16UL)

#define	AMLI_RAMPRI_RADIO_RAM4_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM4_Pos)

#define	AMLI_RAMPRI_RADIO_RAM4_Pri0 (0x0UL)

#define	AMLI_RAMPRI_RADIO_RAM4_Pri2 (0x2UL)

#define	AMLI_RAMPRI_RADIO_RAM4_Pri4 (0x4UL)

#define	AMLI_RAMPRI_RADIO_RAM4_Pri6 (0x6UL)

#define	AMLI_RAMPRI_RADIO_RAM4_Pri8 (0x8UL)

#define	AMLI_RAMPRI_RADIO_RAM4_Pri10 (0xAUL)

#define	AMLI_RAMPRI_RADIO_RAM4_Pri12 (0xCUL)

#define	AMLI_RAMPRI_RADIO_RAM4_Pri14 (0xEUL)

#define	AMLI_RAMPRI_RADIO_RAM3_Pos (12UL)

#define	AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos)

#define	AMLI_RAMPRI_RADIO_RAM3_Pri0 (0x0UL)

#define	AMLI_RAMPRI_RADIO_RAM3_Pri2 (0x2UL)

#define	AMLI_RAMPRI_RADIO_RAM3_Pri4 (0x4UL)

#define	AMLI_RAMPRI_RADIO_RAM3_Pri6 (0x6UL)

#define	AMLI_RAMPRI_RADIO_RAM3_Pri8 (0x8UL)

#define	AMLI_RAMPRI_RADIO_RAM3_Pri10 (0xAUL)

#define	AMLI_RAMPRI_RADIO_RAM3_Pri12 (0xCUL)

#define	AMLI_RAMPRI_RADIO_RAM3_Pri14 (0xEUL)

#define	AMLI_RAMPRI_RADIO_RAM2_Pos (8UL)

#define	AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos)

#define	AMLI_RAMPRI_RADIO_RAM2_Pri0 (0x0UL)

#define	AMLI_RAMPRI_RADIO_RAM2_Pri2 (0x2UL)

#define	AMLI_RAMPRI_RADIO_RAM2_Pri4 (0x4UL)

#define	AMLI_RAMPRI_RADIO_RAM2_Pri6 (0x6UL)

#define	AMLI_RAMPRI_RADIO_RAM2_Pri8 (0x8UL)

#define	AMLI_RAMPRI_RADIO_RAM2_Pri10 (0xAUL)

#define	AMLI_RAMPRI_RADIO_RAM2_Pri12 (0xCUL)

#define	AMLI_RAMPRI_RADIO_RAM2_Pri14 (0xEUL)

#define	AMLI_RAMPRI_RADIO_RAM1_Pos (4UL)

#define	AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos)

#define	AMLI_RAMPRI_RADIO_RAM1_Pri0 (0x0UL)

#define	AMLI_RAMPRI_RADIO_RAM1_Pri2 (0x2UL)

#define	AMLI_RAMPRI_RADIO_RAM1_Pri4 (0x4UL)

#define	AMLI_RAMPRI_RADIO_RAM1_Pri6 (0x6UL)

#define	AMLI_RAMPRI_RADIO_RAM1_Pri8 (0x8UL)

#define	AMLI_RAMPRI_RADIO_RAM1_Pri10 (0xAUL)

#define	AMLI_RAMPRI_RADIO_RAM1_Pri12 (0xCUL)

#define	AMLI_RAMPRI_RADIO_RAM1_Pri14 (0xEUL)

#define	AMLI_RAMPRI_RADIO_RAM0_Pos (0UL)

#define	AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos)

#define	AMLI_RAMPRI_RADIO_RAM0_Pri0 (0x0UL)

#define	AMLI_RAMPRI_RADIO_RAM0_Pri2 (0x2UL)

#define	AMLI_RAMPRI_RADIO_RAM0_Pri4 (0x4UL)

#define	AMLI_RAMPRI_RADIO_RAM0_Pri6 (0x6UL)

#define	AMLI_RAMPRI_RADIO_RAM0_Pri8 (0x8UL)

#define	AMLI_RAMPRI_RADIO_RAM0_Pri10 (0xAUL)

#define	AMLI_RAMPRI_RADIO_RAM0_Pri12 (0xCUL)

#define	AMLI_RAMPRI_RADIO_RAM0_Pri14 (0xEUL)

#define	AMLI_RAMPRI_ECB_RAM7_Pos (28UL)

#define	AMLI_RAMPRI_ECB_RAM7_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM7_Pos)

#define	AMLI_RAMPRI_ECB_RAM7_Pri0 (0x0UL)

#define	AMLI_RAMPRI_ECB_RAM7_Pri2 (0x2UL)

#define	AMLI_RAMPRI_ECB_RAM7_Pri4 (0x4UL)

#define	AMLI_RAMPRI_ECB_RAM7_Pri6 (0x6UL)

#define	AMLI_RAMPRI_ECB_RAM7_Pri8 (0x8UL)

#define	AMLI_RAMPRI_ECB_RAM7_Pri10 (0xAUL)

#define	AMLI_RAMPRI_ECB_RAM7_Pri12 (0xCUL)

#define	AMLI_RAMPRI_ECB_RAM7_Pri14 (0xEUL)

#define	AMLI_RAMPRI_ECB_RAM6_Pos (24UL)

#define	AMLI_RAMPRI_ECB_RAM6_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM6_Pos)

#define	AMLI_RAMPRI_ECB_RAM6_Pri0 (0x0UL)

#define	AMLI_RAMPRI_ECB_RAM6_Pri2 (0x2UL)

#define	AMLI_RAMPRI_ECB_RAM6_Pri4 (0x4UL)

#define	AMLI_RAMPRI_ECB_RAM6_Pri6 (0x6UL)

#define	AMLI_RAMPRI_ECB_RAM6_Pri8 (0x8UL)

#define	AMLI_RAMPRI_ECB_RAM6_Pri10 (0xAUL)

#define	AMLI_RAMPRI_ECB_RAM6_Pri12 (0xCUL)

#define	AMLI_RAMPRI_ECB_RAM6_Pri14 (0xEUL)

#define	AMLI_RAMPRI_ECB_RAM5_Pos (20UL)

#define	AMLI_RAMPRI_ECB_RAM5_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM5_Pos)

#define	AMLI_RAMPRI_ECB_RAM5_Pri0 (0x0UL)

#define	AMLI_RAMPRI_ECB_RAM5_Pri2 (0x2UL)

#define	AMLI_RAMPRI_ECB_RAM5_Pri4 (0x4UL)

#define	AMLI_RAMPRI_ECB_RAM5_Pri6 (0x6UL)

#define	AMLI_RAMPRI_ECB_RAM5_Pri8 (0x8UL)

#define	AMLI_RAMPRI_ECB_RAM5_Pri10 (0xAUL)

#define	AMLI_RAMPRI_ECB_RAM5_Pri12 (0xCUL)

#define	AMLI_RAMPRI_ECB_RAM5_Pri14 (0xEUL)

#define	AMLI_RAMPRI_ECB_RAM4_Pos (16UL)

#define	AMLI_RAMPRI_ECB_RAM4_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM4_Pos)

#define	AMLI_RAMPRI_ECB_RAM4_Pri0 (0x0UL)

#define	AMLI_RAMPRI_ECB_RAM4_Pri2 (0x2UL)

#define	AMLI_RAMPRI_ECB_RAM4_Pri4 (0x4UL)

#define	AMLI_RAMPRI_ECB_RAM4_Pri6 (0x6UL)

#define	AMLI_RAMPRI_ECB_RAM4_Pri8 (0x8UL)

#define	AMLI_RAMPRI_ECB_RAM4_Pri10 (0xAUL)

#define	AMLI_RAMPRI_ECB_RAM4_Pri12 (0xCUL)

#define	AMLI_RAMPRI_ECB_RAM4_Pri14 (0xEUL)

#define	AMLI_RAMPRI_ECB_RAM3_Pos (12UL)

#define	AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos)

#define	AMLI_RAMPRI_ECB_RAM3_Pri0 (0x0UL)

#define	AMLI_RAMPRI_ECB_RAM3_Pri2 (0x2UL)

#define	AMLI_RAMPRI_ECB_RAM3_Pri4 (0x4UL)

#define	AMLI_RAMPRI_ECB_RAM3_Pri6 (0x6UL)

#define	AMLI_RAMPRI_ECB_RAM3_Pri8 (0x8UL)

#define	AMLI_RAMPRI_ECB_RAM3_Pri10 (0xAUL)

#define	AMLI_RAMPRI_ECB_RAM3_Pri12 (0xCUL)

#define	AMLI_RAMPRI_ECB_RAM3_Pri14 (0xEUL)

#define	AMLI_RAMPRI_ECB_RAM2_Pos (8UL)

#define	AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos)

#define	AMLI_RAMPRI_ECB_RAM2_Pri0 (0x0UL)

#define	AMLI_RAMPRI_ECB_RAM2_Pri2 (0x2UL)

#define	AMLI_RAMPRI_ECB_RAM2_Pri4 (0x4UL)

#define	AMLI_RAMPRI_ECB_RAM2_Pri6 (0x6UL)

#define	AMLI_RAMPRI_ECB_RAM2_Pri8 (0x8UL)

#define	AMLI_RAMPRI_ECB_RAM2_Pri10 (0xAUL)

#define	AMLI_RAMPRI_ECB_RAM2_Pri12 (0xCUL)

#define	AMLI_RAMPRI_ECB_RAM2_Pri14 (0xEUL)

#define	AMLI_RAMPRI_ECB_RAM1_Pos (4UL)

#define	AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos)

#define	AMLI_RAMPRI_ECB_RAM1_Pri0 (0x0UL)

#define	AMLI_RAMPRI_ECB_RAM1_Pri2 (0x2UL)

#define	AMLI_RAMPRI_ECB_RAM1_Pri4 (0x4UL)

#define	AMLI_RAMPRI_ECB_RAM1_Pri6 (0x6UL)

#define	AMLI_RAMPRI_ECB_RAM1_Pri8 (0x8UL)

#define	AMLI_RAMPRI_ECB_RAM1_Pri10 (0xAUL)

#define	AMLI_RAMPRI_ECB_RAM1_Pri12 (0xCUL)

#define	AMLI_RAMPRI_ECB_RAM1_Pri14 (0xEUL)

#define	AMLI_RAMPRI_ECB_RAM0_Pos (0UL)

#define	AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos)

#define	AMLI_RAMPRI_ECB_RAM0_Pri0 (0x0UL)

#define	AMLI_RAMPRI_ECB_RAM0_Pri2 (0x2UL)

#define	AMLI_RAMPRI_ECB_RAM0_Pri4 (0x4UL)

#define	AMLI_RAMPRI_ECB_RAM0_Pri6 (0x6UL)

#define	AMLI_RAMPRI_ECB_RAM0_Pri8 (0x8UL)

#define	AMLI_RAMPRI_ECB_RAM0_Pri10 (0xAUL)

#define	AMLI_RAMPRI_ECB_RAM0_Pri12 (0xCUL)

#define	AMLI_RAMPRI_ECB_RAM0_Pri14 (0xEUL)

#define	AMLI_RAMPRI_CCM_RAM7_Pos (28UL)

#define	AMLI_RAMPRI_CCM_RAM7_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM7_Pos)

#define	AMLI_RAMPRI_CCM_RAM7_Pri0 (0x0UL)

#define	AMLI_RAMPRI_CCM_RAM7_Pri2 (0x2UL)

#define	AMLI_RAMPRI_CCM_RAM7_Pri4 (0x4UL)

#define	AMLI_RAMPRI_CCM_RAM7_Pri6 (0x6UL)

#define	AMLI_RAMPRI_CCM_RAM7_Pri8 (0x8UL)

#define	AMLI_RAMPRI_CCM_RAM7_Pri10 (0xAUL)

#define	AMLI_RAMPRI_CCM_RAM7_Pri12 (0xCUL)

#define	AMLI_RAMPRI_CCM_RAM7_Pri14 (0xEUL)

#define	AMLI_RAMPRI_CCM_RAM6_Pos (24UL)

#define	AMLI_RAMPRI_CCM_RAM6_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM6_Pos)

#define	AMLI_RAMPRI_CCM_RAM6_Pri0 (0x0UL)

#define	AMLI_RAMPRI_CCM_RAM6_Pri2 (0x2UL)

#define	AMLI_RAMPRI_CCM_RAM6_Pri4 (0x4UL)

#define	AMLI_RAMPRI_CCM_RAM6_Pri6 (0x6UL)

#define	AMLI_RAMPRI_CCM_RAM6_Pri8 (0x8UL)

#define	AMLI_RAMPRI_CCM_RAM6_Pri10 (0xAUL)

#define	AMLI_RAMPRI_CCM_RAM6_Pri12 (0xCUL)

#define	AMLI_RAMPRI_CCM_RAM6_Pri14 (0xEUL)

#define	AMLI_RAMPRI_CCM_RAM5_Pos (20UL)

#define	AMLI_RAMPRI_CCM_RAM5_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM5_Pos)

#define	AMLI_RAMPRI_CCM_RAM5_Pri0 (0x0UL)

#define	AMLI_RAMPRI_CCM_RAM5_Pri2 (0x2UL)

#define	AMLI_RAMPRI_CCM_RAM5_Pri4 (0x4UL)

#define	AMLI_RAMPRI_CCM_RAM5_Pri6 (0x6UL)

#define	AMLI_RAMPRI_CCM_RAM5_Pri8 (0x8UL)

#define	AMLI_RAMPRI_CCM_RAM5_Pri10 (0xAUL)

#define	AMLI_RAMPRI_CCM_RAM5_Pri12 (0xCUL)

#define	AMLI_RAMPRI_CCM_RAM5_Pri14 (0xEUL)

#define	AMLI_RAMPRI_CCM_RAM4_Pos (16UL)

#define	AMLI_RAMPRI_CCM_RAM4_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM4_Pos)

#define	AMLI_RAMPRI_CCM_RAM4_Pri0 (0x0UL)

#define	AMLI_RAMPRI_CCM_RAM4_Pri2 (0x2UL)

#define	AMLI_RAMPRI_CCM_RAM4_Pri4 (0x4UL)

#define	AMLI_RAMPRI_CCM_RAM4_Pri6 (0x6UL)

#define	AMLI_RAMPRI_CCM_RAM4_Pri8 (0x8UL)

#define	AMLI_RAMPRI_CCM_RAM4_Pri10 (0xAUL)

#define	AMLI_RAMPRI_CCM_RAM4_Pri12 (0xCUL)

#define	AMLI_RAMPRI_CCM_RAM4_Pri14 (0xEUL)

#define	AMLI_RAMPRI_CCM_RAM3_Pos (12UL)

#define	AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos)

#define	AMLI_RAMPRI_CCM_RAM3_Pri0 (0x0UL)

#define	AMLI_RAMPRI_CCM_RAM3_Pri2 (0x2UL)

#define	AMLI_RAMPRI_CCM_RAM3_Pri4 (0x4UL)

#define	AMLI_RAMPRI_CCM_RAM3_Pri6 (0x6UL)

#define	AMLI_RAMPRI_CCM_RAM3_Pri8 (0x8UL)

#define	AMLI_RAMPRI_CCM_RAM3_Pri10 (0xAUL)

#define	AMLI_RAMPRI_CCM_RAM3_Pri12 (0xCUL)

#define	AMLI_RAMPRI_CCM_RAM3_Pri14 (0xEUL)

#define	AMLI_RAMPRI_CCM_RAM2_Pos (8UL)

#define	AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos)

#define	AMLI_RAMPRI_CCM_RAM2_Pri0 (0x0UL)

#define	AMLI_RAMPRI_CCM_RAM2_Pri2 (0x2UL)

#define	AMLI_RAMPRI_CCM_RAM2_Pri4 (0x4UL)

#define	AMLI_RAMPRI_CCM_RAM2_Pri6 (0x6UL)

#define	AMLI_RAMPRI_CCM_RAM2_Pri8 (0x8UL)

#define	AMLI_RAMPRI_CCM_RAM2_Pri10 (0xAUL)

#define	AMLI_RAMPRI_CCM_RAM2_Pri12 (0xCUL)

#define	AMLI_RAMPRI_CCM_RAM2_Pri14 (0xEUL)

#define	AMLI_RAMPRI_CCM_RAM1_Pos (4UL)

#define	AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos)

#define	AMLI_RAMPRI_CCM_RAM1_Pri0 (0x0UL)

#define	AMLI_RAMPRI_CCM_RAM1_Pri2 (0x2UL)

#define	AMLI_RAMPRI_CCM_RAM1_Pri4 (0x4UL)

#define	AMLI_RAMPRI_CCM_RAM1_Pri6 (0x6UL)

#define	AMLI_RAMPRI_CCM_RAM1_Pri8 (0x8UL)

#define	AMLI_RAMPRI_CCM_RAM1_Pri10 (0xAUL)

#define	AMLI_RAMPRI_CCM_RAM1_Pri12 (0xCUL)

#define	AMLI_RAMPRI_CCM_RAM1_Pri14 (0xEUL)

#define	AMLI_RAMPRI_CCM_RAM0_Pos (0UL)

#define	AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos)

#define	AMLI_RAMPRI_CCM_RAM0_Pri0 (0x0UL)

#define	AMLI_RAMPRI_CCM_RAM0_Pri2 (0x2UL)

#define	AMLI_RAMPRI_CCM_RAM0_Pri4 (0x4UL)

#define	AMLI_RAMPRI_CCM_RAM0_Pri6 (0x6UL)

#define	AMLI_RAMPRI_CCM_RAM0_Pri8 (0x8UL)

#define	AMLI_RAMPRI_CCM_RAM0_Pri10 (0xAUL)

#define	AMLI_RAMPRI_CCM_RAM0_Pri12 (0xCUL)

#define	AMLI_RAMPRI_CCM_RAM0_Pri14 (0xEUL)

#define	AMLI_RAMPRI_AAR_RAM7_Pos (28UL)

#define	AMLI_RAMPRI_AAR_RAM7_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM7_Pos)

#define	AMLI_RAMPRI_AAR_RAM7_Pri0 (0x0UL)

#define	AMLI_RAMPRI_AAR_RAM7_Pri2 (0x2UL)

#define	AMLI_RAMPRI_AAR_RAM7_Pri4 (0x4UL)

#define	AMLI_RAMPRI_AAR_RAM7_Pri6 (0x6UL)

#define	AMLI_RAMPRI_AAR_RAM7_Pri8 (0x8UL)

#define	AMLI_RAMPRI_AAR_RAM7_Pri10 (0xAUL)

#define	AMLI_RAMPRI_AAR_RAM7_Pri12 (0xCUL)

#define	AMLI_RAMPRI_AAR_RAM7_Pri14 (0xEUL)

#define	AMLI_RAMPRI_AAR_RAM6_Pos (24UL)

#define	AMLI_RAMPRI_AAR_RAM6_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM6_Pos)

#define	AMLI_RAMPRI_AAR_RAM6_Pri0 (0x0UL)

#define	AMLI_RAMPRI_AAR_RAM6_Pri2 (0x2UL)

#define	AMLI_RAMPRI_AAR_RAM6_Pri4 (0x4UL)

#define	AMLI_RAMPRI_AAR_RAM6_Pri6 (0x6UL)

#define	AMLI_RAMPRI_AAR_RAM6_Pri8 (0x8UL)

#define	AMLI_RAMPRI_AAR_RAM6_Pri10 (0xAUL)

#define	AMLI_RAMPRI_AAR_RAM6_Pri12 (0xCUL)

#define	AMLI_RAMPRI_AAR_RAM6_Pri14 (0xEUL)

#define	AMLI_RAMPRI_AAR_RAM5_Pos (20UL)

#define	AMLI_RAMPRI_AAR_RAM5_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM5_Pos)

#define	AMLI_RAMPRI_AAR_RAM5_Pri0 (0x0UL)

#define	AMLI_RAMPRI_AAR_RAM5_Pri2 (0x2UL)

#define	AMLI_RAMPRI_AAR_RAM5_Pri4 (0x4UL)

#define	AMLI_RAMPRI_AAR_RAM5_Pri6 (0x6UL)

#define	AMLI_RAMPRI_AAR_RAM5_Pri8 (0x8UL)

#define	AMLI_RAMPRI_AAR_RAM5_Pri10 (0xAUL)

#define	AMLI_RAMPRI_AAR_RAM5_Pri12 (0xCUL)

#define	AMLI_RAMPRI_AAR_RAM5_Pri14 (0xEUL)

#define	AMLI_RAMPRI_AAR_RAM4_Pos (16UL)

#define	AMLI_RAMPRI_AAR_RAM4_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM4_Pos)

#define	AMLI_RAMPRI_AAR_RAM4_Pri0 (0x0UL)

#define	AMLI_RAMPRI_AAR_RAM4_Pri2 (0x2UL)

#define	AMLI_RAMPRI_AAR_RAM4_Pri4 (0x4UL)

#define	AMLI_RAMPRI_AAR_RAM4_Pri6 (0x6UL)

#define	AMLI_RAMPRI_AAR_RAM4_Pri8 (0x8UL)

#define	AMLI_RAMPRI_AAR_RAM4_Pri10 (0xAUL)

#define	AMLI_RAMPRI_AAR_RAM4_Pri12 (0xCUL)

#define	AMLI_RAMPRI_AAR_RAM4_Pri14 (0xEUL)

#define	AMLI_RAMPRI_AAR_RAM3_Pos (12UL)

#define	AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos)

#define	AMLI_RAMPRI_AAR_RAM3_Pri0 (0x0UL)

#define	AMLI_RAMPRI_AAR_RAM3_Pri2 (0x2UL)

#define	AMLI_RAMPRI_AAR_RAM3_Pri4 (0x4UL)

#define	AMLI_RAMPRI_AAR_RAM3_Pri6 (0x6UL)

#define	AMLI_RAMPRI_AAR_RAM3_Pri8 (0x8UL)

#define	AMLI_RAMPRI_AAR_RAM3_Pri10 (0xAUL)

#define	AMLI_RAMPRI_AAR_RAM3_Pri12 (0xCUL)

#define	AMLI_RAMPRI_AAR_RAM3_Pri14 (0xEUL)

#define	AMLI_RAMPRI_AAR_RAM2_Pos (8UL)

#define	AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos)

#define	AMLI_RAMPRI_AAR_RAM2_Pri0 (0x0UL)

#define	AMLI_RAMPRI_AAR_RAM2_Pri2 (0x2UL)

#define	AMLI_RAMPRI_AAR_RAM2_Pri4 (0x4UL)

#define	AMLI_RAMPRI_AAR_RAM2_Pri6 (0x6UL)

#define	AMLI_RAMPRI_AAR_RAM2_Pri8 (0x8UL)

#define	AMLI_RAMPRI_AAR_RAM2_Pri10 (0xAUL)

#define	AMLI_RAMPRI_AAR_RAM2_Pri12 (0xCUL)

#define	AMLI_RAMPRI_AAR_RAM2_Pri14 (0xEUL)

#define	AMLI_RAMPRI_AAR_RAM1_Pos (4UL)

#define	AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos)

#define	AMLI_RAMPRI_AAR_RAM1_Pri0 (0x0UL)

#define	AMLI_RAMPRI_AAR_RAM1_Pri2 (0x2UL)

#define	AMLI_RAMPRI_AAR_RAM1_Pri4 (0x4UL)

#define	AMLI_RAMPRI_AAR_RAM1_Pri6 (0x6UL)

#define	AMLI_RAMPRI_AAR_RAM1_Pri8 (0x8UL)

#define	AMLI_RAMPRI_AAR_RAM1_Pri10 (0xAUL)

#define	AMLI_RAMPRI_AAR_RAM1_Pri12 (0xCUL)

#define	AMLI_RAMPRI_AAR_RAM1_Pri14 (0xEUL)

#define	AMLI_RAMPRI_AAR_RAM0_Pos (0UL)

#define	AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos)

#define	AMLI_RAMPRI_AAR_RAM0_Pri0 (0x0UL)

#define	AMLI_RAMPRI_AAR_RAM0_Pri2 (0x2UL)

#define	AMLI_RAMPRI_AAR_RAM0_Pri4 (0x4UL)

#define	AMLI_RAMPRI_AAR_RAM0_Pri6 (0x6UL)

#define	AMLI_RAMPRI_AAR_RAM0_Pri8 (0x8UL)

#define	AMLI_RAMPRI_AAR_RAM0_Pri10 (0xAUL)

#define	AMLI_RAMPRI_AAR_RAM0_Pri12 (0xCUL)

#define	AMLI_RAMPRI_AAR_RAM0_Pri14 (0xEUL)

#define	CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL)

#define	CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos)

#define	CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL)

#define	CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL)

#define	CCM_INTENSET_ERROR_Pos (2UL)

#define	CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos)

#define	CCM_INTENSET_ERROR_Disabled (0UL)

#define	CCM_INTENSET_ERROR_Enabled (1UL)

#define	CCM_INTENSET_ERROR_Set (1UL)

#define	CCM_INTENSET_ENDCRYPT_Pos (1UL)

#define	CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos)

#define	CCM_INTENSET_ENDCRYPT_Disabled (0UL)

#define	CCM_INTENSET_ENDCRYPT_Enabled (1UL)

#define	CCM_INTENSET_ENDCRYPT_Set (1UL)

#define	CCM_INTENSET_ENDKSGEN_Pos (0UL)

#define	CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos)

#define	CCM_INTENSET_ENDKSGEN_Disabled (0UL)

#define	CCM_INTENSET_ENDKSGEN_Enabled (1UL)

#define	CCM_INTENSET_ENDKSGEN_Set (1UL)

#define	CCM_INTENCLR_ERROR_Pos (2UL)

#define	CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos)

#define	CCM_INTENCLR_ERROR_Disabled (0UL)

#define	CCM_INTENCLR_ERROR_Enabled (1UL)

#define	CCM_INTENCLR_ERROR_Clear (1UL)

#define	CCM_INTENCLR_ENDCRYPT_Pos (1UL)

#define	CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos)

#define	CCM_INTENCLR_ENDCRYPT_Disabled (0UL)

#define	CCM_INTENCLR_ENDCRYPT_Enabled (1UL)

#define	CCM_INTENCLR_ENDCRYPT_Clear (1UL)

#define	CCM_INTENCLR_ENDKSGEN_Pos (0UL)

#define	CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos)

#define	CCM_INTENCLR_ENDKSGEN_Disabled (0UL)

#define	CCM_INTENCLR_ENDKSGEN_Enabled (1UL)

#define	CCM_INTENCLR_ENDKSGEN_Clear (1UL)

#define	CCM_MICSTATUS_MICSTATUS_Pos (0UL)

#define	CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos)

#define	CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL)

#define	CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL)

#define	CCM_ENABLE_ENABLE_Pos (0UL)

#define	CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos)

#define	CCM_ENABLE_ENABLE_Disabled (0x00UL)

#define	CCM_ENABLE_ENABLE_Enabled (0x02UL)

#define	CCM_MODE_MODE_Pos (0UL)

#define	CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos)

#define	CCM_MODE_MODE_Encryption (0UL)

#define	CCM_MODE_MODE_Decryption (1UL)

#define	CCM_POWER_POWER_Pos (0UL)

#define	CCM_POWER_POWER_Msk (0x1UL << CCM_POWER_POWER_Pos)

#define	CCM_POWER_POWER_Disabled (0UL)

#define	CCM_POWER_POWER_Enabled (1UL)

#define	CLOCK_INTENSET_CTTO_Pos (4UL)

#define	CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos)

#define	CLOCK_INTENSET_CTTO_Disabled (0UL)

#define	CLOCK_INTENSET_CTTO_Enabled (1UL)

#define	CLOCK_INTENSET_CTTO_Set (1UL)

#define	CLOCK_INTENSET_DONE_Pos (3UL)

#define	CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos)

#define	CLOCK_INTENSET_DONE_Disabled (0UL)

#define	CLOCK_INTENSET_DONE_Enabled (1UL)

#define	CLOCK_INTENSET_DONE_Set (1UL)

#define	CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL)

#define	CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos)

#define	CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL)

#define	CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL)

#define	CLOCK_INTENSET_LFCLKSTARTED_Set (1UL)

#define	CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL)

#define	CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos)

#define	CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL)

#define	CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL)

#define	CLOCK_INTENSET_HFCLKSTARTED_Set (1UL)

#define	CLOCK_INTENCLR_CTTO_Pos (4UL)

#define	CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos)

#define	CLOCK_INTENCLR_CTTO_Disabled (0UL)

#define	CLOCK_INTENCLR_CTTO_Enabled (1UL)

#define	CLOCK_INTENCLR_CTTO_Clear (1UL)

#define	CLOCK_INTENCLR_DONE_Pos (3UL)

#define	CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos)

#define	CLOCK_INTENCLR_DONE_Disabled (0UL)

#define	CLOCK_INTENCLR_DONE_Enabled (1UL)

#define	CLOCK_INTENCLR_DONE_Clear (1UL)

#define	CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL)

#define	CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos)

#define	CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL)

#define	CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL)

#define	CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL)

#define	CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL)

#define	CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos)

#define	CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL)

#define	CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL)

#define	CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL)

#define	CLOCK_HFCLKRUN_STATUS_Pos (0UL)

#define	CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos)

#define	CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL)

#define	CLOCK_HFCLKRUN_STATUS_Triggered (1UL)

#define	CLOCK_HFCLKSTAT_STATE_Pos (16UL)

#define	CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos)

#define	CLOCK_HFCLKSTAT_STATE_NotRunning (0UL)

#define	CLOCK_HFCLKSTAT_STATE_Running (1UL)

#define	CLOCK_HFCLKSTAT_SRC_Pos (0UL)

#define	CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos)

#define	CLOCK_HFCLKSTAT_SRC_RC (0UL)

#define	CLOCK_HFCLKSTAT_SRC_Xtal (1UL)

#define	CLOCK_LFCLKRUN_STATUS_Pos (0UL)

#define	CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos)

#define	CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL)

#define	CLOCK_LFCLKRUN_STATUS_Triggered (1UL)

#define	CLOCK_LFCLKSTAT_STATE_Pos (16UL)

#define	CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos)

#define	CLOCK_LFCLKSTAT_STATE_NotRunning (0UL)

#define	CLOCK_LFCLKSTAT_STATE_Running (1UL)

#define	CLOCK_LFCLKSTAT_SRC_Pos (0UL)

#define	CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos)

#define	CLOCK_LFCLKSTAT_SRC_RC (0UL)

#define	CLOCK_LFCLKSTAT_SRC_Xtal (1UL)

#define	CLOCK_LFCLKSTAT_SRC_Synth (2UL)

#define	CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL)

#define	CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos)

#define	CLOCK_LFCLKSRCCOPY_SRC_RC (0UL)

#define	CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL)

#define	CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL)

#define	CLOCK_LFCLKSRC_SRC_Pos (0UL)

#define	CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos)

#define	CLOCK_LFCLKSRC_SRC_RC (0UL)

#define	CLOCK_LFCLKSRC_SRC_Xtal (1UL)

#define	CLOCK_LFCLKSRC_SRC_Synth (2UL)

#define	CLOCK_CTIV_CTIV_Pos (0UL)

#define	CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos)

#define	CLOCK_XTALFREQ_XTALFREQ_Pos (0UL)

#define	CLOCK_XTALFREQ_XTALFREQ_Msk (0xFFUL << CLOCK_XTALFREQ_XTALFREQ_Pos)

#define	CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL)

#define	CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL)

#define	ECB_INTENSET_ERRORECB_Pos (1UL)

#define	ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos)

#define	ECB_INTENSET_ERRORECB_Disabled (0UL)

#define	ECB_INTENSET_ERRORECB_Enabled (1UL)

#define	ECB_INTENSET_ERRORECB_Set (1UL)

#define	ECB_INTENSET_ENDECB_Pos (0UL)

#define	ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos)

#define	ECB_INTENSET_ENDECB_Disabled (0UL)

#define	ECB_INTENSET_ENDECB_Enabled (1UL)

#define	ECB_INTENSET_ENDECB_Set (1UL)

#define	ECB_INTENCLR_ERRORECB_Pos (1UL)

#define	ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos)

#define	ECB_INTENCLR_ERRORECB_Disabled (0UL)

#define	ECB_INTENCLR_ERRORECB_Enabled (1UL)

#define	ECB_INTENCLR_ERRORECB_Clear (1UL)

#define	ECB_INTENCLR_ENDECB_Pos (0UL)

#define	ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos)

#define	ECB_INTENCLR_ENDECB_Disabled (0UL)

#define	ECB_INTENCLR_ENDECB_Enabled (1UL)

#define	ECB_INTENCLR_ENDECB_Clear (1UL)

#define	ECB_POWER_POWER_Pos (0UL)

#define	ECB_POWER_POWER_Msk (0x1UL << ECB_POWER_POWER_Pos)

#define	ECB_POWER_POWER_Disabled (0UL)

#define	ECB_POWER_POWER_Enabled (1UL)

#define	FICR_PPFC_PPFC_Pos (0UL)

#define	FICR_PPFC_PPFC_Msk (0xFFUL << FICR_PPFC_PPFC_Pos)

#define	FICR_PPFC_PPFC_Present (0x00UL)

#define	FICR_PPFC_PPFC_NotPresent (0xFFUL)

#define	FICR_CONFIGID_FWID_Pos (16UL)

#define	FICR_CONFIGID_FWID_Msk (0xFFFFUL << FICR_CONFIGID_FWID_Pos)

#define	FICR_CONFIGID_HWID_Pos (0UL)

#define	FICR_CONFIGID_HWID_Msk (0xFFFFUL << FICR_CONFIGID_HWID_Pos)

#define	FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL)

#define	FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos)

#define	FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL)

#define	FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL)

#define	FICR_OVERRIDEEN_BLE_1MBIT_Pos (3UL)

#define	FICR_OVERRIDEEN_BLE_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_BLE_1MBIT_Pos)

#define	FICR_OVERRIDEEN_BLE_1MBIT_Override (0UL)

#define	FICR_OVERRIDEEN_BLE_1MBIT_NotOverride (1UL)

#define	FICR_OVERRIDEEN_NRF_1MBIT_Pos (0UL)

#define	FICR_OVERRIDEEN_NRF_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_NRF_1MBIT_Pos)

#define	FICR_OVERRIDEEN_NRF_1MBIT_Override (0UL)

#define	FICR_OVERRIDEEN_NRF_1MBIT_NotOverride (1UL)

#define	GPIO_OUT_PIN31_Pos (31UL)

#define	GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos)

#define	GPIO_OUT_PIN31_Low (0UL)

#define	GPIO_OUT_PIN31_High (1UL)

#define	GPIO_OUT_PIN30_Pos (30UL)

#define	GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos)

#define	GPIO_OUT_PIN30_Low (0UL)

#define	GPIO_OUT_PIN30_High (1UL)

#define	GPIO_OUT_PIN29_Pos (29UL)

#define	GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos)

#define	GPIO_OUT_PIN29_Low (0UL)

#define	GPIO_OUT_PIN29_High (1UL)

#define	GPIO_OUT_PIN28_Pos (28UL)

#define	GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos)

#define	GPIO_OUT_PIN28_Low (0UL)

#define	GPIO_OUT_PIN28_High (1UL)

#define	GPIO_OUT_PIN27_Pos (27UL)

#define	GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos)

#define	GPIO_OUT_PIN27_Low (0UL)

#define	GPIO_OUT_PIN27_High (1UL)

#define	GPIO_OUT_PIN26_Pos (26UL)

#define	GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos)

#define	GPIO_OUT_PIN26_Low (0UL)

#define	GPIO_OUT_PIN26_High (1UL)

#define	GPIO_OUT_PIN25_Pos (25UL)

#define	GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos)

#define	GPIO_OUT_PIN25_Low (0UL)

#define	GPIO_OUT_PIN25_High (1UL)

#define	GPIO_OUT_PIN24_Pos (24UL)

#define	GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos)

#define	GPIO_OUT_PIN24_Low (0UL)

#define	GPIO_OUT_PIN24_High (1UL)

#define	GPIO_OUT_PIN23_Pos (23UL)

#define	GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos)

#define	GPIO_OUT_PIN23_Low (0UL)

#define	GPIO_OUT_PIN23_High (1UL)

#define	GPIO_OUT_PIN22_Pos (22UL)

#define	GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos)

#define	GPIO_OUT_PIN22_Low (0UL)

#define	GPIO_OUT_PIN22_High (1UL)

#define	GPIO_OUT_PIN21_Pos (21UL)

#define	GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos)

#define	GPIO_OUT_PIN21_Low (0UL)

#define	GPIO_OUT_PIN21_High (1UL)

#define	GPIO_OUT_PIN20_Pos (20UL)

#define	GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos)

#define	GPIO_OUT_PIN20_Low (0UL)

#define	GPIO_OUT_PIN20_High (1UL)

#define	GPIO_OUT_PIN19_Pos (19UL)

#define	GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos)

#define	GPIO_OUT_PIN19_Low (0UL)

#define	GPIO_OUT_PIN19_High (1UL)

#define	GPIO_OUT_PIN18_Pos (18UL)

#define	GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos)

#define	GPIO_OUT_PIN18_Low (0UL)

#define	GPIO_OUT_PIN18_High (1UL)

#define	GPIO_OUT_PIN17_Pos (17UL)

#define	GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos)

#define	GPIO_OUT_PIN17_Low (0UL)

#define	GPIO_OUT_PIN17_High (1UL)

#define	GPIO_OUT_PIN16_Pos (16UL)

#define	GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos)

#define	GPIO_OUT_PIN16_Low (0UL)

#define	GPIO_OUT_PIN16_High (1UL)

#define	GPIO_OUT_PIN15_Pos (15UL)

#define	GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos)

#define	GPIO_OUT_PIN15_Low (0UL)

#define	GPIO_OUT_PIN15_High (1UL)

#define	GPIO_OUT_PIN14_Pos (14UL)

#define	GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos)

#define	GPIO_OUT_PIN14_Low (0UL)

#define	GPIO_OUT_PIN14_High (1UL)

#define	GPIO_OUT_PIN13_Pos (13UL)

#define	GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos)

#define	GPIO_OUT_PIN13_Low (0UL)

#define	GPIO_OUT_PIN13_High (1UL)

#define	GPIO_OUT_PIN12_Pos (12UL)

#define	GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos)

#define	GPIO_OUT_PIN12_Low (0UL)

#define	GPIO_OUT_PIN12_High (1UL)

#define	GPIO_OUT_PIN11_Pos (11UL)

#define	GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos)

#define	GPIO_OUT_PIN11_Low (0UL)

#define	GPIO_OUT_PIN11_High (1UL)

#define	GPIO_OUT_PIN10_Pos (10UL)

#define	GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos)

#define	GPIO_OUT_PIN10_Low (0UL)

#define	GPIO_OUT_PIN10_High (1UL)

#define	GPIO_OUT_PIN9_Pos (9UL)

#define	GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos)

#define	GPIO_OUT_PIN9_Low (0UL)

#define	GPIO_OUT_PIN9_High (1UL)

#define	GPIO_OUT_PIN8_Pos (8UL)

#define	GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos)

#define	GPIO_OUT_PIN8_Low (0UL)

#define	GPIO_OUT_PIN8_High (1UL)

#define	GPIO_OUT_PIN7_Pos (7UL)

#define	GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos)

#define	GPIO_OUT_PIN7_Low (0UL)

#define	GPIO_OUT_PIN7_High (1UL)

#define	GPIO_OUT_PIN6_Pos (6UL)

#define	GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos)

#define	GPIO_OUT_PIN6_Low (0UL)

#define	GPIO_OUT_PIN6_High (1UL)

#define	GPIO_OUT_PIN5_Pos (5UL)

#define	GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos)

#define	GPIO_OUT_PIN5_Low (0UL)

#define	GPIO_OUT_PIN5_High (1UL)

#define	GPIO_OUT_PIN4_Pos (4UL)

#define	GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos)

#define	GPIO_OUT_PIN4_Low (0UL)

#define	GPIO_OUT_PIN4_High (1UL)

#define	GPIO_OUT_PIN3_Pos (3UL)

#define	GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos)

#define	GPIO_OUT_PIN3_Low (0UL)

#define	GPIO_OUT_PIN3_High (1UL)

#define	GPIO_OUT_PIN2_Pos (2UL)

#define	GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos)

#define	GPIO_OUT_PIN2_Low (0UL)

#define	GPIO_OUT_PIN2_High (1UL)

#define	GPIO_OUT_PIN1_Pos (1UL)

#define	GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos)

#define	GPIO_OUT_PIN1_Low (0UL)

#define	GPIO_OUT_PIN1_High (1UL)

#define	GPIO_OUT_PIN0_Pos (0UL)

#define	GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos)

#define	GPIO_OUT_PIN0_Low (0UL)

#define	GPIO_OUT_PIN0_High (1UL)

#define	GPIO_OUTSET_PIN31_Pos (31UL)

#define	GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos)

#define	GPIO_OUTSET_PIN31_Low (0UL)

#define	GPIO_OUTSET_PIN31_High (1UL)

#define	GPIO_OUTSET_PIN31_Set (1UL)

#define	GPIO_OUTSET_PIN30_Pos (30UL)

#define	GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos)

#define	GPIO_OUTSET_PIN30_Low (0UL)

#define	GPIO_OUTSET_PIN30_High (1UL)

#define	GPIO_OUTSET_PIN30_Set (1UL)

#define	GPIO_OUTSET_PIN29_Pos (29UL)

#define	GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos)

#define	GPIO_OUTSET_PIN29_Low (0UL)

#define	GPIO_OUTSET_PIN29_High (1UL)

#define	GPIO_OUTSET_PIN29_Set (1UL)

#define	GPIO_OUTSET_PIN28_Pos (28UL)

#define	GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos)

#define	GPIO_OUTSET_PIN28_Low (0UL)

#define	GPIO_OUTSET_PIN28_High (1UL)

#define	GPIO_OUTSET_PIN28_Set (1UL)

#define	GPIO_OUTSET_PIN27_Pos (27UL)

#define	GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos)

#define	GPIO_OUTSET_PIN27_Low (0UL)

#define	GPIO_OUTSET_PIN27_High (1UL)

#define	GPIO_OUTSET_PIN27_Set (1UL)

#define	GPIO_OUTSET_PIN26_Pos (26UL)

#define	GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos)

#define	GPIO_OUTSET_PIN26_Low (0UL)

#define	GPIO_OUTSET_PIN26_High (1UL)

#define	GPIO_OUTSET_PIN26_Set (1UL)

#define	GPIO_OUTSET_PIN25_Pos (25UL)

#define	GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos)

#define	GPIO_OUTSET_PIN25_Low (0UL)

#define	GPIO_OUTSET_PIN25_High (1UL)

#define	GPIO_OUTSET_PIN25_Set (1UL)

#define	GPIO_OUTSET_PIN24_Pos (24UL)

#define	GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos)

#define	GPIO_OUTSET_PIN24_Low (0UL)

#define	GPIO_OUTSET_PIN24_High (1UL)

#define	GPIO_OUTSET_PIN24_Set (1UL)

#define	GPIO_OUTSET_PIN23_Pos (23UL)

#define	GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos)

#define	GPIO_OUTSET_PIN23_Low (0UL)

#define	GPIO_OUTSET_PIN23_High (1UL)

#define	GPIO_OUTSET_PIN23_Set (1UL)

#define	GPIO_OUTSET_PIN22_Pos (22UL)

#define	GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos)

#define	GPIO_OUTSET_PIN22_Low (0UL)

#define	GPIO_OUTSET_PIN22_High (1UL)

#define	GPIO_OUTSET_PIN22_Set (1UL)

#define	GPIO_OUTSET_PIN21_Pos (21UL)

#define	GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos)

#define	GPIO_OUTSET_PIN21_Low (0UL)

#define	GPIO_OUTSET_PIN21_High (1UL)

#define	GPIO_OUTSET_PIN21_Set (1UL)

#define	GPIO_OUTSET_PIN20_Pos (20UL)

#define	GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos)

#define	GPIO_OUTSET_PIN20_Low (0UL)

#define	GPIO_OUTSET_PIN20_High (1UL)

#define	GPIO_OUTSET_PIN20_Set (1UL)

#define	GPIO_OUTSET_PIN19_Pos (19UL)

#define	GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos)

#define	GPIO_OUTSET_PIN19_Low (0UL)

#define	GPIO_OUTSET_PIN19_High (1UL)

#define	GPIO_OUTSET_PIN19_Set (1UL)

#define	GPIO_OUTSET_PIN18_Pos (18UL)

#define	GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos)

#define	GPIO_OUTSET_PIN18_Low (0UL)

#define	GPIO_OUTSET_PIN18_High (1UL)

#define	GPIO_OUTSET_PIN18_Set (1UL)

#define	GPIO_OUTSET_PIN17_Pos (17UL)

#define	GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos)

#define	GPIO_OUTSET_PIN17_Low (0UL)

#define	GPIO_OUTSET_PIN17_High (1UL)

#define	GPIO_OUTSET_PIN17_Set (1UL)

#define	GPIO_OUTSET_PIN16_Pos (16UL)

#define	GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos)

#define	GPIO_OUTSET_PIN16_Low (0UL)

#define	GPIO_OUTSET_PIN16_High (1UL)

#define	GPIO_OUTSET_PIN16_Set (1UL)

#define	GPIO_OUTSET_PIN15_Pos (15UL)

#define	GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos)

#define	GPIO_OUTSET_PIN15_Low (0UL)

#define	GPIO_OUTSET_PIN15_High (1UL)

#define	GPIO_OUTSET_PIN15_Set (1UL)

#define	GPIO_OUTSET_PIN14_Pos (14UL)

#define	GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos)

#define	GPIO_OUTSET_PIN14_Low (0UL)

#define	GPIO_OUTSET_PIN14_High (1UL)

#define	GPIO_OUTSET_PIN14_Set (1UL)

#define	GPIO_OUTSET_PIN13_Pos (13UL)

#define	GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos)

#define	GPIO_OUTSET_PIN13_Low (0UL)

#define	GPIO_OUTSET_PIN13_High (1UL)

#define	GPIO_OUTSET_PIN13_Set (1UL)

#define	GPIO_OUTSET_PIN12_Pos (12UL)

#define	GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos)

#define	GPIO_OUTSET_PIN12_Low (0UL)

#define	GPIO_OUTSET_PIN12_High (1UL)

#define	GPIO_OUTSET_PIN12_Set (1UL)

#define	GPIO_OUTSET_PIN11_Pos (11UL)

#define	GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos)

#define	GPIO_OUTSET_PIN11_Low (0UL)

#define	GPIO_OUTSET_PIN11_High (1UL)

#define	GPIO_OUTSET_PIN11_Set (1UL)

#define	GPIO_OUTSET_PIN10_Pos (10UL)

#define	GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos)

#define	GPIO_OUTSET_PIN10_Low (0UL)

#define	GPIO_OUTSET_PIN10_High (1UL)

#define	GPIO_OUTSET_PIN10_Set (1UL)

#define	GPIO_OUTSET_PIN9_Pos (9UL)

#define	GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos)

#define	GPIO_OUTSET_PIN9_Low (0UL)

#define	GPIO_OUTSET_PIN9_High (1UL)

#define	GPIO_OUTSET_PIN9_Set (1UL)

#define	GPIO_OUTSET_PIN8_Pos (8UL)

#define	GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos)

#define	GPIO_OUTSET_PIN8_Low (0UL)

#define	GPIO_OUTSET_PIN8_High (1UL)

#define	GPIO_OUTSET_PIN8_Set (1UL)

#define	GPIO_OUTSET_PIN7_Pos (7UL)

#define	GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos)

#define	GPIO_OUTSET_PIN7_Low (0UL)

#define	GPIO_OUTSET_PIN7_High (1UL)

#define	GPIO_OUTSET_PIN7_Set (1UL)

#define	GPIO_OUTSET_PIN6_Pos (6UL)

#define	GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos)

#define	GPIO_OUTSET_PIN6_Low (0UL)

#define	GPIO_OUTSET_PIN6_High (1UL)

#define	GPIO_OUTSET_PIN6_Set (1UL)

#define	GPIO_OUTSET_PIN5_Pos (5UL)

#define	GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos)

#define	GPIO_OUTSET_PIN5_Low (0UL)

#define	GPIO_OUTSET_PIN5_High (1UL)

#define	GPIO_OUTSET_PIN5_Set (1UL)

#define	GPIO_OUTSET_PIN4_Pos (4UL)

#define	GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos)

#define	GPIO_OUTSET_PIN4_Low (0UL)

#define	GPIO_OUTSET_PIN4_High (1UL)

#define	GPIO_OUTSET_PIN4_Set (1UL)

#define	GPIO_OUTSET_PIN3_Pos (3UL)

#define	GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos)

#define	GPIO_OUTSET_PIN3_Low (0UL)

#define	GPIO_OUTSET_PIN3_High (1UL)

#define	GPIO_OUTSET_PIN3_Set (1UL)

#define	GPIO_OUTSET_PIN2_Pos (2UL)

#define	GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos)

#define	GPIO_OUTSET_PIN2_Low (0UL)

#define	GPIO_OUTSET_PIN2_High (1UL)

#define	GPIO_OUTSET_PIN2_Set (1UL)

#define	GPIO_OUTSET_PIN1_Pos (1UL)

#define	GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos)

#define	GPIO_OUTSET_PIN1_Low (0UL)

#define	GPIO_OUTSET_PIN1_High (1UL)

#define	GPIO_OUTSET_PIN1_Set (1UL)

#define	GPIO_OUTSET_PIN0_Pos (0UL)

#define	GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos)

#define	GPIO_OUTSET_PIN0_Low (0UL)

#define	GPIO_OUTSET_PIN0_High (1UL)

#define	GPIO_OUTSET_PIN0_Set (1UL)

#define	GPIO_OUTCLR_PIN31_Pos (31UL)

#define	GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos)

#define	GPIO_OUTCLR_PIN31_Low (0UL)

#define	GPIO_OUTCLR_PIN31_High (1UL)

#define	GPIO_OUTCLR_PIN31_Clear (1UL)

#define	GPIO_OUTCLR_PIN30_Pos (30UL)

#define	GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos)

#define	GPIO_OUTCLR_PIN30_Low (0UL)

#define	GPIO_OUTCLR_PIN30_High (1UL)

#define	GPIO_OUTCLR_PIN30_Clear (1UL)

#define	GPIO_OUTCLR_PIN29_Pos (29UL)

#define	GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos)

#define	GPIO_OUTCLR_PIN29_Low (0UL)

#define	GPIO_OUTCLR_PIN29_High (1UL)

#define	GPIO_OUTCLR_PIN29_Clear (1UL)

#define	GPIO_OUTCLR_PIN28_Pos (28UL)

#define	GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos)

#define	GPIO_OUTCLR_PIN28_Low (0UL)

#define	GPIO_OUTCLR_PIN28_High (1UL)

#define	GPIO_OUTCLR_PIN28_Clear (1UL)

#define	GPIO_OUTCLR_PIN27_Pos (27UL)

#define	GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos)

#define	GPIO_OUTCLR_PIN27_Low (0UL)

#define	GPIO_OUTCLR_PIN27_High (1UL)

#define	GPIO_OUTCLR_PIN27_Clear (1UL)

#define	GPIO_OUTCLR_PIN26_Pos (26UL)

#define	GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos)

#define	GPIO_OUTCLR_PIN26_Low (0UL)

#define	GPIO_OUTCLR_PIN26_High (1UL)

#define	GPIO_OUTCLR_PIN26_Clear (1UL)

#define	GPIO_OUTCLR_PIN25_Pos (25UL)

#define	GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos)

#define	GPIO_OUTCLR_PIN25_Low (0UL)

#define	GPIO_OUTCLR_PIN25_High (1UL)

#define	GPIO_OUTCLR_PIN25_Clear (1UL)

#define	GPIO_OUTCLR_PIN24_Pos (24UL)

#define	GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos)

#define	GPIO_OUTCLR_PIN24_Low (0UL)

#define	GPIO_OUTCLR_PIN24_High (1UL)

#define	GPIO_OUTCLR_PIN24_Clear (1UL)

#define	GPIO_OUTCLR_PIN23_Pos (23UL)

#define	GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos)

#define	GPIO_OUTCLR_PIN23_Low (0UL)

#define	GPIO_OUTCLR_PIN23_High (1UL)

#define	GPIO_OUTCLR_PIN23_Clear (1UL)

#define	GPIO_OUTCLR_PIN22_Pos (22UL)

#define	GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos)

#define	GPIO_OUTCLR_PIN22_Low (0UL)

#define	GPIO_OUTCLR_PIN22_High (1UL)

#define	GPIO_OUTCLR_PIN22_Clear (1UL)

#define	GPIO_OUTCLR_PIN21_Pos (21UL)

#define	GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos)

#define	GPIO_OUTCLR_PIN21_Low (0UL)

#define	GPIO_OUTCLR_PIN21_High (1UL)

#define	GPIO_OUTCLR_PIN21_Clear (1UL)

#define	GPIO_OUTCLR_PIN20_Pos (20UL)

#define	GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos)

#define	GPIO_OUTCLR_PIN20_Low (0UL)

#define	GPIO_OUTCLR_PIN20_High (1UL)

#define	GPIO_OUTCLR_PIN20_Clear (1UL)

#define	GPIO_OUTCLR_PIN19_Pos (19UL)

#define	GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos)

#define	GPIO_OUTCLR_PIN19_Low (0UL)

#define	GPIO_OUTCLR_PIN19_High (1UL)

#define	GPIO_OUTCLR_PIN19_Clear (1UL)

#define	GPIO_OUTCLR_PIN18_Pos (18UL)

#define	GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos)

#define	GPIO_OUTCLR_PIN18_Low (0UL)

#define	GPIO_OUTCLR_PIN18_High (1UL)

#define	GPIO_OUTCLR_PIN18_Clear (1UL)

#define	GPIO_OUTCLR_PIN17_Pos (17UL)

#define	GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos)

#define	GPIO_OUTCLR_PIN17_Low (0UL)

#define	GPIO_OUTCLR_PIN17_High (1UL)

#define	GPIO_OUTCLR_PIN17_Clear (1UL)

#define	GPIO_OUTCLR_PIN16_Pos (16UL)

#define	GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos)

#define	GPIO_OUTCLR_PIN16_Low (0UL)

#define	GPIO_OUTCLR_PIN16_High (1UL)

#define	GPIO_OUTCLR_PIN16_Clear (1UL)

#define	GPIO_OUTCLR_PIN15_Pos (15UL)

#define	GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos)

#define	GPIO_OUTCLR_PIN15_Low (0UL)

#define	GPIO_OUTCLR_PIN15_High (1UL)

#define	GPIO_OUTCLR_PIN15_Clear (1UL)

#define	GPIO_OUTCLR_PIN14_Pos (14UL)

#define	GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos)

#define	GPIO_OUTCLR_PIN14_Low (0UL)

#define	GPIO_OUTCLR_PIN14_High (1UL)

#define	GPIO_OUTCLR_PIN14_Clear (1UL)

#define	GPIO_OUTCLR_PIN13_Pos (13UL)

#define	GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos)

#define	GPIO_OUTCLR_PIN13_Low (0UL)

#define	GPIO_OUTCLR_PIN13_High (1UL)

#define	GPIO_OUTCLR_PIN13_Clear (1UL)

#define	GPIO_OUTCLR_PIN12_Pos (12UL)

#define	GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos)

#define	GPIO_OUTCLR_PIN12_Low (0UL)

#define	GPIO_OUTCLR_PIN12_High (1UL)

#define	GPIO_OUTCLR_PIN12_Clear (1UL)

#define	GPIO_OUTCLR_PIN11_Pos (11UL)

#define	GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos)

#define	GPIO_OUTCLR_PIN11_Low (0UL)

#define	GPIO_OUTCLR_PIN11_High (1UL)

#define	GPIO_OUTCLR_PIN11_Clear (1UL)

#define	GPIO_OUTCLR_PIN10_Pos (10UL)

#define	GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos)

#define	GPIO_OUTCLR_PIN10_Low (0UL)

#define	GPIO_OUTCLR_PIN10_High (1UL)

#define	GPIO_OUTCLR_PIN10_Clear (1UL)

#define	GPIO_OUTCLR_PIN9_Pos (9UL)

#define	GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos)

#define	GPIO_OUTCLR_PIN9_Low (0UL)

#define	GPIO_OUTCLR_PIN9_High (1UL)

#define	GPIO_OUTCLR_PIN9_Clear (1UL)

#define	GPIO_OUTCLR_PIN8_Pos (8UL)

#define	GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos)

#define	GPIO_OUTCLR_PIN8_Low (0UL)

#define	GPIO_OUTCLR_PIN8_High (1UL)

#define	GPIO_OUTCLR_PIN8_Clear (1UL)

#define	GPIO_OUTCLR_PIN7_Pos (7UL)

#define	GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos)

#define	GPIO_OUTCLR_PIN7_Low (0UL)

#define	GPIO_OUTCLR_PIN7_High (1UL)

#define	GPIO_OUTCLR_PIN7_Clear (1UL)

#define	GPIO_OUTCLR_PIN6_Pos (6UL)

#define	GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos)

#define	GPIO_OUTCLR_PIN6_Low (0UL)

#define	GPIO_OUTCLR_PIN6_High (1UL)

#define	GPIO_OUTCLR_PIN6_Clear (1UL)

#define	GPIO_OUTCLR_PIN5_Pos (5UL)

#define	GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos)

#define	GPIO_OUTCLR_PIN5_Low (0UL)

#define	GPIO_OUTCLR_PIN5_High (1UL)

#define	GPIO_OUTCLR_PIN5_Clear (1UL)

#define	GPIO_OUTCLR_PIN4_Pos (4UL)

#define	GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos)

#define	GPIO_OUTCLR_PIN4_Low (0UL)

#define	GPIO_OUTCLR_PIN4_High (1UL)

#define	GPIO_OUTCLR_PIN4_Clear (1UL)

#define	GPIO_OUTCLR_PIN3_Pos (3UL)

#define	GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos)

#define	GPIO_OUTCLR_PIN3_Low (0UL)

#define	GPIO_OUTCLR_PIN3_High (1UL)

#define	GPIO_OUTCLR_PIN3_Clear (1UL)

#define	GPIO_OUTCLR_PIN2_Pos (2UL)

#define	GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos)

#define	GPIO_OUTCLR_PIN2_Low (0UL)

#define	GPIO_OUTCLR_PIN2_High (1UL)

#define	GPIO_OUTCLR_PIN2_Clear (1UL)

#define	GPIO_OUTCLR_PIN1_Pos (1UL)

#define	GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos)

#define	GPIO_OUTCLR_PIN1_Low (0UL)

#define	GPIO_OUTCLR_PIN1_High (1UL)

#define	GPIO_OUTCLR_PIN1_Clear (1UL)

#define	GPIO_OUTCLR_PIN0_Pos (0UL)

#define	GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos)

#define	GPIO_OUTCLR_PIN0_Low (0UL)

#define	GPIO_OUTCLR_PIN0_High (1UL)

#define	GPIO_OUTCLR_PIN0_Clear (1UL)

#define	GPIO_IN_PIN31_Pos (31UL)

#define	GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos)

#define	GPIO_IN_PIN31_Low (0UL)

#define	GPIO_IN_PIN31_High (1UL)

#define	GPIO_IN_PIN30_Pos (30UL)

#define	GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos)

#define	GPIO_IN_PIN30_Low (0UL)

#define	GPIO_IN_PIN30_High (1UL)

#define	GPIO_IN_PIN29_Pos (29UL)

#define	GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos)

#define	GPIO_IN_PIN29_Low (0UL)

#define	GPIO_IN_PIN29_High (1UL)

#define	GPIO_IN_PIN28_Pos (28UL)

#define	GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos)

#define	GPIO_IN_PIN28_Low (0UL)

#define	GPIO_IN_PIN28_High (1UL)

#define	GPIO_IN_PIN27_Pos (27UL)

#define	GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos)

#define	GPIO_IN_PIN27_Low (0UL)

#define	GPIO_IN_PIN27_High (1UL)

#define	GPIO_IN_PIN26_Pos (26UL)

#define	GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos)

#define	GPIO_IN_PIN26_Low (0UL)

#define	GPIO_IN_PIN26_High (1UL)

#define	GPIO_IN_PIN25_Pos (25UL)

#define	GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos)

#define	GPIO_IN_PIN25_Low (0UL)

#define	GPIO_IN_PIN25_High (1UL)

#define	GPIO_IN_PIN24_Pos (24UL)

#define	GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos)

#define	GPIO_IN_PIN24_Low (0UL)

#define	GPIO_IN_PIN24_High (1UL)

#define	GPIO_IN_PIN23_Pos (23UL)

#define	GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos)

#define	GPIO_IN_PIN23_Low (0UL)

#define	GPIO_IN_PIN23_High (1UL)

#define	GPIO_IN_PIN22_Pos (22UL)

#define	GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos)

#define	GPIO_IN_PIN22_Low (0UL)

#define	GPIO_IN_PIN22_High (1UL)

#define	GPIO_IN_PIN21_Pos (21UL)

#define	GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos)

#define	GPIO_IN_PIN21_Low (0UL)

#define	GPIO_IN_PIN21_High (1UL)

#define	GPIO_IN_PIN20_Pos (20UL)

#define	GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos)

#define	GPIO_IN_PIN20_Low (0UL)

#define	GPIO_IN_PIN20_High (1UL)

#define	GPIO_IN_PIN19_Pos (19UL)

#define	GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos)

#define	GPIO_IN_PIN19_Low (0UL)

#define	GPIO_IN_PIN19_High (1UL)

#define	GPIO_IN_PIN18_Pos (18UL)

#define	GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos)

#define	GPIO_IN_PIN18_Low (0UL)

#define	GPIO_IN_PIN18_High (1UL)

#define	GPIO_IN_PIN17_Pos (17UL)

#define	GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos)

#define	GPIO_IN_PIN17_Low (0UL)

#define	GPIO_IN_PIN17_High (1UL)

#define	GPIO_IN_PIN16_Pos (16UL)

#define	GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos)

#define	GPIO_IN_PIN16_Low (0UL)

#define	GPIO_IN_PIN16_High (1UL)

#define	GPIO_IN_PIN15_Pos (15UL)

#define	GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos)

#define	GPIO_IN_PIN15_Low (0UL)

#define	GPIO_IN_PIN15_High (1UL)

#define	GPIO_IN_PIN14_Pos (14UL)

#define	GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos)

#define	GPIO_IN_PIN14_Low (0UL)

#define	GPIO_IN_PIN14_High (1UL)

#define	GPIO_IN_PIN13_Pos (13UL)

#define	GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos)

#define	GPIO_IN_PIN13_Low (0UL)

#define	GPIO_IN_PIN13_High (1UL)

#define	GPIO_IN_PIN12_Pos (12UL)

#define	GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos)

#define	GPIO_IN_PIN12_Low (0UL)

#define	GPIO_IN_PIN12_High (1UL)

#define	GPIO_IN_PIN11_Pos (11UL)

#define	GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos)

#define	GPIO_IN_PIN11_Low (0UL)

#define	GPIO_IN_PIN11_High (1UL)

#define	GPIO_IN_PIN10_Pos (10UL)

#define	GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos)

#define	GPIO_IN_PIN10_Low (0UL)

#define	GPIO_IN_PIN10_High (1UL)

#define	GPIO_IN_PIN9_Pos (9UL)

#define	GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos)

#define	GPIO_IN_PIN9_Low (0UL)

#define	GPIO_IN_PIN9_High (1UL)

#define	GPIO_IN_PIN8_Pos (8UL)

#define	GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos)

#define	GPIO_IN_PIN8_Low (0UL)

#define	GPIO_IN_PIN8_High (1UL)

#define	GPIO_IN_PIN7_Pos (7UL)

#define	GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos)

#define	GPIO_IN_PIN7_Low (0UL)

#define	GPIO_IN_PIN7_High (1UL)

#define	GPIO_IN_PIN6_Pos (6UL)

#define	GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos)

#define	GPIO_IN_PIN6_Low (0UL)

#define	GPIO_IN_PIN6_High (1UL)

#define	GPIO_IN_PIN5_Pos (5UL)

#define	GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos)

#define	GPIO_IN_PIN5_Low (0UL)

#define	GPIO_IN_PIN5_High (1UL)

#define	GPIO_IN_PIN4_Pos (4UL)

#define	GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos)

#define	GPIO_IN_PIN4_Low (0UL)

#define	GPIO_IN_PIN4_High (1UL)

#define	GPIO_IN_PIN3_Pos (3UL)

#define	GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos)

#define	GPIO_IN_PIN3_Low (0UL)

#define	GPIO_IN_PIN3_High (1UL)

#define	GPIO_IN_PIN2_Pos (2UL)

#define	GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos)

#define	GPIO_IN_PIN2_Low (0UL)

#define	GPIO_IN_PIN2_High (1UL)

#define	GPIO_IN_PIN1_Pos (1UL)

#define	GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos)

#define	GPIO_IN_PIN1_Low (0UL)

#define	GPIO_IN_PIN1_High (1UL)

#define	GPIO_IN_PIN0_Pos (0UL)

#define	GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos)

#define	GPIO_IN_PIN0_Low (0UL)

#define	GPIO_IN_PIN0_High (1UL)

#define	GPIO_DIR_PIN31_Pos (31UL)

#define	GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos)

#define	GPIO_DIR_PIN31_Input (0UL)

#define	GPIO_DIR_PIN31_Output (1UL)

#define	GPIO_DIR_PIN30_Pos (30UL)

#define	GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos)

#define	GPIO_DIR_PIN30_Input (0UL)

#define	GPIO_DIR_PIN30_Output (1UL)

#define	GPIO_DIR_PIN29_Pos (29UL)

#define	GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos)

#define	GPIO_DIR_PIN29_Input (0UL)

#define	GPIO_DIR_PIN29_Output (1UL)

#define	GPIO_DIR_PIN28_Pos (28UL)

#define	GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos)

#define	GPIO_DIR_PIN28_Input (0UL)

#define	GPIO_DIR_PIN28_Output (1UL)

#define	GPIO_DIR_PIN27_Pos (27UL)

#define	GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos)

#define	GPIO_DIR_PIN27_Input (0UL)

#define	GPIO_DIR_PIN27_Output (1UL)

#define	GPIO_DIR_PIN26_Pos (26UL)

#define	GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos)

#define	GPIO_DIR_PIN26_Input (0UL)

#define	GPIO_DIR_PIN26_Output (1UL)

#define	GPIO_DIR_PIN25_Pos (25UL)

#define	GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos)

#define	GPIO_DIR_PIN25_Input (0UL)

#define	GPIO_DIR_PIN25_Output (1UL)

#define	GPIO_DIR_PIN24_Pos (24UL)

#define	GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos)

#define	GPIO_DIR_PIN24_Input (0UL)

#define	GPIO_DIR_PIN24_Output (1UL)

#define	GPIO_DIR_PIN23_Pos (23UL)

#define	GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos)

#define	GPIO_DIR_PIN23_Input (0UL)

#define	GPIO_DIR_PIN23_Output (1UL)

#define	GPIO_DIR_PIN22_Pos (22UL)

#define	GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos)

#define	GPIO_DIR_PIN22_Input (0UL)

#define	GPIO_DIR_PIN22_Output (1UL)

#define	GPIO_DIR_PIN21_Pos (21UL)

#define	GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos)

#define	GPIO_DIR_PIN21_Input (0UL)

#define	GPIO_DIR_PIN21_Output (1UL)

#define	GPIO_DIR_PIN20_Pos (20UL)

#define	GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos)

#define	GPIO_DIR_PIN20_Input (0UL)

#define	GPIO_DIR_PIN20_Output (1UL)

#define	GPIO_DIR_PIN19_Pos (19UL)

#define	GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos)

#define	GPIO_DIR_PIN19_Input (0UL)

#define	GPIO_DIR_PIN19_Output (1UL)

#define	GPIO_DIR_PIN18_Pos (18UL)

#define	GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos)

#define	GPIO_DIR_PIN18_Input (0UL)

#define	GPIO_DIR_PIN18_Output (1UL)

#define	GPIO_DIR_PIN17_Pos (17UL)

#define	GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos)

#define	GPIO_DIR_PIN17_Input (0UL)

#define	GPIO_DIR_PIN17_Output (1UL)

#define	GPIO_DIR_PIN16_Pos (16UL)

#define	GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos)

#define	GPIO_DIR_PIN16_Input (0UL)

#define	GPIO_DIR_PIN16_Output (1UL)

#define	GPIO_DIR_PIN15_Pos (15UL)

#define	GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos)

#define	GPIO_DIR_PIN15_Input (0UL)

#define	GPIO_DIR_PIN15_Output (1UL)

#define	GPIO_DIR_PIN14_Pos (14UL)

#define	GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos)

#define	GPIO_DIR_PIN14_Input (0UL)

#define	GPIO_DIR_PIN14_Output (1UL)

#define	GPIO_DIR_PIN13_Pos (13UL)

#define	GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos)

#define	GPIO_DIR_PIN13_Input (0UL)

#define	GPIO_DIR_PIN13_Output (1UL)

#define	GPIO_DIR_PIN12_Pos (12UL)

#define	GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos)

#define	GPIO_DIR_PIN12_Input (0UL)

#define	GPIO_DIR_PIN12_Output (1UL)

#define	GPIO_DIR_PIN11_Pos (11UL)

#define	GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos)

#define	GPIO_DIR_PIN11_Input (0UL)

#define	GPIO_DIR_PIN11_Output (1UL)

#define	GPIO_DIR_PIN10_Pos (10UL)

#define	GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos)

#define	GPIO_DIR_PIN10_Input (0UL)

#define	GPIO_DIR_PIN10_Output (1UL)

#define	GPIO_DIR_PIN9_Pos (9UL)

#define	GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos)

#define	GPIO_DIR_PIN9_Input (0UL)

#define	GPIO_DIR_PIN9_Output (1UL)

#define	GPIO_DIR_PIN8_Pos (8UL)

#define	GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos)

#define	GPIO_DIR_PIN8_Input (0UL)

#define	GPIO_DIR_PIN8_Output (1UL)

#define	GPIO_DIR_PIN7_Pos (7UL)

#define	GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos)

#define	GPIO_DIR_PIN7_Input (0UL)

#define	GPIO_DIR_PIN7_Output (1UL)

#define	GPIO_DIR_PIN6_Pos (6UL)

#define	GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos)

#define	GPIO_DIR_PIN6_Input (0UL)

#define	GPIO_DIR_PIN6_Output (1UL)

#define	GPIO_DIR_PIN5_Pos (5UL)

#define	GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos)

#define	GPIO_DIR_PIN5_Input (0UL)

#define	GPIO_DIR_PIN5_Output (1UL)

#define	GPIO_DIR_PIN4_Pos (4UL)

#define	GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos)

#define	GPIO_DIR_PIN4_Input (0UL)

#define	GPIO_DIR_PIN4_Output (1UL)

#define	GPIO_DIR_PIN3_Pos (3UL)

#define	GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos)

#define	GPIO_DIR_PIN3_Input (0UL)

#define	GPIO_DIR_PIN3_Output (1UL)

#define	GPIO_DIR_PIN2_Pos (2UL)

#define	GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos)

#define	GPIO_DIR_PIN2_Input (0UL)

#define	GPIO_DIR_PIN2_Output (1UL)

#define	GPIO_DIR_PIN1_Pos (1UL)

#define	GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos)

#define	GPIO_DIR_PIN1_Input (0UL)

#define	GPIO_DIR_PIN1_Output (1UL)

#define	GPIO_DIR_PIN0_Pos (0UL)

#define	GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos)

#define	GPIO_DIR_PIN0_Input (0UL)

#define	GPIO_DIR_PIN0_Output (1UL)

#define	GPIO_DIRSET_PIN31_Pos (31UL)

#define	GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos)

#define	GPIO_DIRSET_PIN31_Input (0UL)

#define	GPIO_DIRSET_PIN31_Output (1UL)

#define	GPIO_DIRSET_PIN31_Set (1UL)

#define	GPIO_DIRSET_PIN30_Pos (30UL)

#define	GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos)

#define	GPIO_DIRSET_PIN30_Input (0UL)

#define	GPIO_DIRSET_PIN30_Output (1UL)

#define	GPIO_DIRSET_PIN30_Set (1UL)

#define	GPIO_DIRSET_PIN29_Pos (29UL)

#define	GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos)

#define	GPIO_DIRSET_PIN29_Input (0UL)

#define	GPIO_DIRSET_PIN29_Output (1UL)

#define	GPIO_DIRSET_PIN29_Set (1UL)

#define	GPIO_DIRSET_PIN28_Pos (28UL)

#define	GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos)

#define	GPIO_DIRSET_PIN28_Input (0UL)

#define	GPIO_DIRSET_PIN28_Output (1UL)

#define	GPIO_DIRSET_PIN28_Set (1UL)

#define	GPIO_DIRSET_PIN27_Pos (27UL)

#define	GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos)

#define	GPIO_DIRSET_PIN27_Input (0UL)

#define	GPIO_DIRSET_PIN27_Output (1UL)

#define	GPIO_DIRSET_PIN27_Set (1UL)

#define	GPIO_DIRSET_PIN26_Pos (26UL)

#define	GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos)

#define	GPIO_DIRSET_PIN26_Input (0UL)

#define	GPIO_DIRSET_PIN26_Output (1UL)

#define	GPIO_DIRSET_PIN26_Set (1UL)

#define	GPIO_DIRSET_PIN25_Pos (25UL)

#define	GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos)

#define	GPIO_DIRSET_PIN25_Input (0UL)

#define	GPIO_DIRSET_PIN25_Output (1UL)

#define	GPIO_DIRSET_PIN25_Set (1UL)

#define	GPIO_DIRSET_PIN24_Pos (24UL)

#define	GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos)

#define	GPIO_DIRSET_PIN24_Input (0UL)

#define	GPIO_DIRSET_PIN24_Output (1UL)

#define	GPIO_DIRSET_PIN24_Set (1UL)

#define	GPIO_DIRSET_PIN23_Pos (23UL)

#define	GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos)

#define	GPIO_DIRSET_PIN23_Input (0UL)

#define	GPIO_DIRSET_PIN23_Output (1UL)

#define	GPIO_DIRSET_PIN23_Set (1UL)

#define	GPIO_DIRSET_PIN22_Pos (22UL)

#define	GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos)

#define	GPIO_DIRSET_PIN22_Input (0UL)

#define	GPIO_DIRSET_PIN22_Output (1UL)

#define	GPIO_DIRSET_PIN22_Set (1UL)

#define	GPIO_DIRSET_PIN21_Pos (21UL)

#define	GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos)

#define	GPIO_DIRSET_PIN21_Input (0UL)

#define	GPIO_DIRSET_PIN21_Output (1UL)

#define	GPIO_DIRSET_PIN21_Set (1UL)

#define	GPIO_DIRSET_PIN20_Pos (20UL)

#define	GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos)

#define	GPIO_DIRSET_PIN20_Input (0UL)

#define	GPIO_DIRSET_PIN20_Output (1UL)

#define	GPIO_DIRSET_PIN20_Set (1UL)

#define	GPIO_DIRSET_PIN19_Pos (19UL)

#define	GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos)

#define	GPIO_DIRSET_PIN19_Input (0UL)

#define	GPIO_DIRSET_PIN19_Output (1UL)

#define	GPIO_DIRSET_PIN19_Set (1UL)

#define	GPIO_DIRSET_PIN18_Pos (18UL)

#define	GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos)

#define	GPIO_DIRSET_PIN18_Input (0UL)

#define	GPIO_DIRSET_PIN18_Output (1UL)

#define	GPIO_DIRSET_PIN18_Set (1UL)

#define	GPIO_DIRSET_PIN17_Pos (17UL)

#define	GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos)

#define	GPIO_DIRSET_PIN17_Input (0UL)

#define	GPIO_DIRSET_PIN17_Output (1UL)

#define	GPIO_DIRSET_PIN17_Set (1UL)

#define	GPIO_DIRSET_PIN16_Pos (16UL)

#define	GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos)

#define	GPIO_DIRSET_PIN16_Input (0UL)

#define	GPIO_DIRSET_PIN16_Output (1UL)

#define	GPIO_DIRSET_PIN16_Set (1UL)

#define	GPIO_DIRSET_PIN15_Pos (15UL)

#define	GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos)

#define	GPIO_DIRSET_PIN15_Input (0UL)

#define	GPIO_DIRSET_PIN15_Output (1UL)

#define	GPIO_DIRSET_PIN15_Set (1UL)

#define	GPIO_DIRSET_PIN14_Pos (14UL)

#define	GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos)

#define	GPIO_DIRSET_PIN14_Input (0UL)

#define	GPIO_DIRSET_PIN14_Output (1UL)

#define	GPIO_DIRSET_PIN14_Set (1UL)

#define	GPIO_DIRSET_PIN13_Pos (13UL)

#define	GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos)

#define	GPIO_DIRSET_PIN13_Input (0UL)

#define	GPIO_DIRSET_PIN13_Output (1UL)

#define	GPIO_DIRSET_PIN13_Set (1UL)

#define	GPIO_DIRSET_PIN12_Pos (12UL)

#define	GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos)

#define	GPIO_DIRSET_PIN12_Input (0UL)

#define	GPIO_DIRSET_PIN12_Output (1UL)

#define	GPIO_DIRSET_PIN12_Set (1UL)

#define	GPIO_DIRSET_PIN11_Pos (11UL)

#define	GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos)

#define	GPIO_DIRSET_PIN11_Input (0UL)

#define	GPIO_DIRSET_PIN11_Output (1UL)

#define	GPIO_DIRSET_PIN11_Set (1UL)

#define	GPIO_DIRSET_PIN10_Pos (10UL)

#define	GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos)

#define	GPIO_DIRSET_PIN10_Input (0UL)

#define	GPIO_DIRSET_PIN10_Output (1UL)

#define	GPIO_DIRSET_PIN10_Set (1UL)

#define	GPIO_DIRSET_PIN9_Pos (9UL)

#define	GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos)

#define	GPIO_DIRSET_PIN9_Input (0UL)

#define	GPIO_DIRSET_PIN9_Output (1UL)

#define	GPIO_DIRSET_PIN9_Set (1UL)

#define	GPIO_DIRSET_PIN8_Pos (8UL)

#define	GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos)

#define	GPIO_DIRSET_PIN8_Input (0UL)

#define	GPIO_DIRSET_PIN8_Output (1UL)

#define	GPIO_DIRSET_PIN8_Set (1UL)

#define	GPIO_DIRSET_PIN7_Pos (7UL)

#define	GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos)

#define	GPIO_DIRSET_PIN7_Input (0UL)

#define	GPIO_DIRSET_PIN7_Output (1UL)

#define	GPIO_DIRSET_PIN7_Set (1UL)

#define	GPIO_DIRSET_PIN6_Pos (6UL)

#define	GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos)

#define	GPIO_DIRSET_PIN6_Input (0UL)

#define	GPIO_DIRSET_PIN6_Output (1UL)

#define	GPIO_DIRSET_PIN6_Set (1UL)

#define	GPIO_DIRSET_PIN5_Pos (5UL)

#define	GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos)

#define	GPIO_DIRSET_PIN5_Input (0UL)

#define	GPIO_DIRSET_PIN5_Output (1UL)

#define	GPIO_DIRSET_PIN5_Set (1UL)

#define	GPIO_DIRSET_PIN4_Pos (4UL)

#define	GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos)

#define	GPIO_DIRSET_PIN4_Input (0UL)

#define	GPIO_DIRSET_PIN4_Output (1UL)

#define	GPIO_DIRSET_PIN4_Set (1UL)

#define	GPIO_DIRSET_PIN3_Pos (3UL)

#define	GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos)

#define	GPIO_DIRSET_PIN3_Input (0UL)

#define	GPIO_DIRSET_PIN3_Output (1UL)

#define	GPIO_DIRSET_PIN3_Set (1UL)

#define	GPIO_DIRSET_PIN2_Pos (2UL)

#define	GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos)

#define	GPIO_DIRSET_PIN2_Input (0UL)

#define	GPIO_DIRSET_PIN2_Output (1UL)

#define	GPIO_DIRSET_PIN2_Set (1UL)

#define	GPIO_DIRSET_PIN1_Pos (1UL)

#define	GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos)

#define	GPIO_DIRSET_PIN1_Input (0UL)

#define	GPIO_DIRSET_PIN1_Output (1UL)

#define	GPIO_DIRSET_PIN1_Set (1UL)

#define	GPIO_DIRSET_PIN0_Pos (0UL)

#define	GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos)

#define	GPIO_DIRSET_PIN0_Input (0UL)

#define	GPIO_DIRSET_PIN0_Output (1UL)

#define	GPIO_DIRSET_PIN0_Set (1UL)

#define	GPIO_DIRCLR_PIN31_Pos (31UL)

#define	GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos)

#define	GPIO_DIRCLR_PIN31_Input (0UL)

#define	GPIO_DIRCLR_PIN31_Output (1UL)

#define	GPIO_DIRCLR_PIN31_Clear (1UL)

#define	GPIO_DIRCLR_PIN30_Pos (30UL)

#define	GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos)

#define	GPIO_DIRCLR_PIN30_Input (0UL)

#define	GPIO_DIRCLR_PIN30_Output (1UL)

#define	GPIO_DIRCLR_PIN30_Clear (1UL)

#define	GPIO_DIRCLR_PIN29_Pos (29UL)

#define	GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos)

#define	GPIO_DIRCLR_PIN29_Input (0UL)

#define	GPIO_DIRCLR_PIN29_Output (1UL)

#define	GPIO_DIRCLR_PIN29_Clear (1UL)

#define	GPIO_DIRCLR_PIN28_Pos (28UL)

#define	GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos)

#define	GPIO_DIRCLR_PIN28_Input (0UL)

#define	GPIO_DIRCLR_PIN28_Output (1UL)

#define	GPIO_DIRCLR_PIN28_Clear (1UL)

#define	GPIO_DIRCLR_PIN27_Pos (27UL)

#define	GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos)

#define	GPIO_DIRCLR_PIN27_Input (0UL)

#define	GPIO_DIRCLR_PIN27_Output (1UL)

#define	GPIO_DIRCLR_PIN27_Clear (1UL)

#define	GPIO_DIRCLR_PIN26_Pos (26UL)

#define	GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos)

#define	GPIO_DIRCLR_PIN26_Input (0UL)

#define	GPIO_DIRCLR_PIN26_Output (1UL)

#define	GPIO_DIRCLR_PIN26_Clear (1UL)

#define	GPIO_DIRCLR_PIN25_Pos (25UL)

#define	GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos)

#define	GPIO_DIRCLR_PIN25_Input (0UL)

#define	GPIO_DIRCLR_PIN25_Output (1UL)

#define	GPIO_DIRCLR_PIN25_Clear (1UL)

#define	GPIO_DIRCLR_PIN24_Pos (24UL)

#define	GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos)

#define	GPIO_DIRCLR_PIN24_Input (0UL)

#define	GPIO_DIRCLR_PIN24_Output (1UL)

#define	GPIO_DIRCLR_PIN24_Clear (1UL)

#define	GPIO_DIRCLR_PIN23_Pos (23UL)

#define	GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos)

#define	GPIO_DIRCLR_PIN23_Input (0UL)

#define	GPIO_DIRCLR_PIN23_Output (1UL)

#define	GPIO_DIRCLR_PIN23_Clear (1UL)

#define	GPIO_DIRCLR_PIN22_Pos (22UL)

#define	GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos)

#define	GPIO_DIRCLR_PIN22_Input (0UL)

#define	GPIO_DIRCLR_PIN22_Output (1UL)

#define	GPIO_DIRCLR_PIN22_Clear (1UL)

#define	GPIO_DIRCLR_PIN21_Pos (21UL)

#define	GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos)

#define	GPIO_DIRCLR_PIN21_Input (0UL)

#define	GPIO_DIRCLR_PIN21_Output (1UL)

#define	GPIO_DIRCLR_PIN21_Clear (1UL)

#define	GPIO_DIRCLR_PIN20_Pos (20UL)

#define	GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos)

#define	GPIO_DIRCLR_PIN20_Input (0UL)

#define	GPIO_DIRCLR_PIN20_Output (1UL)

#define	GPIO_DIRCLR_PIN20_Clear (1UL)

#define	GPIO_DIRCLR_PIN19_Pos (19UL)

#define	GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos)

#define	GPIO_DIRCLR_PIN19_Input (0UL)

#define	GPIO_DIRCLR_PIN19_Output (1UL)

#define	GPIO_DIRCLR_PIN19_Clear (1UL)

#define	GPIO_DIRCLR_PIN18_Pos (18UL)

#define	GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos)

#define	GPIO_DIRCLR_PIN18_Input (0UL)

#define	GPIO_DIRCLR_PIN18_Output (1UL)

#define	GPIO_DIRCLR_PIN18_Clear (1UL)

#define	GPIO_DIRCLR_PIN17_Pos (17UL)

#define	GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos)

#define	GPIO_DIRCLR_PIN17_Input (0UL)

#define	GPIO_DIRCLR_PIN17_Output (1UL)

#define	GPIO_DIRCLR_PIN17_Clear (1UL)

#define	GPIO_DIRCLR_PIN16_Pos (16UL)

#define	GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos)

#define	GPIO_DIRCLR_PIN16_Input (0UL)

#define	GPIO_DIRCLR_PIN16_Output (1UL)

#define	GPIO_DIRCLR_PIN16_Clear (1UL)

#define	GPIO_DIRCLR_PIN15_Pos (15UL)

#define	GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos)

#define	GPIO_DIRCLR_PIN15_Input (0UL)

#define	GPIO_DIRCLR_PIN15_Output (1UL)

#define	GPIO_DIRCLR_PIN15_Clear (1UL)

#define	GPIO_DIRCLR_PIN14_Pos (14UL)

#define	GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos)

#define	GPIO_DIRCLR_PIN14_Input (0UL)

#define	GPIO_DIRCLR_PIN14_Output (1UL)

#define	GPIO_DIRCLR_PIN14_Clear (1UL)

#define	GPIO_DIRCLR_PIN13_Pos (13UL)

#define	GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos)

#define	GPIO_DIRCLR_PIN13_Input (0UL)

#define	GPIO_DIRCLR_PIN13_Output (1UL)

#define	GPIO_DIRCLR_PIN13_Clear (1UL)

#define	GPIO_DIRCLR_PIN12_Pos (12UL)

#define	GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos)

#define	GPIO_DIRCLR_PIN12_Input (0UL)

#define	GPIO_DIRCLR_PIN12_Output (1UL)

#define	GPIO_DIRCLR_PIN12_Clear (1UL)

#define	GPIO_DIRCLR_PIN11_Pos (11UL)

#define	GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos)

#define	GPIO_DIRCLR_PIN11_Input (0UL)

#define	GPIO_DIRCLR_PIN11_Output (1UL)

#define	GPIO_DIRCLR_PIN11_Clear (1UL)

#define	GPIO_DIRCLR_PIN10_Pos (10UL)

#define	GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos)

#define	GPIO_DIRCLR_PIN10_Input (0UL)

#define	GPIO_DIRCLR_PIN10_Output (1UL)

#define	GPIO_DIRCLR_PIN10_Clear (1UL)

#define	GPIO_DIRCLR_PIN9_Pos (9UL)

#define	GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos)

#define	GPIO_DIRCLR_PIN9_Input (0UL)

#define	GPIO_DIRCLR_PIN9_Output (1UL)

#define	GPIO_DIRCLR_PIN9_Clear (1UL)

#define	GPIO_DIRCLR_PIN8_Pos (8UL)

#define	GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos)

#define	GPIO_DIRCLR_PIN8_Input (0UL)

#define	GPIO_DIRCLR_PIN8_Output (1UL)

#define	GPIO_DIRCLR_PIN8_Clear (1UL)

#define	GPIO_DIRCLR_PIN7_Pos (7UL)

#define	GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos)

#define	GPIO_DIRCLR_PIN7_Input (0UL)

#define	GPIO_DIRCLR_PIN7_Output (1UL)

#define	GPIO_DIRCLR_PIN7_Clear (1UL)

#define	GPIO_DIRCLR_PIN6_Pos (6UL)

#define	GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos)

#define	GPIO_DIRCLR_PIN6_Input (0UL)

#define	GPIO_DIRCLR_PIN6_Output (1UL)

#define	GPIO_DIRCLR_PIN6_Clear (1UL)

#define	GPIO_DIRCLR_PIN5_Pos (5UL)

#define	GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos)

#define	GPIO_DIRCLR_PIN5_Input (0UL)

#define	GPIO_DIRCLR_PIN5_Output (1UL)

#define	GPIO_DIRCLR_PIN5_Clear (1UL)

#define	GPIO_DIRCLR_PIN4_Pos (4UL)

#define	GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos)

#define	GPIO_DIRCLR_PIN4_Input (0UL)

#define	GPIO_DIRCLR_PIN4_Output (1UL)

#define	GPIO_DIRCLR_PIN4_Clear (1UL)

#define	GPIO_DIRCLR_PIN3_Pos (3UL)

#define	GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos)

#define	GPIO_DIRCLR_PIN3_Input (0UL)

#define	GPIO_DIRCLR_PIN3_Output (1UL)

#define	GPIO_DIRCLR_PIN3_Clear (1UL)

#define	GPIO_DIRCLR_PIN2_Pos (2UL)

#define	GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos)

#define	GPIO_DIRCLR_PIN2_Input (0UL)

#define	GPIO_DIRCLR_PIN2_Output (1UL)

#define	GPIO_DIRCLR_PIN2_Clear (1UL)

#define	GPIO_DIRCLR_PIN1_Pos (1UL)

#define	GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos)

#define	GPIO_DIRCLR_PIN1_Input (0UL)

#define	GPIO_DIRCLR_PIN1_Output (1UL)

#define	GPIO_DIRCLR_PIN1_Clear (1UL)

#define	GPIO_DIRCLR_PIN0_Pos (0UL)

#define	GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos)

#define	GPIO_DIRCLR_PIN0_Input (0UL)

#define	GPIO_DIRCLR_PIN0_Output (1UL)

#define	GPIO_DIRCLR_PIN0_Clear (1UL)

#define	GPIO_PIN_CNF_SENSE_Pos (16UL)

#define	GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos)

#define	GPIO_PIN_CNF_SENSE_Disabled (0x00UL)

#define	GPIO_PIN_CNF_SENSE_High (0x02UL)

#define	GPIO_PIN_CNF_SENSE_Low (0x03UL)

#define	GPIO_PIN_CNF_DRIVE_Pos (8UL)

#define	GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos)

#define	GPIO_PIN_CNF_DRIVE_S0S1 (0x00UL)

#define	GPIO_PIN_CNF_DRIVE_H0S1 (0x01UL)

#define	GPIO_PIN_CNF_DRIVE_S0H1 (0x02UL)

#define	GPIO_PIN_CNF_DRIVE_H0H1 (0x03UL)

#define	GPIO_PIN_CNF_DRIVE_D0S1 (0x04UL)

#define	GPIO_PIN_CNF_DRIVE_D0H1 (0x05UL)

#define	GPIO_PIN_CNF_DRIVE_S0D1 (0x06UL)

#define	GPIO_PIN_CNF_DRIVE_H0D1 (0x07UL)

#define	GPIO_PIN_CNF_PULL_Pos (2UL)

#define	GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos)

#define	GPIO_PIN_CNF_PULL_Disabled (0x00UL)

#define	GPIO_PIN_CNF_PULL_Pulldown (0x01UL)

#define	GPIO_PIN_CNF_PULL_Pullup (0x03UL)

#define	GPIO_PIN_CNF_INPUT_Pos (1UL)

#define	GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos)

#define	GPIO_PIN_CNF_INPUT_Connect (0UL)

#define	GPIO_PIN_CNF_INPUT_Disconnect (1UL)

#define	GPIO_PIN_CNF_DIR_Pos (0UL)

#define	GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos)

#define	GPIO_PIN_CNF_DIR_Input (0UL)

#define	GPIO_PIN_CNF_DIR_Output (1UL)

#define	GPIOTE_INTENSET_PORT_Pos (31UL)

#define	GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos)

#define	GPIOTE_INTENSET_PORT_Disabled (0UL)

#define	GPIOTE_INTENSET_PORT_Enabled (1UL)

#define	GPIOTE_INTENSET_PORT_Set (1UL)

#define	GPIOTE_INTENSET_IN3_Pos (3UL)

#define	GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos)

#define	GPIOTE_INTENSET_IN3_Disabled (0UL)

#define	GPIOTE_INTENSET_IN3_Enabled (1UL)

#define	GPIOTE_INTENSET_IN3_Set (1UL)

#define	GPIOTE_INTENSET_IN2_Pos (2UL)

#define	GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos)

#define	GPIOTE_INTENSET_IN2_Disabled (0UL)

#define	GPIOTE_INTENSET_IN2_Enabled (1UL)

#define	GPIOTE_INTENSET_IN2_Set (1UL)

#define	GPIOTE_INTENSET_IN1_Pos (1UL)

#define	GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos)

#define	GPIOTE_INTENSET_IN1_Disabled (0UL)

#define	GPIOTE_INTENSET_IN1_Enabled (1UL)

#define	GPIOTE_INTENSET_IN1_Set (1UL)

#define	GPIOTE_INTENSET_IN0_Pos (0UL)

#define	GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos)

#define	GPIOTE_INTENSET_IN0_Disabled (0UL)

#define	GPIOTE_INTENSET_IN0_Enabled (1UL)

#define	GPIOTE_INTENSET_IN0_Set (1UL)

#define	GPIOTE_INTENCLR_PORT_Pos (31UL)

#define	GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos)

#define	GPIOTE_INTENCLR_PORT_Disabled (0UL)

#define	GPIOTE_INTENCLR_PORT_Enabled (1UL)

#define	GPIOTE_INTENCLR_PORT_Clear (1UL)

#define	GPIOTE_INTENCLR_IN3_Pos (3UL)

#define	GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos)

#define	GPIOTE_INTENCLR_IN3_Disabled (0UL)

#define	GPIOTE_INTENCLR_IN3_Enabled (1UL)

#define	GPIOTE_INTENCLR_IN3_Clear (1UL)

#define	GPIOTE_INTENCLR_IN2_Pos (2UL)

#define	GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos)

#define	GPIOTE_INTENCLR_IN2_Disabled (0UL)

#define	GPIOTE_INTENCLR_IN2_Enabled (1UL)

#define	GPIOTE_INTENCLR_IN2_Clear (1UL)

#define	GPIOTE_INTENCLR_IN1_Pos (1UL)

#define	GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos)

#define	GPIOTE_INTENCLR_IN1_Disabled (0UL)

#define	GPIOTE_INTENCLR_IN1_Enabled (1UL)

#define	GPIOTE_INTENCLR_IN1_Clear (1UL)

#define	GPIOTE_INTENCLR_IN0_Pos (0UL)

#define	GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos)

#define	GPIOTE_INTENCLR_IN0_Disabled (0UL)

#define	GPIOTE_INTENCLR_IN0_Enabled (1UL)

#define	GPIOTE_INTENCLR_IN0_Clear (1UL)

#define	GPIOTE_CONFIG_OUTINIT_Pos (20UL)

#define	GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos)

#define	GPIOTE_CONFIG_OUTINIT_Low (0UL)

#define	GPIOTE_CONFIG_OUTINIT_High (1UL)

#define	GPIOTE_CONFIG_POLARITY_Pos (16UL)

#define	GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos)

#define	GPIOTE_CONFIG_POLARITY_None (0x00UL)

#define	GPIOTE_CONFIG_POLARITY_LoToHi (0x01UL)

#define	GPIOTE_CONFIG_POLARITY_HiToLo (0x02UL)

#define	GPIOTE_CONFIG_POLARITY_Toggle (0x03UL)

#define	GPIOTE_CONFIG_PSEL_Pos (8UL)

#define	GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos)

#define	GPIOTE_CONFIG_MODE_Pos (0UL)

#define	GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos)

#define	GPIOTE_CONFIG_MODE_Disabled (0x00UL)

#define	GPIOTE_CONFIG_MODE_Event (0x01UL)

#define	GPIOTE_CONFIG_MODE_Task (0x03UL)

#define	GPIOTE_POWER_POWER_Pos (0UL)

#define	GPIOTE_POWER_POWER_Msk (0x1UL << GPIOTE_POWER_POWER_Pos)

#define	GPIOTE_POWER_POWER_Disabled (0UL)

#define	GPIOTE_POWER_POWER_Enabled (1UL)

#define	LPCOMP_SHORTS_CROSS_STOP_Pos (4UL)

#define	LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos)

#define	LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL)

#define	LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL)

#define	LPCOMP_SHORTS_UP_STOP_Pos (3UL)

#define	LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos)

#define	LPCOMP_SHORTS_UP_STOP_Disabled (0UL)

#define	LPCOMP_SHORTS_UP_STOP_Enabled (1UL)

#define	LPCOMP_SHORTS_DOWN_STOP_Pos (2UL)

#define	LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos)

#define	LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL)

#define	LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL)

#define	LPCOMP_SHORTS_READY_STOP_Pos (1UL)

#define	LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos)

#define	LPCOMP_SHORTS_READY_STOP_Disabled (0UL)

#define	LPCOMP_SHORTS_READY_STOP_Enabled (1UL)

#define	LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL)

#define	LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos)

#define	LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL)

#define	LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL)

#define	LPCOMP_INTENSET_CROSS_Pos (3UL)

#define	LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos)

#define	LPCOMP_INTENSET_CROSS_Disabled (0UL)

#define	LPCOMP_INTENSET_CROSS_Enabled (1UL)

#define	LPCOMP_INTENSET_CROSS_Set (1UL)

#define	LPCOMP_INTENSET_UP_Pos (2UL)

#define	LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos)

#define	LPCOMP_INTENSET_UP_Disabled (0UL)

#define	LPCOMP_INTENSET_UP_Enabled (1UL)

#define	LPCOMP_INTENSET_UP_Set (1UL)

#define	LPCOMP_INTENSET_DOWN_Pos (1UL)

#define	LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos)

#define	LPCOMP_INTENSET_DOWN_Disabled (0UL)

#define	LPCOMP_INTENSET_DOWN_Enabled (1UL)

#define	LPCOMP_INTENSET_DOWN_Set (1UL)

#define	LPCOMP_INTENSET_READY_Pos (0UL)

#define	LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos)

#define	LPCOMP_INTENSET_READY_Disabled (0UL)

#define	LPCOMP_INTENSET_READY_Enabled (1UL)

#define	LPCOMP_INTENSET_READY_Set (1UL)

#define	LPCOMP_INTENCLR_CROSS_Pos (3UL)

#define	LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos)

#define	LPCOMP_INTENCLR_CROSS_Disabled (0UL)

#define	LPCOMP_INTENCLR_CROSS_Enabled (1UL)

#define	LPCOMP_INTENCLR_CROSS_Clear (1UL)

#define	LPCOMP_INTENCLR_UP_Pos (2UL)

#define	LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos)

#define	LPCOMP_INTENCLR_UP_Disabled (0UL)

#define	LPCOMP_INTENCLR_UP_Enabled (1UL)

#define	LPCOMP_INTENCLR_UP_Clear (1UL)

#define	LPCOMP_INTENCLR_DOWN_Pos (1UL)

#define	LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos)

#define	LPCOMP_INTENCLR_DOWN_Disabled (0UL)

#define	LPCOMP_INTENCLR_DOWN_Enabled (1UL)

#define	LPCOMP_INTENCLR_DOWN_Clear (1UL)

#define	LPCOMP_INTENCLR_READY_Pos (0UL)

#define	LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos)

#define	LPCOMP_INTENCLR_READY_Disabled (0UL)

#define	LPCOMP_INTENCLR_READY_Enabled (1UL)

#define	LPCOMP_INTENCLR_READY_Clear (1UL)

#define	LPCOMP_RESULT_RESULT_Pos (0UL)

#define	LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos)

#define	LPCOMP_RESULT_RESULT_Bellow (0UL)

#define	LPCOMP_RESULT_RESULT_Above (1UL)

#define	LPCOMP_ENABLE_ENABLE_Pos (0UL)

#define	LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos)

#define	LPCOMP_ENABLE_ENABLE_Disabled (0x00UL)

#define	LPCOMP_ENABLE_ENABLE_Enabled (0x01UL)

#define	LPCOMP_PSEL_PSEL_Pos (0UL)

#define	LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos)

#define	LPCOMP_PSEL_PSEL_AnalogInput0 (0UL)

#define	LPCOMP_PSEL_PSEL_AnalogInput1 (1UL)

#define	LPCOMP_PSEL_PSEL_AnalogInput2 (2UL)

#define	LPCOMP_PSEL_PSEL_AnalogInput3 (3UL)

#define	LPCOMP_PSEL_PSEL_AnalogInput4 (4UL)

#define	LPCOMP_PSEL_PSEL_AnalogInput5 (5UL)

#define	LPCOMP_PSEL_PSEL_AnalogInput6 (6UL)

#define	LPCOMP_PSEL_PSEL_AnalogInput7 (7UL)

#define	LPCOMP_REFSEL_REFSEL_Pos (0UL)

#define	LPCOMP_REFSEL_REFSEL_Msk (0x7UL << LPCOMP_REFSEL_REFSEL_Pos)

#define	LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling (0UL)

#define	LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling (1UL)

#define	LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling (2UL)

#define	LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling (3UL)

#define	LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling (4UL)

#define	LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling (5UL)

#define	LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling (6UL)

#define	LPCOMP_REFSEL_REFSEL_ARef (7UL)

#define	LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL)

#define	LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos)

#define	LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL)

#define	LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL)

#define	LPCOMP_ANADETECT_ANADETECT_Pos (0UL)

#define	LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos)

#define	LPCOMP_ANADETECT_ANADETECT_Cross (0UL)

#define	LPCOMP_ANADETECT_ANADETECT_Up (1UL)

#define	LPCOMP_ANADETECT_ANADETECT_Down (2UL)

#define	LPCOMP_POWER_POWER_Pos (0UL)

#define	LPCOMP_POWER_POWER_Msk (0x1UL << LPCOMP_POWER_POWER_Pos)

#define	LPCOMP_POWER_POWER_Disabled (0UL)

#define	LPCOMP_POWER_POWER_Enabled (1UL)

#define	MPU_PERR0_PPI_Pos (31UL)

#define	MPU_PERR0_PPI_Msk (0x1UL << MPU_PERR0_PPI_Pos)

#define	MPU_PERR0_PPI_InRegion1 (0UL)

#define	MPU_PERR0_PPI_InRegion0 (1UL)

#define	MPU_PERR0_NVMC_Pos (30UL)

#define	MPU_PERR0_NVMC_Msk (0x1UL << MPU_PERR0_NVMC_Pos)

#define	MPU_PERR0_NVMC_InRegion1 (0UL)

#define	MPU_PERR0_NVMC_InRegion0 (1UL)

#define	MPU_PERR0_LPCOMP_Pos (19UL)

#define	MPU_PERR0_LPCOMP_Msk (0x1UL << MPU_PERR0_LPCOMP_Pos)

#define	MPU_PERR0_LPCOMP_InRegion1 (0UL)

#define	MPU_PERR0_LPCOMP_InRegion0 (1UL)

#define	MPU_PERR0_QDEC_Pos (18UL)

#define	MPU_PERR0_QDEC_Msk (0x1UL << MPU_PERR0_QDEC_Pos)

#define	MPU_PERR0_QDEC_InRegion1 (0UL)

#define	MPU_PERR0_QDEC_InRegion0 (1UL)

#define	MPU_PERR0_RTC1_Pos (17UL)

#define	MPU_PERR0_RTC1_Msk (0x1UL << MPU_PERR0_RTC1_Pos)

#define	MPU_PERR0_RTC1_InRegion1 (0UL)

#define	MPU_PERR0_RTC1_InRegion0 (1UL)

#define	MPU_PERR0_WDT_Pos (16UL)

#define	MPU_PERR0_WDT_Msk (0x1UL << MPU_PERR0_WDT_Pos)

#define	MPU_PERR0_WDT_InRegion1 (0UL)

#define	MPU_PERR0_WDT_InRegion0 (1UL)

#define	MPU_PERR0_CCM_AAR_Pos (15UL)

#define	MPU_PERR0_CCM_AAR_Msk (0x1UL << MPU_PERR0_CCM_AAR_Pos)

#define	MPU_PERR0_CCM_AAR_InRegion1 (0UL)

#define	MPU_PERR0_CCM_AAR_InRegion0 (1UL)

#define	MPU_PERR0_ECB_Pos (14UL)

#define	MPU_PERR0_ECB_Msk (0x1UL << MPU_PERR0_ECB_Pos)

#define	MPU_PERR0_ECB_InRegion1 (0UL)

#define	MPU_PERR0_ECB_InRegion0 (1UL)

#define	MPU_PERR0_RNG_Pos (13UL)

#define	MPU_PERR0_RNG_Msk (0x1UL << MPU_PERR0_RNG_Pos)

#define	MPU_PERR0_RNG_InRegion1 (0UL)

#define	MPU_PERR0_RNG_InRegion0 (1UL)

#define	MPU_PERR0_TEMP_Pos (12UL)

#define	MPU_PERR0_TEMP_Msk (0x1UL << MPU_PERR0_TEMP_Pos)

#define	MPU_PERR0_TEMP_InRegion1 (0UL)

#define	MPU_PERR0_TEMP_InRegion0 (1UL)

#define	MPU_PERR0_RTC0_Pos (11UL)

#define	MPU_PERR0_RTC0_Msk (0x1UL << MPU_PERR0_RTC0_Pos)

#define	MPU_PERR0_RTC0_InRegion1 (0UL)

#define	MPU_PERR0_RTC0_InRegion0 (1UL)

#define	MPU_PERR0_TIMER2_Pos (10UL)

#define	MPU_PERR0_TIMER2_Msk (0x1UL << MPU_PERR0_TIMER2_Pos)

#define	MPU_PERR0_TIMER2_InRegion1 (0UL)

#define	MPU_PERR0_TIMER2_InRegion0 (1UL)

#define	MPU_PERR0_TIMER1_Pos (9UL)

#define	MPU_PERR0_TIMER1_Msk (0x1UL << MPU_PERR0_TIMER1_Pos)

#define	MPU_PERR0_TIMER1_InRegion1 (0UL)

#define	MPU_PERR0_TIMER1_InRegion0 (1UL)

#define	MPU_PERR0_TIMER0_Pos (8UL)

#define	MPU_PERR0_TIMER0_Msk (0x1UL << MPU_PERR0_TIMER0_Pos)

#define	MPU_PERR0_TIMER0_InRegion1 (0UL)

#define	MPU_PERR0_TIMER0_InRegion0 (1UL)

#define	MPU_PERR0_ADC_Pos (7UL)

#define	MPU_PERR0_ADC_Msk (0x1UL << MPU_PERR0_ADC_Pos)

#define	MPU_PERR0_ADC_InRegion1 (0UL)

#define	MPU_PERR0_ADC_InRegion0 (1UL)

#define	MPU_PERR0_GPIOTE_Pos (6UL)

#define	MPU_PERR0_GPIOTE_Msk (0x1UL << MPU_PERR0_GPIOTE_Pos)

#define	MPU_PERR0_GPIOTE_InRegion1 (0UL)

#define	MPU_PERR0_GPIOTE_InRegion0 (1UL)

#define	MPU_PERR0_SPI1_TWI1_Pos (4UL)

#define	MPU_PERR0_SPI1_TWI1_Msk (0x1UL << MPU_PERR0_SPI1_TWI1_Pos)

#define	MPU_PERR0_SPI1_TWI1_InRegion1 (0UL)

#define	MPU_PERR0_SPI1_TWI1_InRegion0 (1UL)

#define	MPU_PERR0_SPI0_TWI0_Pos (3UL)

#define	MPU_PERR0_SPI0_TWI0_Msk (0x1UL << MPU_PERR0_SPI0_TWI0_Pos)

#define	MPU_PERR0_SPI0_TWI0_InRegion1 (0UL)

#define	MPU_PERR0_SPI0_TWI0_InRegion0 (1UL)

#define	MPU_PERR0_UART0_Pos (2UL)

#define	MPU_PERR0_UART0_Msk (0x1UL << MPU_PERR0_UART0_Pos)

#define	MPU_PERR0_UART0_InRegion1 (0UL)

#define	MPU_PERR0_UART0_InRegion0 (1UL)

#define	MPU_PERR0_RADIO_Pos (1UL)

#define	MPU_PERR0_RADIO_Msk (0x1UL << MPU_PERR0_RADIO_Pos)

#define	MPU_PERR0_RADIO_InRegion1 (0UL)

#define	MPU_PERR0_RADIO_InRegion0 (1UL)

#define	MPU_PERR0_POWER_CLOCK_Pos (0UL)

#define	MPU_PERR0_POWER_CLOCK_Msk (0x1UL << MPU_PERR0_POWER_CLOCK_Pos)

#define	MPU_PERR0_POWER_CLOCK_InRegion1 (0UL)

#define	MPU_PERR0_POWER_CLOCK_InRegion0 (1UL)

#define	MPU_PROTENSET0_PROTREG31_Pos (31UL)

#define	MPU_PROTENSET0_PROTREG31_Msk (0x1UL << MPU_PROTENSET0_PROTREG31_Pos)

#define	MPU_PROTENSET0_PROTREG31_Disabled (0UL)

#define	MPU_PROTENSET0_PROTREG31_Enabled (1UL)

#define	MPU_PROTENSET0_PROTREG31_Set (1UL)

#define	MPU_PROTENSET0_PROTREG30_Pos (30UL)

#define	MPU_PROTENSET0_PROTREG30_Msk (0x1UL << MPU_PROTENSET0_PROTREG30_Pos)

#define	MPU_PROTENSET0_PROTREG30_Disabled (0UL)

#define	MPU_PROTENSET0_PROTREG30_Enabled (1UL)

#define	MPU_PROTENSET0_PROTREG30_Set (1UL)

#define	MPU_PROTENSET0_PROTREG29_Pos (29UL)

#define	MPU_PROTENSET0_PROTREG29_Msk (0x1UL << MPU_PROTENSET0_PROTREG29_Pos)

#define	MPU_PROTENSET0_PROTREG29_Disabled (0UL)

#define	MPU_PROTENSET0_PROTREG29_Enabled (1UL)

#define	MPU_PROTENSET0_PROTREG29_Set (1UL)

#define	MPU_PROTENSET0_PROTREG28_Pos (28UL)

#define	MPU_PROTENSET0_PROTREG28_Msk (0x1UL << MPU_PROTENSET0_PROTREG28_Pos)

#define	MPU_PROTENSET0_PROTREG28_Disabled (0UL)

#define	MPU_PROTENSET0_PROTREG28_Enabled (1UL)

#define	MPU_PROTENSET0_PROTREG28_Set (1UL)

#define	MPU_PROTENSET0_PROTREG27_Pos (27UL)

#define	MPU_PROTENSET0_PROTREG27_Msk (0x1UL << MPU_PROTENSET0_PROTREG27_Pos)

#define	MPU_PROTENSET0_PROTREG27_Disabled (0UL)

#define	MPU_PROTENSET0_PROTREG27_Enabled (1UL)

#define	MPU_PROTENSET0_PROTREG27_Set (1UL)

#define	MPU_PROTENSET0_PROTREG26_Pos (26UL)

#define	MPU_PROTENSET0_PROTREG26_Msk (0x1UL << MPU_PROTENSET0_PROTREG26_Pos)

#define	MPU_PROTENSET0_PROTREG26_Disabled (0UL)

#define	MPU_PROTENSET0_PROTREG26_Enabled (1UL)

#define	MPU_PROTENSET0_PROTREG26_Set (1UL)

#define	MPU_PROTENSET0_PROTREG25_Pos (25UL)

#define	MPU_PROTENSET0_PROTREG25_Msk (0x1UL << MPU_PROTENSET0_PROTREG25_Pos)

#define	MPU_PROTENSET0_PROTREG25_Disabled (0UL)

#define	MPU_PROTENSET0_PROTREG25_Enabled (1UL)

#define	MPU_PROTENSET0_PROTREG25_Set (1UL)

#define	MPU_PROTENSET0_PROTREG24_Pos (24UL)

#define	MPU_PROTENSET0_PROTREG24_Msk (0x1UL << MPU_PROTENSET0_PROTREG24_Pos)

#define	MPU_PROTENSET0_PROTREG24_Disabled (0UL)

#define	MPU_PROTENSET0_PROTREG24_Enabled (1UL)

#define	MPU_PROTENSET0_PROTREG24_Set (1UL)

#define	MPU_PROTENSET0_PROTREG23_Pos (23UL)

#define	MPU_PROTENSET0_PROTREG23_Msk (0x1UL << MPU_PROTENSET0_PROTREG23_Pos)

#define	MPU_PROTENSET0_PROTREG23_Disabled (0UL)

#define	MPU_PROTENSET0_PROTREG23_Enabled (1UL)

#define	MPU_PROTENSET0_PROTREG23_Set (1UL)

#define	MPU_PROTENSET0_PROTREG22_Pos (22UL)

#define	MPU_PROTENSET0_PROTREG22_Msk (0x1UL << MPU_PROTENSET0_PROTREG22_Pos)

#define	MPU_PROTENSET0_PROTREG22_Disabled (0UL)

#define	MPU_PROTENSET0_PROTREG22_Enabled (1UL)

#define	MPU_PROTENSET0_PROTREG22_Set (1UL)

#define	MPU_PROTENSET0_PROTREG21_Pos (21UL)

#define	MPU_PROTENSET0_PROTREG21_Msk (0x1UL << MPU_PROTENSET0_PROTREG21_Pos)

#define	MPU_PROTENSET0_PROTREG21_Disabled (0UL)

#define	MPU_PROTENSET0_PROTREG21_Enabled (1UL)

#define	MPU_PROTENSET0_PROTREG21_Set (1UL)

#define	MPU_PROTENSET0_PROTREG20_Pos (20UL)

#define	MPU_PROTENSET0_PROTREG20_Msk (0x1UL << MPU_PROTENSET0_PROTREG20_Pos)

#define	MPU_PROTENSET0_PROTREG20_Disabled (0UL)

#define	MPU_PROTENSET0_PROTREG20_Enabled (1UL)

#define	MPU_PROTENSET0_PROTREG20_Set (1UL)

#define	MPU_PROTENSET0_PROTREG19_Pos (19UL)

#define	MPU_PROTENSET0_PROTREG19_Msk (0x1UL << MPU_PROTENSET0_PROTREG19_Pos)

#define	MPU_PROTENSET0_PROTREG19_Disabled (0UL)

#define	MPU_PROTENSET0_PROTREG19_Enabled (1UL)

#define	MPU_PROTENSET0_PROTREG19_Set (1UL)

#define	MPU_PROTENSET0_PROTREG18_Pos (18UL)

#define	MPU_PROTENSET0_PROTREG18_Msk (0x1UL << MPU_PROTENSET0_PROTREG18_Pos)

#define	MPU_PROTENSET0_PROTREG18_Disabled (0UL)

#define	MPU_PROTENSET0_PROTREG18_Enabled (1UL)

#define	MPU_PROTENSET0_PROTREG18_Set (1UL)

#define	MPU_PROTENSET0_PROTREG17_Pos (17UL)

#define	MPU_PROTENSET0_PROTREG17_Msk (0x1UL << MPU_PROTENSET0_PROTREG17_Pos)

#define	MPU_PROTENSET0_PROTREG17_Disabled (0UL)

#define	MPU_PROTENSET0_PROTREG17_Enabled (1UL)

#define	MPU_PROTENSET0_PROTREG17_Set (1UL)

#define	MPU_PROTENSET0_PROTREG16_Pos (16UL)

#define	MPU_PROTENSET0_PROTREG16_Msk (0x1UL << MPU_PROTENSET0_PROTREG16_Pos)

#define	MPU_PROTENSET0_PROTREG16_Disabled (0UL)

#define	MPU_PROTENSET0_PROTREG16_Enabled (1UL)

#define	MPU_PROTENSET0_PROTREG16_Set (1UL)

#define	MPU_PROTENSET0_PROTREG15_Pos (15UL)

#define	MPU_PROTENSET0_PROTREG15_Msk (0x1UL << MPU_PROTENSET0_PROTREG15_Pos)

#define	MPU_PROTENSET0_PROTREG15_Disabled (0UL)

#define	MPU_PROTENSET0_PROTREG15_Enabled (1UL)

#define	MPU_PROTENSET0_PROTREG15_Set (1UL)

#define	MPU_PROTENSET0_PROTREG14_Pos (14UL)

#define	MPU_PROTENSET0_PROTREG14_Msk (0x1UL << MPU_PROTENSET0_PROTREG14_Pos)

#define	MPU_PROTENSET0_PROTREG14_Disabled (0UL)

#define	MPU_PROTENSET0_PROTREG14_Enabled (1UL)

#define	MPU_PROTENSET0_PROTREG14_Set (1UL)

#define	MPU_PROTENSET0_PROTREG13_Pos (13UL)

#define	MPU_PROTENSET0_PROTREG13_Msk (0x1UL << MPU_PROTENSET0_PROTREG13_Pos)

#define	MPU_PROTENSET0_PROTREG13_Disabled (0UL)

#define	MPU_PROTENSET0_PROTREG13_Enabled (1UL)

#define	MPU_PROTENSET0_PROTREG13_Set (1UL)

#define	MPU_PROTENSET0_PROTREG12_Pos (12UL)

#define	MPU_PROTENSET0_PROTREG12_Msk (0x1UL << MPU_PROTENSET0_PROTREG12_Pos)

#define	MPU_PROTENSET0_PROTREG12_Disabled (0UL)

#define	MPU_PROTENSET0_PROTREG12_Enabled (1UL)

#define	MPU_PROTENSET0_PROTREG12_Set (1UL)

#define	MPU_PROTENSET0_PROTREG11_Pos (11UL)

#define	MPU_PROTENSET0_PROTREG11_Msk (0x1UL << MPU_PROTENSET0_PROTREG11_Pos)

#define	MPU_PROTENSET0_PROTREG11_Disabled (0UL)

#define	MPU_PROTENSET0_PROTREG11_Enabled (1UL)

#define	MPU_PROTENSET0_PROTREG11_Set (1UL)

#define	MPU_PROTENSET0_PROTREG10_Pos (10UL)

#define	MPU_PROTENSET0_PROTREG10_Msk (0x1UL << MPU_PROTENSET0_PROTREG10_Pos)

#define	MPU_PROTENSET0_PROTREG10_Disabled (0UL)

#define	MPU_PROTENSET0_PROTREG10_Enabled (1UL)

#define	MPU_PROTENSET0_PROTREG10_Set (1UL)

#define	MPU_PROTENSET0_PROTREG9_Pos (9UL)

#define	MPU_PROTENSET0_PROTREG9_Msk (0x1UL << MPU_PROTENSET0_PROTREG9_Pos)

#define	MPU_PROTENSET0_PROTREG9_Disabled (0UL)

#define	MPU_PROTENSET0_PROTREG9_Enabled (1UL)

#define	MPU_PROTENSET0_PROTREG9_Set (1UL)

#define	MPU_PROTENSET0_PROTREG8_Pos (8UL)

#define	MPU_PROTENSET0_PROTREG8_Msk (0x1UL << MPU_PROTENSET0_PROTREG8_Pos)

#define	MPU_PROTENSET0_PROTREG8_Disabled (0UL)

#define	MPU_PROTENSET0_PROTREG8_Enabled (1UL)

#define	MPU_PROTENSET0_PROTREG8_Set (1UL)

#define	MPU_PROTENSET0_PROTREG7_Pos (7UL)

#define	MPU_PROTENSET0_PROTREG7_Msk (0x1UL << MPU_PROTENSET0_PROTREG7_Pos)

#define	MPU_PROTENSET0_PROTREG7_Disabled (0UL)

#define	MPU_PROTENSET0_PROTREG7_Enabled (1UL)

#define	MPU_PROTENSET0_PROTREG7_Set (1UL)

#define	MPU_PROTENSET0_PROTREG6_Pos (6UL)

#define	MPU_PROTENSET0_PROTREG6_Msk (0x1UL << MPU_PROTENSET0_PROTREG6_Pos)

#define	MPU_PROTENSET0_PROTREG6_Disabled (0UL)

#define	MPU_PROTENSET0_PROTREG6_Enabled (1UL)

#define	MPU_PROTENSET0_PROTREG6_Set (1UL)

#define	MPU_PROTENSET0_PROTREG5_Pos (5UL)

#define	MPU_PROTENSET0_PROTREG5_Msk (0x1UL << MPU_PROTENSET0_PROTREG5_Pos)

#define	MPU_PROTENSET0_PROTREG5_Disabled (0UL)

#define	MPU_PROTENSET0_PROTREG5_Enabled (1UL)

#define	MPU_PROTENSET0_PROTREG5_Set (1UL)

#define	MPU_PROTENSET0_PROTREG4_Pos (4UL)

#define	MPU_PROTENSET0_PROTREG4_Msk (0x1UL << MPU_PROTENSET0_PROTREG4_Pos)

#define	MPU_PROTENSET0_PROTREG4_Disabled (0UL)

#define	MPU_PROTENSET0_PROTREG4_Enabled (1UL)

#define	MPU_PROTENSET0_PROTREG4_Set (1UL)

#define	MPU_PROTENSET0_PROTREG3_Pos (3UL)

#define	MPU_PROTENSET0_PROTREG3_Msk (0x1UL << MPU_PROTENSET0_PROTREG3_Pos)

#define	MPU_PROTENSET0_PROTREG3_Disabled (0UL)

#define	MPU_PROTENSET0_PROTREG3_Enabled (1UL)

#define	MPU_PROTENSET0_PROTREG3_Set (1UL)

#define	MPU_PROTENSET0_PROTREG2_Pos (2UL)

#define	MPU_PROTENSET0_PROTREG2_Msk (0x1UL << MPU_PROTENSET0_PROTREG2_Pos)

#define	MPU_PROTENSET0_PROTREG2_Disabled (0UL)

#define	MPU_PROTENSET0_PROTREG2_Enabled (1UL)

#define	MPU_PROTENSET0_PROTREG2_Set (1UL)

#define	MPU_PROTENSET0_PROTREG1_Pos (1UL)

#define	MPU_PROTENSET0_PROTREG1_Msk (0x1UL << MPU_PROTENSET0_PROTREG1_Pos)

#define	MPU_PROTENSET0_PROTREG1_Disabled (0UL)

#define	MPU_PROTENSET0_PROTREG1_Enabled (1UL)

#define	MPU_PROTENSET0_PROTREG1_Set (1UL)

#define	MPU_PROTENSET0_PROTREG0_Pos (0UL)

#define	MPU_PROTENSET0_PROTREG0_Msk (0x1UL << MPU_PROTENSET0_PROTREG0_Pos)

#define	MPU_PROTENSET0_PROTREG0_Disabled (0UL)

#define	MPU_PROTENSET0_PROTREG0_Enabled (1UL)

#define	MPU_PROTENSET0_PROTREG0_Set (1UL)

#define	MPU_PROTENSET1_PROTREG63_Pos (31UL)

#define	MPU_PROTENSET1_PROTREG63_Msk (0x1UL << MPU_PROTENSET1_PROTREG63_Pos)

#define	MPU_PROTENSET1_PROTREG63_Disabled (0UL)

#define	MPU_PROTENSET1_PROTREG63_Enabled (1UL)

#define	MPU_PROTENSET1_PROTREG63_Set (1UL)

#define	MPU_PROTENSET1_PROTREG62_Pos (30UL)

#define	MPU_PROTENSET1_PROTREG62_Msk (0x1UL << MPU_PROTENSET1_PROTREG62_Pos)

#define	MPU_PROTENSET1_PROTREG62_Disabled (0UL)

#define	MPU_PROTENSET1_PROTREG62_Enabled (1UL)

#define	MPU_PROTENSET1_PROTREG62_Set (1UL)

#define	MPU_PROTENSET1_PROTREG61_Pos (29UL)

#define	MPU_PROTENSET1_PROTREG61_Msk (0x1UL << MPU_PROTENSET1_PROTREG61_Pos)

#define	MPU_PROTENSET1_PROTREG61_Disabled (0UL)

#define	MPU_PROTENSET1_PROTREG61_Enabled (1UL)

#define	MPU_PROTENSET1_PROTREG61_Set (1UL)

#define	MPU_PROTENSET1_PROTREG60_Pos (28UL)

#define	MPU_PROTENSET1_PROTREG60_Msk (0x1UL << MPU_PROTENSET1_PROTREG60_Pos)

#define	MPU_PROTENSET1_PROTREG60_Disabled (0UL)

#define	MPU_PROTENSET1_PROTREG60_Enabled (1UL)

#define	MPU_PROTENSET1_PROTREG60_Set (1UL)

#define	MPU_PROTENSET1_PROTREG59_Pos (27UL)

#define	MPU_PROTENSET1_PROTREG59_Msk (0x1UL << MPU_PROTENSET1_PROTREG59_Pos)

#define	MPU_PROTENSET1_PROTREG59_Disabled (0UL)

#define	MPU_PROTENSET1_PROTREG59_Enabled (1UL)

#define	MPU_PROTENSET1_PROTREG59_Set (1UL)

#define	MPU_PROTENSET1_PROTREG58_Pos (26UL)

#define	MPU_PROTENSET1_PROTREG58_Msk (0x1UL << MPU_PROTENSET1_PROTREG58_Pos)

#define	MPU_PROTENSET1_PROTREG58_Disabled (0UL)

#define	MPU_PROTENSET1_PROTREG58_Enabled (1UL)

#define	MPU_PROTENSET1_PROTREG58_Set (1UL)

#define	MPU_PROTENSET1_PROTREG57_Pos (25UL)

#define	MPU_PROTENSET1_PROTREG57_Msk (0x1UL << MPU_PROTENSET1_PROTREG57_Pos)

#define	MPU_PROTENSET1_PROTREG57_Disabled (0UL)

#define	MPU_PROTENSET1_PROTREG57_Enabled (1UL)

#define	MPU_PROTENSET1_PROTREG57_Set (1UL)

#define	MPU_PROTENSET1_PROTREG56_Pos (24UL)

#define	MPU_PROTENSET1_PROTREG56_Msk (0x1UL << MPU_PROTENSET1_PROTREG56_Pos)

#define	MPU_PROTENSET1_PROTREG56_Disabled (0UL)

#define	MPU_PROTENSET1_PROTREG56_Enabled (1UL)

#define	MPU_PROTENSET1_PROTREG56_Set (1UL)

#define	MPU_PROTENSET1_PROTREG55_Pos (23UL)

#define	MPU_PROTENSET1_PROTREG55_Msk (0x1UL << MPU_PROTENSET1_PROTREG55_Pos)

#define	MPU_PROTENSET1_PROTREG55_Disabled (0UL)

#define	MPU_PROTENSET1_PROTREG55_Enabled (1UL)

#define	MPU_PROTENSET1_PROTREG55_Set (1UL)

#define	MPU_PROTENSET1_PROTREG54_Pos (22UL)

#define	MPU_PROTENSET1_PROTREG54_Msk (0x1UL << MPU_PROTENSET1_PROTREG54_Pos)

#define	MPU_PROTENSET1_PROTREG54_Disabled (0UL)

#define	MPU_PROTENSET1_PROTREG54_Enabled (1UL)

#define	MPU_PROTENSET1_PROTREG54_Set (1UL)

#define	MPU_PROTENSET1_PROTREG53_Pos (21UL)

#define	MPU_PROTENSET1_PROTREG53_Msk (0x1UL << MPU_PROTENSET1_PROTREG53_Pos)

#define	MPU_PROTENSET1_PROTREG53_Disabled (0UL)

#define	MPU_PROTENSET1_PROTREG53_Enabled (1UL)

#define	MPU_PROTENSET1_PROTREG53_Set (1UL)

#define	MPU_PROTENSET1_PROTREG52_Pos (20UL)

#define	MPU_PROTENSET1_PROTREG52_Msk (0x1UL << MPU_PROTENSET1_PROTREG52_Pos)

#define	MPU_PROTENSET1_PROTREG52_Disabled (0UL)

#define	MPU_PROTENSET1_PROTREG52_Enabled (1UL)

#define	MPU_PROTENSET1_PROTREG52_Set (1UL)

#define	MPU_PROTENSET1_PROTREG51_Pos (19UL)

#define	MPU_PROTENSET1_PROTREG51_Msk (0x1UL << MPU_PROTENSET1_PROTREG51_Pos)

#define	MPU_PROTENSET1_PROTREG51_Disabled (0UL)

#define	MPU_PROTENSET1_PROTREG51_Enabled (1UL)

#define	MPU_PROTENSET1_PROTREG51_Set (1UL)

#define	MPU_PROTENSET1_PROTREG50_Pos (18UL)

#define	MPU_PROTENSET1_PROTREG50_Msk (0x1UL << MPU_PROTENSET1_PROTREG50_Pos)

#define	MPU_PROTENSET1_PROTREG50_Disabled (0UL)

#define	MPU_PROTENSET1_PROTREG50_Enabled (1UL)

#define	MPU_PROTENSET1_PROTREG50_Set (1UL)

#define	MPU_PROTENSET1_PROTREG49_Pos (17UL)

#define	MPU_PROTENSET1_PROTREG49_Msk (0x1UL << MPU_PROTENSET1_PROTREG49_Pos)

#define	MPU_PROTENSET1_PROTREG49_Disabled (0UL)

#define	MPU_PROTENSET1_PROTREG49_Enabled (1UL)

#define	MPU_PROTENSET1_PROTREG49_Set (1UL)

#define	MPU_PROTENSET1_PROTREG48_Pos (16UL)

#define	MPU_PROTENSET1_PROTREG48_Msk (0x1UL << MPU_PROTENSET1_PROTREG48_Pos)

#define	MPU_PROTENSET1_PROTREG48_Disabled (0UL)

#define	MPU_PROTENSET1_PROTREG48_Enabled (1UL)

#define	MPU_PROTENSET1_PROTREG48_Set (1UL)

#define	MPU_PROTENSET1_PROTREG47_Pos (15UL)

#define	MPU_PROTENSET1_PROTREG47_Msk (0x1UL << MPU_PROTENSET1_PROTREG47_Pos)

#define	MPU_PROTENSET1_PROTREG47_Disabled (0UL)

#define	MPU_PROTENSET1_PROTREG47_Enabled (1UL)

#define	MPU_PROTENSET1_PROTREG47_Set (1UL)

#define	MPU_PROTENSET1_PROTREG46_Pos (14UL)

#define	MPU_PROTENSET1_PROTREG46_Msk (0x1UL << MPU_PROTENSET1_PROTREG46_Pos)

#define	MPU_PROTENSET1_PROTREG46_Disabled (0UL)

#define	MPU_PROTENSET1_PROTREG46_Enabled (1UL)

#define	MPU_PROTENSET1_PROTREG46_Set (1UL)

#define	MPU_PROTENSET1_PROTREG45_Pos (13UL)

#define	MPU_PROTENSET1_PROTREG45_Msk (0x1UL << MPU_PROTENSET1_PROTREG45_Pos)

#define	MPU_PROTENSET1_PROTREG45_Disabled (0UL)

#define	MPU_PROTENSET1_PROTREG45_Enabled (1UL)

#define	MPU_PROTENSET1_PROTREG45_Set (1UL)

#define	MPU_PROTENSET1_PROTREG44_Pos (12UL)

#define	MPU_PROTENSET1_PROTREG44_Msk (0x1UL << MPU_PROTENSET1_PROTREG44_Pos)

#define	MPU_PROTENSET1_PROTREG44_Disabled (0UL)

#define	MPU_PROTENSET1_PROTREG44_Enabled (1UL)

#define	MPU_PROTENSET1_PROTREG44_Set (1UL)

#define	MPU_PROTENSET1_PROTREG43_Pos (11UL)

#define	MPU_PROTENSET1_PROTREG43_Msk (0x1UL << MPU_PROTENSET1_PROTREG43_Pos)

#define	MPU_PROTENSET1_PROTREG43_Disabled (0UL)

#define	MPU_PROTENSET1_PROTREG43_Enabled (1UL)

#define	MPU_PROTENSET1_PROTREG43_Set (1UL)

#define	MPU_PROTENSET1_PROTREG42_Pos (10UL)

#define	MPU_PROTENSET1_PROTREG42_Msk (0x1UL << MPU_PROTENSET1_PROTREG42_Pos)

#define	MPU_PROTENSET1_PROTREG42_Disabled (0UL)

#define	MPU_PROTENSET1_PROTREG42_Enabled (1UL)

#define	MPU_PROTENSET1_PROTREG42_Set (1UL)

#define	MPU_PROTENSET1_PROTREG41_Pos (9UL)

#define	MPU_PROTENSET1_PROTREG41_Msk (0x1UL << MPU_PROTENSET1_PROTREG41_Pos)

#define	MPU_PROTENSET1_PROTREG41_Disabled (0UL)

#define	MPU_PROTENSET1_PROTREG41_Enabled (1UL)

#define	MPU_PROTENSET1_PROTREG41_Set (1UL)

#define	MPU_PROTENSET1_PROTREG40_Pos (8UL)

#define	MPU_PROTENSET1_PROTREG40_Msk (0x1UL << MPU_PROTENSET1_PROTREG40_Pos)

#define	MPU_PROTENSET1_PROTREG40_Disabled (0UL)

#define	MPU_PROTENSET1_PROTREG40_Enabled (1UL)

#define	MPU_PROTENSET1_PROTREG40_Set (1UL)

#define	MPU_PROTENSET1_PROTREG39_Pos (7UL)

#define	MPU_PROTENSET1_PROTREG39_Msk (0x1UL << MPU_PROTENSET1_PROTREG39_Pos)

#define	MPU_PROTENSET1_PROTREG39_Disabled (0UL)

#define	MPU_PROTENSET1_PROTREG39_Enabled (1UL)

#define	MPU_PROTENSET1_PROTREG39_Set (1UL)

#define	MPU_PROTENSET1_PROTREG38_Pos (6UL)

#define	MPU_PROTENSET1_PROTREG38_Msk (0x1UL << MPU_PROTENSET1_PROTREG38_Pos)

#define	MPU_PROTENSET1_PROTREG38_Disabled (0UL)

#define	MPU_PROTENSET1_PROTREG38_Enabled (1UL)

#define	MPU_PROTENSET1_PROTREG38_Set (1UL)

#define	MPU_PROTENSET1_PROTREG37_Pos (5UL)

#define	MPU_PROTENSET1_PROTREG37_Msk (0x1UL << MPU_PROTENSET1_PROTREG37_Pos)

#define	MPU_PROTENSET1_PROTREG37_Disabled (0UL)

#define	MPU_PROTENSET1_PROTREG37_Enabled (1UL)

#define	MPU_PROTENSET1_PROTREG37_Set (1UL)

#define	MPU_PROTENSET1_PROTREG36_Pos (4UL)

#define	MPU_PROTENSET1_PROTREG36_Msk (0x1UL << MPU_PROTENSET1_PROTREG36_Pos)

#define	MPU_PROTENSET1_PROTREG36_Disabled (0UL)

#define	MPU_PROTENSET1_PROTREG36_Enabled (1UL)

#define	MPU_PROTENSET1_PROTREG36_Set (1UL)

#define	MPU_PROTENSET1_PROTREG35_Pos (3UL)

#define	MPU_PROTENSET1_PROTREG35_Msk (0x1UL << MPU_PROTENSET1_PROTREG35_Pos)

#define	MPU_PROTENSET1_PROTREG35_Disabled (0UL)

#define	MPU_PROTENSET1_PROTREG35_Enabled (1UL)

#define	MPU_PROTENSET1_PROTREG35_Set (1UL)

#define	MPU_PROTENSET1_PROTREG34_Pos (2UL)

#define	MPU_PROTENSET1_PROTREG34_Msk (0x1UL << MPU_PROTENSET1_PROTREG34_Pos)

#define	MPU_PROTENSET1_PROTREG34_Disabled (0UL)

#define	MPU_PROTENSET1_PROTREG34_Enabled (1UL)

#define	MPU_PROTENSET1_PROTREG34_Set (1UL)

#define	MPU_PROTENSET1_PROTREG33_Pos (1UL)

#define	MPU_PROTENSET1_PROTREG33_Msk (0x1UL << MPU_PROTENSET1_PROTREG33_Pos)

#define	MPU_PROTENSET1_PROTREG33_Disabled (0UL)

#define	MPU_PROTENSET1_PROTREG33_Enabled (1UL)

#define	MPU_PROTENSET1_PROTREG33_Set (1UL)

#define	MPU_PROTENSET1_PROTREG32_Pos (0UL)

#define	MPU_PROTENSET1_PROTREG32_Msk (0x1UL << MPU_PROTENSET1_PROTREG32_Pos)

#define	MPU_PROTENSET1_PROTREG32_Disabled (0UL)

#define	MPU_PROTENSET1_PROTREG32_Enabled (1UL)

#define	MPU_PROTENSET1_PROTREG32_Set (1UL)

#define	MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL)

#define	MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos)

#define	MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL)

#define	MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL)

#define	MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos (0UL)

#define	MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Msk (0x3UL << MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos)

#define	MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_4k (0UL)

#define	NVMC_READY_READY_Pos (0UL)

#define	NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos)

#define	NVMC_READY_READY_Busy (0UL)

#define	NVMC_READY_READY_Ready (1UL)

#define	NVMC_CONFIG_WEN_Pos (0UL)

#define	NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos)

#define	NVMC_CONFIG_WEN_Ren (0x00UL)

#define	NVMC_CONFIG_WEN_Wen (0x01UL)

#define	NVMC_CONFIG_WEN_Een (0x02UL)

#define	NVMC_ERASEALL_ERASEALL_Pos (0UL)

#define	NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos)

#define	NVMC_ERASEALL_ERASEALL_NoOperation (0UL)

#define	NVMC_ERASEALL_ERASEALL_Erase (1UL)

#define	NVMC_ERASEUICR_ERASEUICR_Pos (0UL)

#define	NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos)

#define	NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL)

#define	NVMC_ERASEUICR_ERASEUICR_Erase (1UL)

#define	POWER_INTENSET_POFWARN_Pos (2UL)

#define	POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos)

#define	POWER_INTENSET_POFWARN_Disabled (0UL)

#define	POWER_INTENSET_POFWARN_Enabled (1UL)

#define	POWER_INTENSET_POFWARN_Set (1UL)

#define	POWER_INTENCLR_POFWARN_Pos (2UL)

#define	POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos)

#define	POWER_INTENCLR_POFWARN_Disabled (0UL)

#define	POWER_INTENCLR_POFWARN_Enabled (1UL)

#define	POWER_INTENCLR_POFWARN_Clear (1UL)

#define	POWER_RESETREAS_DIF_Pos (18UL)

#define	POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos)

#define	POWER_RESETREAS_DIF_NotDetected (0UL)

#define	POWER_RESETREAS_DIF_Detected (1UL)

#define	POWER_RESETREAS_LPCOMP_Pos (17UL)

#define	POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos)

#define	POWER_RESETREAS_LPCOMP_NotDetected (0UL)

#define	POWER_RESETREAS_LPCOMP_Detected (1UL)

#define	POWER_RESETREAS_OFF_Pos (16UL)

#define	POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos)

#define	POWER_RESETREAS_OFF_NotDetected (0UL)

#define	POWER_RESETREAS_OFF_Detected (1UL)

#define	POWER_RESETREAS_LOCKUP_Pos (3UL)

#define	POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos)

#define	POWER_RESETREAS_LOCKUP_NotDetected (0UL)

#define	POWER_RESETREAS_LOCKUP_Detected (1UL)

#define	POWER_RESETREAS_SREQ_Pos (2UL)

#define	POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos)

#define	POWER_RESETREAS_SREQ_NotDetected (0UL)

#define	POWER_RESETREAS_SREQ_Detected (1UL)

#define	POWER_RESETREAS_DOG_Pos (1UL)

#define	POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos)

#define	POWER_RESETREAS_DOG_NotDetected (0UL)

#define	POWER_RESETREAS_DOG_Detected (1UL)

#define	POWER_RESETREAS_RESETPIN_Pos (0UL)

#define	POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos)

#define	POWER_RESETREAS_RESETPIN_NotDetected (0UL)

#define	POWER_RESETREAS_RESETPIN_Detected (1UL)

#define	POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL)

#define	POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos)

#define	POWER_RAMSTATUS_RAMBLOCK3_Off (0UL)

#define	POWER_RAMSTATUS_RAMBLOCK3_On (1UL)

#define	POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL)

#define	POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos)

#define	POWER_RAMSTATUS_RAMBLOCK2_Off (0UL)

#define	POWER_RAMSTATUS_RAMBLOCK2_On (1UL)

#define	POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL)

#define	POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos)

#define	POWER_RAMSTATUS_RAMBLOCK1_Off (0UL)

#define	POWER_RAMSTATUS_RAMBLOCK1_On (1UL)

#define	POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL)

#define	POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos)

#define	POWER_RAMSTATUS_RAMBLOCK0_Off (0UL)

#define	POWER_RAMSTATUS_RAMBLOCK0_On (1UL)

#define	POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL)

#define	POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos)

#define	POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL)

#define	POWER_POFCON_THRESHOLD_Pos (1UL)

#define	POWER_POFCON_THRESHOLD_Msk (0x3UL << POWER_POFCON_THRESHOLD_Pos)

#define	POWER_POFCON_THRESHOLD_V21 (0x00UL)

#define	POWER_POFCON_THRESHOLD_V23 (0x01UL)

#define	POWER_POFCON_THRESHOLD_V25 (0x02UL)

#define	POWER_POFCON_THRESHOLD_V27 (0x03UL)

#define	POWER_POFCON_POF_Pos (0UL)

#define	POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos)

#define	POWER_POFCON_POF_Disabled (0UL)

#define	POWER_POFCON_POF_Enabled (1UL)

#define	POWER_GPREGRET_GPREGRET_Pos (0UL)

#define	POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos)

#define	POWER_RAMON_OFFRAM1_Pos (17UL)

#define	POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos)

#define	POWER_RAMON_OFFRAM1_RAM1Off (0UL)

#define	POWER_RAMON_OFFRAM1_RAM1On (1UL)

#define	POWER_RAMON_OFFRAM0_Pos (16UL)

#define	POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos)

#define	POWER_RAMON_OFFRAM0_RAM0Off (0UL)

#define	POWER_RAMON_OFFRAM0_RAM0On (1UL)

#define	POWER_RAMON_ONRAM1_Pos (1UL)

#define	POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos)

#define	POWER_RAMON_ONRAM1_RAM1Off (0UL)

#define	POWER_RAMON_ONRAM1_RAM1On (1UL)

#define	POWER_RAMON_ONRAM0_Pos (0UL)

#define	POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos)

#define	POWER_RAMON_ONRAM0_RAM0Off (0UL)

#define	POWER_RAMON_ONRAM0_RAM0On (1UL)

#define	POWER_RESET_RESET_Pos (0UL)

#define	POWER_RESET_RESET_Msk (0x1UL << POWER_RESET_RESET_Pos)

#define	POWER_RESET_RESET_Disabled (0UL)

#define	POWER_RESET_RESET_Enabled (1UL)

#define	POWER_RAMONB_OFFRAM3_Pos (17UL)

#define	POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos)

#define	POWER_RAMONB_OFFRAM3_RAM3Off (0UL)

#define	POWER_RAMONB_OFFRAM3_RAM3On (1UL)

#define	POWER_RAMONB_OFFRAM2_Pos (16UL)

#define	POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos)

#define	POWER_RAMONB_OFFRAM2_RAM2Off (0UL)

#define	POWER_RAMONB_OFFRAM2_RAM2On (1UL)

#define	POWER_RAMONB_ONRAM3_Pos (1UL)

#define	POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos)

#define	POWER_RAMONB_ONRAM3_RAM3Off (0UL)

#define	POWER_RAMONB_ONRAM3_RAM3On (1UL)

#define	POWER_RAMONB_ONRAM2_Pos (0UL)

#define	POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos)

#define	POWER_RAMONB_ONRAM2_RAM2Off (0UL)

#define	POWER_RAMONB_ONRAM2_RAM2On (1UL)

#define	POWER_DCDCEN_DCDCEN_Pos (0UL)

#define	POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos)

#define	POWER_DCDCEN_DCDCEN_Disabled (0UL)

#define	POWER_DCDCEN_DCDCEN_Enabled (1UL)

#define	POWER_DCDCFORCE_FORCEON_Pos (1UL)

#define	POWER_DCDCFORCE_FORCEON_Msk (0x1UL << POWER_DCDCFORCE_FORCEON_Pos)

#define	POWER_DCDCFORCE_FORCEON_NoForce (0UL)

#define	POWER_DCDCFORCE_FORCEON_Force (1UL)

#define	POWER_DCDCFORCE_FORCEOFF_Pos (0UL)

#define	POWER_DCDCFORCE_FORCEOFF_Msk (0x1UL << POWER_DCDCFORCE_FORCEOFF_Pos)

#define	POWER_DCDCFORCE_FORCEOFF_NoForce (0UL)

#define	POWER_DCDCFORCE_FORCEOFF_Force (1UL)

#define	PPI_CHEN_CH31_Pos (31UL)

#define	PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos)

#define	PPI_CHEN_CH31_Disabled (0UL)

#define	PPI_CHEN_CH31_Enabled (1UL)

#define	PPI_CHEN_CH30_Pos (30UL)

#define	PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos)

#define	PPI_CHEN_CH30_Disabled (0UL)

#define	PPI_CHEN_CH30_Enabled (1UL)

#define	PPI_CHEN_CH29_Pos (29UL)

#define	PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos)

#define	PPI_CHEN_CH29_Disabled (0UL)

#define	PPI_CHEN_CH29_Enabled (1UL)

#define	PPI_CHEN_CH28_Pos (28UL)

#define	PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos)

#define	PPI_CHEN_CH28_Disabled (0UL)

#define	PPI_CHEN_CH28_Enabled (1UL)

#define	PPI_CHEN_CH27_Pos (27UL)

#define	PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos)

#define	PPI_CHEN_CH27_Disabled (0UL)

#define	PPI_CHEN_CH27_Enabled (1UL)

#define	PPI_CHEN_CH26_Pos (26UL)

#define	PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos)

#define	PPI_CHEN_CH26_Disabled (0UL)

#define	PPI_CHEN_CH26_Enabled (1UL)

#define	PPI_CHEN_CH25_Pos (25UL)

#define	PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos)

#define	PPI_CHEN_CH25_Disabled (0UL)

#define	PPI_CHEN_CH25_Enabled (1UL)

#define	PPI_CHEN_CH24_Pos (24UL)

#define	PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos)

#define	PPI_CHEN_CH24_Disabled (0UL)

#define	PPI_CHEN_CH24_Enabled (1UL)

#define	PPI_CHEN_CH23_Pos (23UL)

#define	PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos)

#define	PPI_CHEN_CH23_Disabled (0UL)

#define	PPI_CHEN_CH23_Enabled (1UL)

#define	PPI_CHEN_CH22_Pos (22UL)

#define	PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos)

#define	PPI_CHEN_CH22_Disabled (0UL)

#define	PPI_CHEN_CH22_Enabled (1UL)

#define	PPI_CHEN_CH21_Pos (21UL)

#define	PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos)

#define	PPI_CHEN_CH21_Disabled (0UL)

#define	PPI_CHEN_CH21_Enabled (1UL)

#define	PPI_CHEN_CH20_Pos (20UL)

#define	PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos)

#define	PPI_CHEN_CH20_Disabled (0UL)

#define	PPI_CHEN_CH20_Enabled (1UL)

#define	PPI_CHEN_CH15_Pos (15UL)

#define	PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos)

#define	PPI_CHEN_CH15_Disabled (0UL)

#define	PPI_CHEN_CH15_Enabled (1UL)

#define	PPI_CHEN_CH14_Pos (14UL)

#define	PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos)

#define	PPI_CHEN_CH14_Disabled (0UL)

#define	PPI_CHEN_CH14_Enabled (1UL)

#define	PPI_CHEN_CH13_Pos (13UL)

#define	PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos)

#define	PPI_CHEN_CH13_Disabled (0UL)

#define	PPI_CHEN_CH13_Enabled (1UL)

#define	PPI_CHEN_CH12_Pos (12UL)

#define	PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos)

#define	PPI_CHEN_CH12_Disabled (0UL)

#define	PPI_CHEN_CH12_Enabled (1UL)

#define	PPI_CHEN_CH11_Pos (11UL)

#define	PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos)

#define	PPI_CHEN_CH11_Disabled (0UL)

#define	PPI_CHEN_CH11_Enabled (1UL)

#define	PPI_CHEN_CH10_Pos (10UL)

#define	PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos)

#define	PPI_CHEN_CH10_Disabled (0UL)

#define	PPI_CHEN_CH10_Enabled (1UL)

#define	PPI_CHEN_CH9_Pos (9UL)

#define	PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos)

#define	PPI_CHEN_CH9_Disabled (0UL)

#define	PPI_CHEN_CH9_Enabled (1UL)

#define	PPI_CHEN_CH8_Pos (8UL)

#define	PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos)

#define	PPI_CHEN_CH8_Disabled (0UL)

#define	PPI_CHEN_CH8_Enabled (1UL)

#define	PPI_CHEN_CH7_Pos (7UL)

#define	PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos)

#define	PPI_CHEN_CH7_Disabled (0UL)

#define	PPI_CHEN_CH7_Enabled (1UL)

#define	PPI_CHEN_CH6_Pos (6UL)

#define	PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos)

#define	PPI_CHEN_CH6_Disabled (0UL)

#define	PPI_CHEN_CH6_Enabled (1UL)

#define	PPI_CHEN_CH5_Pos (5UL)

#define	PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos)

#define	PPI_CHEN_CH5_Disabled (0UL)

#define	PPI_CHEN_CH5_Enabled (1UL)

#define	PPI_CHEN_CH4_Pos (4UL)

#define	PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos)

#define	PPI_CHEN_CH4_Disabled (0UL)

#define	PPI_CHEN_CH4_Enabled (1UL)

#define	PPI_CHEN_CH3_Pos (3UL)

#define	PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos)

#define	PPI_CHEN_CH3_Disabled (0UL)

#define	PPI_CHEN_CH3_Enabled (1UL)

#define	PPI_CHEN_CH2_Pos (2UL)

#define	PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos)

#define	PPI_CHEN_CH2_Disabled (0UL)

#define	PPI_CHEN_CH2_Enabled (1UL)

#define	PPI_CHEN_CH1_Pos (1UL)

#define	PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos)

#define	PPI_CHEN_CH1_Disabled (0UL)

#define	PPI_CHEN_CH1_Enabled (1UL)

#define	PPI_CHEN_CH0_Pos (0UL)

#define	PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos)

#define	PPI_CHEN_CH0_Disabled (0UL)

#define	PPI_CHEN_CH0_Enabled (1UL)

#define	PPI_CHENSET_CH31_Pos (31UL)

#define	PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos)

#define	PPI_CHENSET_CH31_Disabled (0UL)

#define	PPI_CHENSET_CH31_Enabled (1UL)

#define	PPI_CHENSET_CH31_Set (1UL)

#define	PPI_CHENSET_CH30_Pos (30UL)

#define	PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos)

#define	PPI_CHENSET_CH30_Disabled (0UL)

#define	PPI_CHENSET_CH30_Enabled (1UL)

#define	PPI_CHENSET_CH30_Set (1UL)

#define	PPI_CHENSET_CH29_Pos (29UL)

#define	PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos)

#define	PPI_CHENSET_CH29_Disabled (0UL)

#define	PPI_CHENSET_CH29_Enabled (1UL)

#define	PPI_CHENSET_CH29_Set (1UL)

#define	PPI_CHENSET_CH28_Pos (28UL)

#define	PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos)

#define	PPI_CHENSET_CH28_Disabled (0UL)

#define	PPI_CHENSET_CH28_Enabled (1UL)

#define	PPI_CHENSET_CH28_Set (1UL)

#define	PPI_CHENSET_CH27_Pos (27UL)

#define	PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos)

#define	PPI_CHENSET_CH27_Disabled (0UL)

#define	PPI_CHENSET_CH27_Enabled (1UL)

#define	PPI_CHENSET_CH27_Set (1UL)

#define	PPI_CHENSET_CH26_Pos (26UL)

#define	PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos)

#define	PPI_CHENSET_CH26_Disabled (0UL)

#define	PPI_CHENSET_CH26_Enabled (1UL)

#define	PPI_CHENSET_CH26_Set (1UL)

#define	PPI_CHENSET_CH25_Pos (25UL)

#define	PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos)

#define	PPI_CHENSET_CH25_Disabled (0UL)

#define	PPI_CHENSET_CH25_Enabled (1UL)

#define	PPI_CHENSET_CH25_Set (1UL)

#define	PPI_CHENSET_CH24_Pos (24UL)

#define	PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos)

#define	PPI_CHENSET_CH24_Disabled (0UL)

#define	PPI_CHENSET_CH24_Enabled (1UL)

#define	PPI_CHENSET_CH24_Set (1UL)

#define	PPI_CHENSET_CH23_Pos (23UL)

#define	PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos)

#define	PPI_CHENSET_CH23_Disabled (0UL)

#define	PPI_CHENSET_CH23_Enabled (1UL)

#define	PPI_CHENSET_CH23_Set (1UL)

#define	PPI_CHENSET_CH22_Pos (22UL)

#define	PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos)

#define	PPI_CHENSET_CH22_Disabled (0UL)

#define	PPI_CHENSET_CH22_Enabled (1UL)

#define	PPI_CHENSET_CH22_Set (1UL)

#define	PPI_CHENSET_CH21_Pos (21UL)

#define	PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos)

#define	PPI_CHENSET_CH21_Disabled (0UL)

#define	PPI_CHENSET_CH21_Enabled (1UL)

#define	PPI_CHENSET_CH21_Set (1UL)

#define	PPI_CHENSET_CH20_Pos (20UL)

#define	PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos)

#define	PPI_CHENSET_CH20_Disabled (0UL)

#define	PPI_CHENSET_CH20_Enabled (1UL)

#define	PPI_CHENSET_CH20_Set (1UL)

#define	PPI_CHENSET_CH15_Pos (15UL)

#define	PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos)

#define	PPI_CHENSET_CH15_Disabled (0UL)

#define	PPI_CHENSET_CH15_Enabled (1UL)

#define	PPI_CHENSET_CH15_Set (1UL)

#define	PPI_CHENSET_CH14_Pos (14UL)

#define	PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos)

#define	PPI_CHENSET_CH14_Disabled (0UL)

#define	PPI_CHENSET_CH14_Enabled (1UL)

#define	PPI_CHENSET_CH14_Set (1UL)

#define	PPI_CHENSET_CH13_Pos (13UL)

#define	PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos)

#define	PPI_CHENSET_CH13_Disabled (0UL)

#define	PPI_CHENSET_CH13_Enabled (1UL)

#define	PPI_CHENSET_CH13_Set (1UL)

#define	PPI_CHENSET_CH12_Pos (12UL)

#define	PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos)

#define	PPI_CHENSET_CH12_Disabled (0UL)

#define	PPI_CHENSET_CH12_Enabled (1UL)

#define	PPI_CHENSET_CH12_Set (1UL)

#define	PPI_CHENSET_CH11_Pos (11UL)

#define	PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos)

#define	PPI_CHENSET_CH11_Disabled (0UL)

#define	PPI_CHENSET_CH11_Enabled (1UL)

#define	PPI_CHENSET_CH11_Set (1UL)

#define	PPI_CHENSET_CH10_Pos (10UL)

#define	PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos)

#define	PPI_CHENSET_CH10_Disabled (0UL)

#define	PPI_CHENSET_CH10_Enabled (1UL)

#define	PPI_CHENSET_CH10_Set (1UL)

#define	PPI_CHENSET_CH9_Pos (9UL)

#define	PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos)

#define	PPI_CHENSET_CH9_Disabled (0UL)

#define	PPI_CHENSET_CH9_Enabled (1UL)

#define	PPI_CHENSET_CH9_Set (1UL)

#define	PPI_CHENSET_CH8_Pos (8UL)

#define	PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos)

#define	PPI_CHENSET_CH8_Disabled (0UL)

#define	PPI_CHENSET_CH8_Enabled (1UL)

#define	PPI_CHENSET_CH8_Set (1UL)

#define	PPI_CHENSET_CH7_Pos (7UL)

#define	PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos)

#define	PPI_CHENSET_CH7_Disabled (0UL)

#define	PPI_CHENSET_CH7_Enabled (1UL)

#define	PPI_CHENSET_CH7_Set (1UL)

#define	PPI_CHENSET_CH6_Pos (6UL)

#define	PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos)

#define	PPI_CHENSET_CH6_Disabled (0UL)

#define	PPI_CHENSET_CH6_Enabled (1UL)

#define	PPI_CHENSET_CH6_Set (1UL)

#define	PPI_CHENSET_CH5_Pos (5UL)

#define	PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos)

#define	PPI_CHENSET_CH5_Disabled (0UL)

#define	PPI_CHENSET_CH5_Enabled (1UL)

#define	PPI_CHENSET_CH5_Set (1UL)

#define	PPI_CHENSET_CH4_Pos (4UL)

#define	PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos)

#define	PPI_CHENSET_CH4_Disabled (0UL)

#define	PPI_CHENSET_CH4_Enabled (1UL)

#define	PPI_CHENSET_CH4_Set (1UL)

#define	PPI_CHENSET_CH3_Pos (3UL)

#define	PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos)

#define	PPI_CHENSET_CH3_Disabled (0UL)

#define	PPI_CHENSET_CH3_Enabled (1UL)

#define	PPI_CHENSET_CH3_Set (1UL)

#define	PPI_CHENSET_CH2_Pos (2UL)

#define	PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos)

#define	PPI_CHENSET_CH2_Disabled (0UL)

#define	PPI_CHENSET_CH2_Enabled (1UL)

#define	PPI_CHENSET_CH2_Set (1UL)

#define	PPI_CHENSET_CH1_Pos (1UL)

#define	PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos)

#define	PPI_CHENSET_CH1_Disabled (0UL)

#define	PPI_CHENSET_CH1_Enabled (1UL)

#define	PPI_CHENSET_CH1_Set (1UL)

#define	PPI_CHENSET_CH0_Pos (0UL)

#define	PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos)

#define	PPI_CHENSET_CH0_Disabled (0UL)

#define	PPI_CHENSET_CH0_Enabled (1UL)

#define	PPI_CHENSET_CH0_Set (1UL)

#define	PPI_CHENCLR_CH31_Pos (31UL)

#define	PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos)

#define	PPI_CHENCLR_CH31_Disabled (0UL)

#define	PPI_CHENCLR_CH31_Enabled (1UL)

#define	PPI_CHENCLR_CH31_Clear (1UL)

#define	PPI_CHENCLR_CH30_Pos (30UL)

#define	PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos)

#define	PPI_CHENCLR_CH30_Disabled (0UL)

#define	PPI_CHENCLR_CH30_Enabled (1UL)

#define	PPI_CHENCLR_CH30_Clear (1UL)

#define	PPI_CHENCLR_CH29_Pos (29UL)

#define	PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos)

#define	PPI_CHENCLR_CH29_Disabled (0UL)

#define	PPI_CHENCLR_CH29_Enabled (1UL)

#define	PPI_CHENCLR_CH29_Clear (1UL)

#define	PPI_CHENCLR_CH28_Pos (28UL)

#define	PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos)

#define	PPI_CHENCLR_CH28_Disabled (0UL)

#define	PPI_CHENCLR_CH28_Enabled (1UL)

#define	PPI_CHENCLR_CH28_Clear (1UL)

#define	PPI_CHENCLR_CH27_Pos (27UL)

#define	PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos)

#define	PPI_CHENCLR_CH27_Disabled (0UL)

#define	PPI_CHENCLR_CH27_Enabled (1UL)

#define	PPI_CHENCLR_CH27_Clear (1UL)

#define	PPI_CHENCLR_CH26_Pos (26UL)

#define	PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos)

#define	PPI_CHENCLR_CH26_Disabled (0UL)

#define	PPI_CHENCLR_CH26_Enabled (1UL)

#define	PPI_CHENCLR_CH26_Clear (1UL)

#define	PPI_CHENCLR_CH25_Pos (25UL)

#define	PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos)

#define	PPI_CHENCLR_CH25_Disabled (0UL)

#define	PPI_CHENCLR_CH25_Enabled (1UL)

#define	PPI_CHENCLR_CH25_Clear (1UL)

#define	PPI_CHENCLR_CH24_Pos (24UL)

#define	PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos)

#define	PPI_CHENCLR_CH24_Disabled (0UL)

#define	PPI_CHENCLR_CH24_Enabled (1UL)

#define	PPI_CHENCLR_CH24_Clear (1UL)

#define	PPI_CHENCLR_CH23_Pos (23UL)

#define	PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos)

#define	PPI_CHENCLR_CH23_Disabled (0UL)

#define	PPI_CHENCLR_CH23_Enabled (1UL)

#define	PPI_CHENCLR_CH23_Clear (1UL)

#define	PPI_CHENCLR_CH22_Pos (22UL)

#define	PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos)

#define	PPI_CHENCLR_CH22_Disabled (0UL)

#define	PPI_CHENCLR_CH22_Enabled (1UL)

#define	PPI_CHENCLR_CH22_Clear (1UL)

#define	PPI_CHENCLR_CH21_Pos (21UL)

#define	PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos)

#define	PPI_CHENCLR_CH21_Disabled (0UL)

#define	PPI_CHENCLR_CH21_Enabled (1UL)

#define	PPI_CHENCLR_CH21_Clear (1UL)

#define	PPI_CHENCLR_CH20_Pos (20UL)

#define	PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos)

#define	PPI_CHENCLR_CH20_Disabled (0UL)

#define	PPI_CHENCLR_CH20_Enabled (1UL)

#define	PPI_CHENCLR_CH20_Clear (1UL)

#define	PPI_CHENCLR_CH15_Pos (15UL)

#define	PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos)

#define	PPI_CHENCLR_CH15_Disabled (0UL)

#define	PPI_CHENCLR_CH15_Enabled (1UL)

#define	PPI_CHENCLR_CH15_Clear (1UL)

#define	PPI_CHENCLR_CH14_Pos (14UL)

#define	PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos)

#define	PPI_CHENCLR_CH14_Disabled (0UL)

#define	PPI_CHENCLR_CH14_Enabled (1UL)

#define	PPI_CHENCLR_CH14_Clear (1UL)

#define	PPI_CHENCLR_CH13_Pos (13UL)

#define	PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos)

#define	PPI_CHENCLR_CH13_Disabled (0UL)

#define	PPI_CHENCLR_CH13_Enabled (1UL)

#define	PPI_CHENCLR_CH13_Clear (1UL)

#define	PPI_CHENCLR_CH12_Pos (12UL)

#define	PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos)

#define	PPI_CHENCLR_CH12_Disabled (0UL)

#define	PPI_CHENCLR_CH12_Enabled (1UL)

#define	PPI_CHENCLR_CH12_Clear (1UL)

#define	PPI_CHENCLR_CH11_Pos (11UL)

#define	PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos)

#define	PPI_CHENCLR_CH11_Disabled (0UL)

#define	PPI_CHENCLR_CH11_Enabled (1UL)

#define	PPI_CHENCLR_CH11_Clear (1UL)

#define	PPI_CHENCLR_CH10_Pos (10UL)

#define	PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos)

#define	PPI_CHENCLR_CH10_Disabled (0UL)

#define	PPI_CHENCLR_CH10_Enabled (1UL)

#define	PPI_CHENCLR_CH10_Clear (1UL)

#define	PPI_CHENCLR_CH9_Pos (9UL)

#define	PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos)

#define	PPI_CHENCLR_CH9_Disabled (0UL)

#define	PPI_CHENCLR_CH9_Enabled (1UL)

#define	PPI_CHENCLR_CH9_Clear (1UL)

#define	PPI_CHENCLR_CH8_Pos (8UL)

#define	PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos)

#define	PPI_CHENCLR_CH8_Disabled (0UL)

#define	PPI_CHENCLR_CH8_Enabled (1UL)

#define	PPI_CHENCLR_CH8_Clear (1UL)

#define	PPI_CHENCLR_CH7_Pos (7UL)

#define	PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos)

#define	PPI_CHENCLR_CH7_Disabled (0UL)

#define	PPI_CHENCLR_CH7_Enabled (1UL)

#define	PPI_CHENCLR_CH7_Clear (1UL)

#define	PPI_CHENCLR_CH6_Pos (6UL)

#define	PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos)

#define	PPI_CHENCLR_CH6_Disabled (0UL)

#define	PPI_CHENCLR_CH6_Enabled (1UL)

#define	PPI_CHENCLR_CH6_Clear (1UL)

#define	PPI_CHENCLR_CH5_Pos (5UL)

#define	PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos)

#define	PPI_CHENCLR_CH5_Disabled (0UL)

#define	PPI_CHENCLR_CH5_Enabled (1UL)

#define	PPI_CHENCLR_CH5_Clear (1UL)

#define	PPI_CHENCLR_CH4_Pos (4UL)

#define	PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos)

#define	PPI_CHENCLR_CH4_Disabled (0UL)

#define	PPI_CHENCLR_CH4_Enabled (1UL)

#define	PPI_CHENCLR_CH4_Clear (1UL)

#define	PPI_CHENCLR_CH3_Pos (3UL)

#define	PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos)

#define	PPI_CHENCLR_CH3_Disabled (0UL)

#define	PPI_CHENCLR_CH3_Enabled (1UL)

#define	PPI_CHENCLR_CH3_Clear (1UL)

#define	PPI_CHENCLR_CH2_Pos (2UL)

#define	PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos)

#define	PPI_CHENCLR_CH2_Disabled (0UL)

#define	PPI_CHENCLR_CH2_Enabled (1UL)

#define	PPI_CHENCLR_CH2_Clear (1UL)

#define	PPI_CHENCLR_CH1_Pos (1UL)

#define	PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos)

#define	PPI_CHENCLR_CH1_Disabled (0UL)

#define	PPI_CHENCLR_CH1_Enabled (1UL)

#define	PPI_CHENCLR_CH1_Clear (1UL)

#define	PPI_CHENCLR_CH0_Pos (0UL)

#define	PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos)

#define	PPI_CHENCLR_CH0_Disabled (0UL)

#define	PPI_CHENCLR_CH0_Enabled (1UL)

#define	PPI_CHENCLR_CH0_Clear (1UL)

#define	PPI_CHG_CH31_Pos (31UL)

#define	PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos)

#define	PPI_CHG_CH31_Excluded (0UL)

#define	PPI_CHG_CH31_Included (1UL)

#define	PPI_CHG_CH30_Pos (30UL)

#define	PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos)

#define	PPI_CHG_CH30_Excluded (0UL)

#define	PPI_CHG_CH30_Included (1UL)

#define	PPI_CHG_CH29_Pos (29UL)

#define	PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos)

#define	PPI_CHG_CH29_Excluded (0UL)

#define	PPI_CHG_CH29_Included (1UL)

#define	PPI_CHG_CH28_Pos (28UL)

#define	PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos)

#define	PPI_CHG_CH28_Excluded (0UL)

#define	PPI_CHG_CH28_Included (1UL)

#define	PPI_CHG_CH27_Pos (27UL)

#define	PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos)

#define	PPI_CHG_CH27_Excluded (0UL)

#define	PPI_CHG_CH27_Included (1UL)

#define	PPI_CHG_CH26_Pos (26UL)

#define	PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos)

#define	PPI_CHG_CH26_Excluded (0UL)

#define	PPI_CHG_CH26_Included (1UL)

#define	PPI_CHG_CH25_Pos (25UL)

#define	PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos)

#define	PPI_CHG_CH25_Excluded (0UL)

#define	PPI_CHG_CH25_Included (1UL)

#define	PPI_CHG_CH24_Pos (24UL)

#define	PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos)

#define	PPI_CHG_CH24_Excluded (0UL)

#define	PPI_CHG_CH24_Included (1UL)

#define	PPI_CHG_CH23_Pos (23UL)

#define	PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos)

#define	PPI_CHG_CH23_Excluded (0UL)

#define	PPI_CHG_CH23_Included (1UL)

#define	PPI_CHG_CH22_Pos (22UL)

#define	PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos)

#define	PPI_CHG_CH22_Excluded (0UL)

#define	PPI_CHG_CH22_Included (1UL)

#define	PPI_CHG_CH21_Pos (21UL)

#define	PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos)

#define	PPI_CHG_CH21_Excluded (0UL)

#define	PPI_CHG_CH21_Included (1UL)

#define	PPI_CHG_CH20_Pos (20UL)

#define	PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos)

#define	PPI_CHG_CH20_Excluded (0UL)

#define	PPI_CHG_CH20_Included (1UL)

#define	PPI_CHG_CH15_Pos (15UL)

#define	PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos)

#define	PPI_CHG_CH15_Excluded (0UL)

#define	PPI_CHG_CH15_Included (1UL)

#define	PPI_CHG_CH14_Pos (14UL)

#define	PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos)

#define	PPI_CHG_CH14_Excluded (0UL)

#define	PPI_CHG_CH14_Included (1UL)

#define	PPI_CHG_CH13_Pos (13UL)

#define	PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos)

#define	PPI_CHG_CH13_Excluded (0UL)

#define	PPI_CHG_CH13_Included (1UL)

#define	PPI_CHG_CH12_Pos (12UL)

#define	PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos)

#define	PPI_CHG_CH12_Excluded (0UL)

#define	PPI_CHG_CH12_Included (1UL)

#define	PPI_CHG_CH11_Pos (11UL)

#define	PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos)

#define	PPI_CHG_CH11_Excluded (0UL)

#define	PPI_CHG_CH11_Included (1UL)

#define	PPI_CHG_CH10_Pos (10UL)

#define	PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos)

#define	PPI_CHG_CH10_Excluded (0UL)

#define	PPI_CHG_CH10_Included (1UL)

#define	PPI_CHG_CH9_Pos (9UL)

#define	PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos)

#define	PPI_CHG_CH9_Excluded (0UL)

#define	PPI_CHG_CH9_Included (1UL)

#define	PPI_CHG_CH8_Pos (8UL)

#define	PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos)

#define	PPI_CHG_CH8_Excluded (0UL)

#define	PPI_CHG_CH8_Included (1UL)

#define	PPI_CHG_CH7_Pos (7UL)

#define	PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos)

#define	PPI_CHG_CH7_Excluded (0UL)

#define	PPI_CHG_CH7_Included (1UL)

#define	PPI_CHG_CH6_Pos (6UL)

#define	PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos)

#define	PPI_CHG_CH6_Excluded (0UL)

#define	PPI_CHG_CH6_Included (1UL)

#define	PPI_CHG_CH5_Pos (5UL)

#define	PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos)

#define	PPI_CHG_CH5_Excluded (0UL)

#define	PPI_CHG_CH5_Included (1UL)

#define	PPI_CHG_CH4_Pos (4UL)

#define	PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos)

#define	PPI_CHG_CH4_Excluded (0UL)

#define	PPI_CHG_CH4_Included (1UL)

#define	PPI_CHG_CH3_Pos (3UL)

#define	PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos)

#define	PPI_CHG_CH3_Excluded (0UL)

#define	PPI_CHG_CH3_Included (1UL)

#define	PPI_CHG_CH2_Pos (2UL)

#define	PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos)

#define	PPI_CHG_CH2_Excluded (0UL)

#define	PPI_CHG_CH2_Included (1UL)

#define	PPI_CHG_CH1_Pos (1UL)

#define	PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos)

#define	PPI_CHG_CH1_Excluded (0UL)

#define	PPI_CHG_CH1_Included (1UL)

#define	PPI_CHG_CH0_Pos (0UL)

#define	PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos)

#define	PPI_CHG_CH0_Excluded (0UL)

#define	PPI_CHG_CH0_Included (1UL)

#define	PU_PATCHADDR_PATCHADDR_Pos (0UL)

#define	PU_PATCHADDR_PATCHADDR_Msk (0x1FFFFFFUL << PU_PATCHADDR_PATCHADDR_Pos)

#define	PU_PATCHEN_PATCH7_Pos (7UL)

#define	PU_PATCHEN_PATCH7_Msk (0x1UL << PU_PATCHEN_PATCH7_Pos)

#define	PU_PATCHEN_PATCH7_Disabled (0UL)

#define	PU_PATCHEN_PATCH7_Enabled (1UL)

#define	PU_PATCHEN_PATCH6_Pos (6UL)

#define	PU_PATCHEN_PATCH6_Msk (0x1UL << PU_PATCHEN_PATCH6_Pos)

#define	PU_PATCHEN_PATCH6_Disabled (0UL)

#define	PU_PATCHEN_PATCH6_Enabled (1UL)

#define	PU_PATCHEN_PATCH5_Pos (5UL)

#define	PU_PATCHEN_PATCH5_Msk (0x1UL << PU_PATCHEN_PATCH5_Pos)

#define	PU_PATCHEN_PATCH5_Disabled (0UL)

#define	PU_PATCHEN_PATCH5_Enabled (1UL)

#define	PU_PATCHEN_PATCH4_Pos (4UL)

#define	PU_PATCHEN_PATCH4_Msk (0x1UL << PU_PATCHEN_PATCH4_Pos)

#define	PU_PATCHEN_PATCH4_Disabled (0UL)

#define	PU_PATCHEN_PATCH4_Enabled (1UL)

#define	PU_PATCHEN_PATCH3_Pos (3UL)

#define	PU_PATCHEN_PATCH3_Msk (0x1UL << PU_PATCHEN_PATCH3_Pos)

#define	PU_PATCHEN_PATCH3_Disabled (0UL)

#define	PU_PATCHEN_PATCH3_Enabled (1UL)

#define	PU_PATCHEN_PATCH2_Pos (2UL)

#define	PU_PATCHEN_PATCH2_Msk (0x1UL << PU_PATCHEN_PATCH2_Pos)

#define	PU_PATCHEN_PATCH2_Disabled (0UL)

#define	PU_PATCHEN_PATCH2_Enabled (1UL)

#define	PU_PATCHEN_PATCH1_Pos (1UL)

#define	PU_PATCHEN_PATCH1_Msk (0x1UL << PU_PATCHEN_PATCH1_Pos)

#define	PU_PATCHEN_PATCH1_Disabled (0UL)

#define	PU_PATCHEN_PATCH1_Enabled (1UL)

#define	PU_PATCHEN_PATCH0_Pos (0UL)

#define	PU_PATCHEN_PATCH0_Msk (0x1UL << PU_PATCHEN_PATCH0_Pos)

#define	PU_PATCHEN_PATCH0_Disabled (0UL)

#define	PU_PATCHEN_PATCH0_Enabled (1UL)

#define	PU_PATCHENSET_PATCH7_Pos (7UL)

#define	PU_PATCHENSET_PATCH7_Msk (0x1UL << PU_PATCHENSET_PATCH7_Pos)

#define	PU_PATCHENSET_PATCH7_Disabled (0UL)

#define	PU_PATCHENSET_PATCH7_Enabled (1UL)

#define	PU_PATCHENSET_PATCH7_Set (1UL)

#define	PU_PATCHENSET_PATCH6_Pos (6UL)

#define	PU_PATCHENSET_PATCH6_Msk (0x1UL << PU_PATCHENSET_PATCH6_Pos)

#define	PU_PATCHENSET_PATCH6_Disabled (0UL)

#define	PU_PATCHENSET_PATCH6_Enabled (1UL)

#define	PU_PATCHENSET_PATCH6_Set (1UL)

#define	PU_PATCHENSET_PATCH5_Pos (5UL)

#define	PU_PATCHENSET_PATCH5_Msk (0x1UL << PU_PATCHENSET_PATCH5_Pos)

#define	PU_PATCHENSET_PATCH5_Disabled (0UL)

#define	PU_PATCHENSET_PATCH5_Enabled (1UL)

#define	PU_PATCHENSET_PATCH5_Set (1UL)

#define	PU_PATCHENSET_PATCH4_Pos (4UL)

#define	PU_PATCHENSET_PATCH4_Msk (0x1UL << PU_PATCHENSET_PATCH4_Pos)

#define	PU_PATCHENSET_PATCH4_Disabled (0UL)

#define	PU_PATCHENSET_PATCH4_Enabled (1UL)

#define	PU_PATCHENSET_PATCH4_Set (1UL)

#define	PU_PATCHENSET_PATCH3_Pos (3UL)

#define	PU_PATCHENSET_PATCH3_Msk (0x1UL << PU_PATCHENSET_PATCH3_Pos)

#define	PU_PATCHENSET_PATCH3_Disabled (0UL)

#define	PU_PATCHENSET_PATCH3_Enabled (1UL)

#define	PU_PATCHENSET_PATCH3_Set (1UL)

#define	PU_PATCHENSET_PATCH2_Pos (2UL)

#define	PU_PATCHENSET_PATCH2_Msk (0x1UL << PU_PATCHENSET_PATCH2_Pos)

#define	PU_PATCHENSET_PATCH2_Disabled (0UL)

#define	PU_PATCHENSET_PATCH2_Enabled (1UL)

#define	PU_PATCHENSET_PATCH2_Set (1UL)

#define	PU_PATCHENSET_PATCH1_Pos (1UL)

#define	PU_PATCHENSET_PATCH1_Msk (0x1UL << PU_PATCHENSET_PATCH1_Pos)

#define	PU_PATCHENSET_PATCH1_Disabled (0UL)

#define	PU_PATCHENSET_PATCH1_Enabled (1UL)

#define	PU_PATCHENSET_PATCH1_Set (1UL)

#define	PU_PATCHENSET_PATCH0_Pos (0UL)

#define	PU_PATCHENSET_PATCH0_Msk (0x1UL << PU_PATCHENSET_PATCH0_Pos)

#define	PU_PATCHENSET_PATCH0_Disabled (0UL)

#define	PU_PATCHENSET_PATCH0_Enabled (1UL)

#define	PU_PATCHENSET_PATCH0_Set (1UL)

#define	PU_PATCHENCLR_PATCH7_Pos (7UL)

#define	PU_PATCHENCLR_PATCH7_Msk (0x1UL << PU_PATCHENCLR_PATCH7_Pos)

#define	PU_PATCHENCLR_PATCH7_Disabled (0UL)

#define	PU_PATCHENCLR_PATCH7_Enabled (1UL)

#define	PU_PATCHENCLR_PATCH7_Clear (1UL)

#define	PU_PATCHENCLR_PATCH6_Pos (6UL)

#define	PU_PATCHENCLR_PATCH6_Msk (0x1UL << PU_PATCHENCLR_PATCH6_Pos)

#define	PU_PATCHENCLR_PATCH6_Disabled (0UL)

#define	PU_PATCHENCLR_PATCH6_Enabled (1UL)

#define	PU_PATCHENCLR_PATCH6_Clear (1UL)

#define	PU_PATCHENCLR_PATCH5_Pos (5UL)

#define	PU_PATCHENCLR_PATCH5_Msk (0x1UL << PU_PATCHENCLR_PATCH5_Pos)

#define	PU_PATCHENCLR_PATCH5_Disabled (0UL)

#define	PU_PATCHENCLR_PATCH5_Enabled (1UL)

#define	PU_PATCHENCLR_PATCH5_Clear (1UL)

#define	PU_PATCHENCLR_PATCH4_Pos (4UL)

#define	PU_PATCHENCLR_PATCH4_Msk (0x1UL << PU_PATCHENCLR_PATCH4_Pos)

#define	PU_PATCHENCLR_PATCH4_Disabled (0UL)

#define	PU_PATCHENCLR_PATCH4_Enabled (1UL)

#define	PU_PATCHENCLR_PATCH4_Clear (1UL)

#define	PU_PATCHENCLR_PATCH3_Pos (3UL)

#define	PU_PATCHENCLR_PATCH3_Msk (0x1UL << PU_PATCHENCLR_PATCH3_Pos)

#define	PU_PATCHENCLR_PATCH3_Disabled (0UL)

#define	PU_PATCHENCLR_PATCH3_Enabled (1UL)

#define	PU_PATCHENCLR_PATCH3_Clear (1UL)

#define	PU_PATCHENCLR_PATCH2_Pos (2UL)

#define	PU_PATCHENCLR_PATCH2_Msk (0x1UL << PU_PATCHENCLR_PATCH2_Pos)

#define	PU_PATCHENCLR_PATCH2_Disabled (0UL)

#define	PU_PATCHENCLR_PATCH2_Enabled (1UL)

#define	PU_PATCHENCLR_PATCH2_Clear (1UL)

#define	PU_PATCHENCLR_PATCH1_Pos (1UL)

#define	PU_PATCHENCLR_PATCH1_Msk (0x1UL << PU_PATCHENCLR_PATCH1_Pos)

#define	PU_PATCHENCLR_PATCH1_Disabled (0UL)

#define	PU_PATCHENCLR_PATCH1_Enabled (1UL)

#define	PU_PATCHENCLR_PATCH1_Clear (1UL)

#define	PU_PATCHENCLR_PATCH0_Pos (0UL)

#define	PU_PATCHENCLR_PATCH0_Msk (0x1UL << PU_PATCHENCLR_PATCH0_Pos)

#define	PU_PATCHENCLR_PATCH0_Disabled (0UL)

#define	PU_PATCHENCLR_PATCH0_Enabled (1UL)

#define	PU_PATCHENCLR_PATCH0_Clear (1UL)

#define	QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL)

#define	QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos)

#define	QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL)

#define	QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL)

#define	QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL)

#define	QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos)

#define	QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL)

#define	QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL)

#define	QDEC_INTENSET_ACCOF_Pos (2UL)

#define	QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos)

#define	QDEC_INTENSET_ACCOF_Disabled (0UL)

#define	QDEC_INTENSET_ACCOF_Enabled (1UL)

#define	QDEC_INTENSET_ACCOF_Set (1UL)

#define	QDEC_INTENSET_REPORTRDY_Pos (1UL)

#define	QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos)

#define	QDEC_INTENSET_REPORTRDY_Disabled (0UL)

#define	QDEC_INTENSET_REPORTRDY_Enabled (1UL)

#define	QDEC_INTENSET_REPORTRDY_Set (1UL)

#define	QDEC_INTENSET_SAMPLERDY_Pos (0UL)

#define	QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos)

#define	QDEC_INTENSET_SAMPLERDY_Disabled (0UL)

#define	QDEC_INTENSET_SAMPLERDY_Enabled (1UL)

#define	QDEC_INTENSET_SAMPLERDY_Set (1UL)

#define	QDEC_INTENCLR_ACCOF_Pos (2UL)

#define	QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos)

#define	QDEC_INTENCLR_ACCOF_Disabled (0UL)

#define	QDEC_INTENCLR_ACCOF_Enabled (1UL)

#define	QDEC_INTENCLR_ACCOF_Clear (1UL)

#define	QDEC_INTENCLR_REPORTRDY_Pos (1UL)

#define	QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos)

#define	QDEC_INTENCLR_REPORTRDY_Disabled (0UL)

#define	QDEC_INTENCLR_REPORTRDY_Enabled (1UL)

#define	QDEC_INTENCLR_REPORTRDY_Clear (1UL)

#define	QDEC_INTENCLR_SAMPLERDY_Pos (0UL)

#define	QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos)

#define	QDEC_INTENCLR_SAMPLERDY_Disabled (0UL)

#define	QDEC_INTENCLR_SAMPLERDY_Enabled (1UL)

#define	QDEC_INTENCLR_SAMPLERDY_Clear (1UL)

#define	QDEC_ENABLE_ENABLE_Pos (0UL)

#define	QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos)

#define	QDEC_ENABLE_ENABLE_Disabled (0UL)

#define	QDEC_ENABLE_ENABLE_Enabled (1UL)

#define	QDEC_LEDPOL_LEDPOL_Pos (0UL)

#define	QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos)

#define	QDEC_LEDPOL_LEDPOL_ActiveLow (0UL)

#define	QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL)

#define	QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL)

#define	QDEC_SAMPLEPER_SAMPLEPER_Msk (0x7UL << QDEC_SAMPLEPER_SAMPLEPER_Pos)

#define	QDEC_SAMPLEPER_SAMPLEPER_128us (0x00UL)

#define	QDEC_SAMPLEPER_SAMPLEPER_256us (0x01UL)

#define	QDEC_SAMPLEPER_SAMPLEPER_512us (0x02UL)

#define	QDEC_SAMPLEPER_SAMPLEPER_1024us (0x03UL)

#define	QDEC_SAMPLEPER_SAMPLEPER_2048us (0x04UL)

#define	QDEC_SAMPLEPER_SAMPLEPER_4096us (0x05UL)

#define	QDEC_SAMPLEPER_SAMPLEPER_8192us (0x06UL)

#define	QDEC_SAMPLEPER_SAMPLEPER_16384us (0x07UL)

#define	QDEC_SAMPLE_SAMPLE_Pos (0UL)

#define	QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos)

#define	QDEC_REPORTPER_REPORTPER_Pos (0UL)

#define	QDEC_REPORTPER_REPORTPER_Msk (0x7UL << QDEC_REPORTPER_REPORTPER_Pos)

#define	QDEC_REPORTPER_REPORTPER_10Smpl (0x00UL)

#define	QDEC_REPORTPER_REPORTPER_40Smpl (0x01UL)

#define	QDEC_REPORTPER_REPORTPER_80Smpl (0x02UL)

#define	QDEC_REPORTPER_REPORTPER_120Smpl (0x03UL)

#define	QDEC_REPORTPER_REPORTPER_160Smpl (0x04UL)

#define	QDEC_REPORTPER_REPORTPER_200Smpl (0x05UL)

#define	QDEC_REPORTPER_REPORTPER_240Smpl (0x06UL)

#define	QDEC_REPORTPER_REPORTPER_280Smpl (0x07UL)

#define	QDEC_DBFEN_DBFEN_Pos (0UL)

#define	QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos)

#define	QDEC_DBFEN_DBFEN_Disabled (0UL)

#define	QDEC_DBFEN_DBFEN_Enabled (1UL)

#define	QDEC_LEDPRE_LEDPRE_Pos (0UL)

#define	QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos)

#define	QDEC_ACCDBL_ACCDBL_Pos (0UL)

#define	QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos)

#define	QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL)

#define	QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos)

#define	QDEC_POWER_POWER_Pos (0UL)

#define	QDEC_POWER_POWER_Msk (0x1UL << QDEC_POWER_POWER_Pos)

#define	QDEC_POWER_POWER_Disabled (0UL)

#define	QDEC_POWER_POWER_Enabled (1UL)

#define	RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL)

#define	RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos)

#define	RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL)

#define	RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL)

#define	RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL)

#define	RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos)

#define	RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL)

#define	RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL)

#define	RADIO_SHORTS_END_START_Pos (5UL)

#define	RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos)

#define	RADIO_SHORTS_END_START_Disabled (0UL)

#define	RADIO_SHORTS_END_START_Enabled (1UL)

#define	RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL)

#define	RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos)

#define	RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL)

#define	RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL)

#define	RADIO_SHORTS_DISABLED_RXEN_Pos (3UL)

#define	RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos)

#define	RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL)

#define	RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL)

#define	RADIO_SHORTS_DISABLED_TXEN_Pos (2UL)

#define	RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos)

#define	RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL)

#define	RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL)

#define	RADIO_SHORTS_END_DISABLE_Pos (1UL)

#define	RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos)

#define	RADIO_SHORTS_END_DISABLE_Disabled (0UL)

#define	RADIO_SHORTS_END_DISABLE_Enabled (1UL)

#define	RADIO_SHORTS_READY_START_Pos (0UL)

#define	RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos)

#define	RADIO_SHORTS_READY_START_Disabled (0UL)

#define	RADIO_SHORTS_READY_START_Enabled (1UL)

#define	RADIO_INTENSET_BCMATCH_Pos (10UL)

#define	RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos)

#define	RADIO_INTENSET_BCMATCH_Disabled (0UL)

#define	RADIO_INTENSET_BCMATCH_Enabled (1UL)

#define	RADIO_INTENSET_BCMATCH_Set (1UL)

#define	RADIO_INTENSET_RSSIEND_Pos (7UL)

#define	RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos)

#define	RADIO_INTENSET_RSSIEND_Disabled (0UL)

#define	RADIO_INTENSET_RSSIEND_Enabled (1UL)

#define	RADIO_INTENSET_RSSIEND_Set (1UL)

#define	RADIO_INTENSET_DEVMISS_Pos (6UL)

#define	RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos)

#define	RADIO_INTENSET_DEVMISS_Disabled (0UL)

#define	RADIO_INTENSET_DEVMISS_Enabled (1UL)

#define	RADIO_INTENSET_DEVMISS_Set (1UL)

#define	RADIO_INTENSET_DEVMATCH_Pos (5UL)

#define	RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos)

#define	RADIO_INTENSET_DEVMATCH_Disabled (0UL)

#define	RADIO_INTENSET_DEVMATCH_Enabled (1UL)

#define	RADIO_INTENSET_DEVMATCH_Set (1UL)

#define	RADIO_INTENSET_DISABLED_Pos (4UL)

#define	RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos)

#define	RADIO_INTENSET_DISABLED_Disabled (0UL)

#define	RADIO_INTENSET_DISABLED_Enabled (1UL)

#define	RADIO_INTENSET_DISABLED_Set (1UL)

#define	RADIO_INTENSET_END_Pos (3UL)

#define	RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos)

#define	RADIO_INTENSET_END_Disabled (0UL)

#define	RADIO_INTENSET_END_Enabled (1UL)

#define	RADIO_INTENSET_END_Set (1UL)

#define	RADIO_INTENSET_PAYLOAD_Pos (2UL)

#define	RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos)

#define	RADIO_INTENSET_PAYLOAD_Disabled (0UL)

#define	RADIO_INTENSET_PAYLOAD_Enabled (1UL)

#define	RADIO_INTENSET_PAYLOAD_Set (1UL)

#define	RADIO_INTENSET_ADDRESS_Pos (1UL)

#define	RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos)

#define	RADIO_INTENSET_ADDRESS_Disabled (0UL)

#define	RADIO_INTENSET_ADDRESS_Enabled (1UL)

#define	RADIO_INTENSET_ADDRESS_Set (1UL)

#define	RADIO_INTENSET_READY_Pos (0UL)

#define	RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos)

#define	RADIO_INTENSET_READY_Disabled (0UL)

#define	RADIO_INTENSET_READY_Enabled (1UL)

#define	RADIO_INTENSET_READY_Set (1UL)

#define	RADIO_INTENCLR_BCMATCH_Pos (10UL)

#define	RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos)

#define	RADIO_INTENCLR_BCMATCH_Disabled (0UL)

#define	RADIO_INTENCLR_BCMATCH_Enabled (1UL)

#define	RADIO_INTENCLR_BCMATCH_Clear (1UL)

#define	RADIO_INTENCLR_RSSIEND_Pos (7UL)

#define	RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos)

#define	RADIO_INTENCLR_RSSIEND_Disabled (0UL)

#define	RADIO_INTENCLR_RSSIEND_Enabled (1UL)

#define	RADIO_INTENCLR_RSSIEND_Clear (1UL)

#define	RADIO_INTENCLR_DEVMISS_Pos (6UL)

#define	RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos)

#define	RADIO_INTENCLR_DEVMISS_Disabled (0UL)

#define	RADIO_INTENCLR_DEVMISS_Enabled (1UL)

#define	RADIO_INTENCLR_DEVMISS_Clear (1UL)

#define	RADIO_INTENCLR_DEVMATCH_Pos (5UL)

#define	RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos)

#define	RADIO_INTENCLR_DEVMATCH_Disabled (0UL)

#define	RADIO_INTENCLR_DEVMATCH_Enabled (1UL)

#define	RADIO_INTENCLR_DEVMATCH_Clear (1UL)

#define	RADIO_INTENCLR_DISABLED_Pos (4UL)

#define	RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos)

#define	RADIO_INTENCLR_DISABLED_Disabled (0UL)

#define	RADIO_INTENCLR_DISABLED_Enabled (1UL)

#define	RADIO_INTENCLR_DISABLED_Clear (1UL)

#define	RADIO_INTENCLR_END_Pos (3UL)

#define	RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos)

#define	RADIO_INTENCLR_END_Disabled (0UL)

#define	RADIO_INTENCLR_END_Enabled (1UL)

#define	RADIO_INTENCLR_END_Clear (1UL)

#define	RADIO_INTENCLR_PAYLOAD_Pos (2UL)

#define	RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos)

#define	RADIO_INTENCLR_PAYLOAD_Disabled (0UL)

#define	RADIO_INTENCLR_PAYLOAD_Enabled (1UL)

#define	RADIO_INTENCLR_PAYLOAD_Clear (1UL)

#define	RADIO_INTENCLR_ADDRESS_Pos (1UL)

#define	RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos)

#define	RADIO_INTENCLR_ADDRESS_Disabled (0UL)

#define	RADIO_INTENCLR_ADDRESS_Enabled (1UL)

#define	RADIO_INTENCLR_ADDRESS_Clear (1UL)

#define	RADIO_INTENCLR_READY_Pos (0UL)

#define	RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos)

#define	RADIO_INTENCLR_READY_Disabled (0UL)

#define	RADIO_INTENCLR_READY_Enabled (1UL)

#define	RADIO_INTENCLR_READY_Clear (1UL)

#define	RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL)

#define	RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos)

#define	RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL)

#define	RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL)

#define	RADIO_CD_CD_Pos (0UL)

#define	RADIO_CD_CD_Msk (0x1UL << RADIO_CD_CD_Pos)

#define	RADIO_RXMATCH_RXMATCH_Pos (0UL)

#define	RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos)

#define	RADIO_RXCRC_RXCRC_Pos (0UL)

#define	RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos)

#define	RADIO_DAI_DAI_Pos (0UL)

#define	RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos)

#define	RADIO_FREQUENCY_FREQUENCY_Pos (0UL)

#define	RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos)

#define	RADIO_TXPOWER_TXPOWER_Pos (0UL)

#define	RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos)

#define	RADIO_TXPOWER_TXPOWER_0dBm (0x00UL)

#define	RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL)

#define	RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL)

#define	RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL)

#define	RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL)

#define	RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL)

#define	RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL)

#define	RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL)

#define	RADIO_MODE_MODE_Pos (0UL)

#define	RADIO_MODE_MODE_Msk (0x3UL << RADIO_MODE_MODE_Pos)

#define	RADIO_MODE_MODE_Nrf_1Mbit (0x00UL)

#define	RADIO_MODE_MODE_Nrf_2Mbit (0x01UL)

#define	RADIO_MODE_MODE_Nrf_250Kbit (0x02UL)

#define	RADIO_MODE_MODE_Ble_1Mbit (0x03UL)

#define	RADIO_PCNF0_S1LEN_Pos (16UL)

#define	RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos)

#define	RADIO_PCNF0_S0LEN_Pos (8UL)

#define	RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos)

#define	RADIO_PCNF0_LFLEN_Pos (0UL)

#define	RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos)

#define	RADIO_PCNF1_WHITEEN_Pos (25UL)

#define	RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos)

#define	RADIO_PCNF1_WHITEEN_Disabled (0UL)

#define	RADIO_PCNF1_WHITEEN_Enabled (1UL)

#define	RADIO_PCNF1_ENDIAN_Pos (24UL)

#define	RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos)

#define	RADIO_PCNF1_ENDIAN_Little (0UL)

#define	RADIO_PCNF1_ENDIAN_Big (1UL)

#define	RADIO_PCNF1_BALEN_Pos (16UL)

#define	RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos)

#define	RADIO_PCNF1_STATLEN_Pos (8UL)

#define	RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos)

#define	RADIO_PCNF1_MAXLEN_Pos (0UL)

#define	RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos)

#define	RADIO_PREFIX0_AP3_Pos (24UL)

#define	RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos)

#define	RADIO_PREFIX0_AP2_Pos (16UL)

#define	RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos)

#define	RADIO_PREFIX0_AP1_Pos (8UL)

#define	RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos)

#define	RADIO_PREFIX0_AP0_Pos (0UL)

#define	RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos)

#define	RADIO_PREFIX1_AP7_Pos (24UL)

#define	RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos)

#define	RADIO_PREFIX1_AP6_Pos (16UL)

#define	RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos)

#define	RADIO_PREFIX1_AP5_Pos (8UL)

#define	RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos)

#define	RADIO_PREFIX1_AP4_Pos (0UL)

#define	RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos)

#define	RADIO_TXADDRESS_TXADDRESS_Pos (0UL)

#define	RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos)

#define	RADIO_RXADDRESSES_ADDR7_Pos (7UL)

#define	RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos)

#define	RADIO_RXADDRESSES_ADDR7_Disabled (0UL)

#define	RADIO_RXADDRESSES_ADDR7_Enabled (1UL)

#define	RADIO_RXADDRESSES_ADDR6_Pos (6UL)

#define	RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos)

#define	RADIO_RXADDRESSES_ADDR6_Disabled (0UL)

#define	RADIO_RXADDRESSES_ADDR6_Enabled (1UL)

#define	RADIO_RXADDRESSES_ADDR5_Pos (5UL)

#define	RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos)

#define	RADIO_RXADDRESSES_ADDR5_Disabled (0UL)

#define	RADIO_RXADDRESSES_ADDR5_Enabled (1UL)

#define	RADIO_RXADDRESSES_ADDR4_Pos (4UL)

#define	RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos)

#define	RADIO_RXADDRESSES_ADDR4_Disabled (0UL)

#define	RADIO_RXADDRESSES_ADDR4_Enabled (1UL)

#define	RADIO_RXADDRESSES_ADDR3_Pos (3UL)

#define	RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos)

#define	RADIO_RXADDRESSES_ADDR3_Disabled (0UL)

#define	RADIO_RXADDRESSES_ADDR3_Enabled (1UL)

#define	RADIO_RXADDRESSES_ADDR2_Pos (2UL)

#define	RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos)

#define	RADIO_RXADDRESSES_ADDR2_Disabled (0UL)

#define	RADIO_RXADDRESSES_ADDR2_Enabled (1UL)

#define	RADIO_RXADDRESSES_ADDR1_Pos (1UL)

#define	RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos)

#define	RADIO_RXADDRESSES_ADDR1_Disabled (0UL)

#define	RADIO_RXADDRESSES_ADDR1_Enabled (1UL)

#define	RADIO_RXADDRESSES_ADDR0_Pos (0UL)

#define	RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos)

#define	RADIO_RXADDRESSES_ADDR0_Disabled (0UL)

#define	RADIO_RXADDRESSES_ADDR0_Enabled (1UL)

#define	RADIO_CRCCNF_SKIPADDR_Pos (8UL)

#define	RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos)

#define	RADIO_CRCCNF_SKIPADDR_Include (0UL)

#define	RADIO_CRCCNF_SKIPADDR_Skip (1UL)

#define	RADIO_CRCCNF_LEN_Pos (0UL)

#define	RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos)

#define	RADIO_CRCCNF_LEN_Disabled (0UL)

#define	RADIO_CRCCNF_LEN_One (1UL)

#define	RADIO_CRCCNF_LEN_Two (2UL)

#define	RADIO_CRCCNF_LEN_Three (3UL)

#define	RADIO_CRCPOLY_CRCPOLY_Pos (0UL)

#define	RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos)

#define	RADIO_CRCINIT_CRCINIT_Pos (0UL)

#define	RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos)

#define	RADIO_TEST_PLLLOCK_Pos (1UL)

#define	RADIO_TEST_PLLLOCK_Msk (0x1UL << RADIO_TEST_PLLLOCK_Pos)

#define	RADIO_TEST_PLLLOCK_Disabled (0UL)

#define	RADIO_TEST_PLLLOCK_Enabled (1UL)

#define	RADIO_TEST_CONSTCARRIER_Pos (0UL)

#define	RADIO_TEST_CONSTCARRIER_Msk (0x1UL << RADIO_TEST_CONSTCARRIER_Pos)

#define	RADIO_TEST_CONSTCARRIER_Disabled (0UL)

#define	RADIO_TEST_CONSTCARRIER_Enabled (1UL)

#define	RADIO_TIFS_TIFS_Pos (0UL)

#define	RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos)

#define	RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL)

#define	RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos)

#define	RADIO_STATE_STATE_Pos (0UL)

#define	RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos)

#define	RADIO_STATE_STATE_Disabled (0x00UL)

#define	RADIO_STATE_STATE_RxRu (0x01UL)

#define	RADIO_STATE_STATE_RxIdle (0x02UL)

#define	RADIO_STATE_STATE_Rx (0x03UL)

#define	RADIO_STATE_STATE_RxDisable (0x04UL)

#define	RADIO_STATE_STATE_TxRu (0x09UL)

#define	RADIO_STATE_STATE_TxIdle (0x0AUL)

#define	RADIO_STATE_STATE_Tx (0x0BUL)

#define	RADIO_STATE_STATE_TxDisable (0x0CUL)

#define	RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL)

#define	RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos)

#define	RADIO_DAP_DAP_Pos (0UL)

#define	RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos)

#define	RADIO_DACNF_TXADD7_Pos (15UL)

#define	RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos)

#define	RADIO_DACNF_TXADD6_Pos (14UL)

#define	RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos)

#define	RADIO_DACNF_TXADD5_Pos (13UL)

#define	RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos)

#define	RADIO_DACNF_TXADD4_Pos (12UL)

#define	RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos)

#define	RADIO_DACNF_TXADD3_Pos (11UL)

#define	RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos)

#define	RADIO_DACNF_TXADD2_Pos (10UL)

#define	RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos)

#define	RADIO_DACNF_TXADD1_Pos (9UL)

#define	RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos)

#define	RADIO_DACNF_TXADD0_Pos (8UL)

#define	RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos)

#define	RADIO_DACNF_ENA7_Pos (7UL)

#define	RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos)

#define	RADIO_DACNF_ENA7_Disabled (0UL)

#define	RADIO_DACNF_ENA7_Enabled (1UL)

#define	RADIO_DACNF_ENA6_Pos (6UL)

#define	RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos)

#define	RADIO_DACNF_ENA6_Disabled (0UL)

#define	RADIO_DACNF_ENA6_Enabled (1UL)

#define	RADIO_DACNF_ENA5_Pos (5UL)

#define	RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos)

#define	RADIO_DACNF_ENA5_Disabled (0UL)

#define	RADIO_DACNF_ENA5_Enabled (1UL)

#define	RADIO_DACNF_ENA4_Pos (4UL)

#define	RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos)

#define	RADIO_DACNF_ENA4_Disabled (0UL)

#define	RADIO_DACNF_ENA4_Enabled (1UL)

#define	RADIO_DACNF_ENA3_Pos (3UL)

#define	RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos)

#define	RADIO_DACNF_ENA3_Disabled (0UL)

#define	RADIO_DACNF_ENA3_Enabled (1UL)

#define	RADIO_DACNF_ENA2_Pos (2UL)

#define	RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos)

#define	RADIO_DACNF_ENA2_Disabled (0UL)

#define	RADIO_DACNF_ENA2_Enabled (1UL)

#define	RADIO_DACNF_ENA1_Pos (1UL)

#define	RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos)

#define	RADIO_DACNF_ENA1_Disabled (0UL)

#define	RADIO_DACNF_ENA1_Enabled (1UL)

#define	RADIO_DACNF_ENA0_Pos (0UL)

#define	RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos)

#define	RADIO_DACNF_ENA0_Disabled (0UL)

#define	RADIO_DACNF_ENA0_Enabled (1UL)

#define	RADIO_OVERRIDE0_OVERRIDE0_Pos (0UL)

#define	RADIO_OVERRIDE0_OVERRIDE0_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE0_OVERRIDE0_Pos)

#define	RADIO_OVERRIDE1_OVERRIDE1_Pos (0UL)

#define	RADIO_OVERRIDE1_OVERRIDE1_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE1_OVERRIDE1_Pos)

#define	RADIO_OVERRIDE2_OVERRIDE2_Pos (0UL)

#define	RADIO_OVERRIDE2_OVERRIDE2_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE2_OVERRIDE2_Pos)

#define	RADIO_OVERRIDE3_OVERRIDE3_Pos (0UL)

#define	RADIO_OVERRIDE3_OVERRIDE3_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE3_OVERRIDE3_Pos)

#define	RADIO_OVERRIDE4_ENABLE_Pos (31UL)

#define	RADIO_OVERRIDE4_ENABLE_Msk (0x1UL << RADIO_OVERRIDE4_ENABLE_Pos)

#define	RADIO_OVERRIDE4_ENABLE_Disabled (0UL)

#define	RADIO_OVERRIDE4_ENABLE_Enabled (1UL)

#define	RADIO_OVERRIDE4_OVERRIDE4_Pos (0UL)

#define	RADIO_OVERRIDE4_OVERRIDE4_Msk (0xFFFFFFFUL << RADIO_OVERRIDE4_OVERRIDE4_Pos)

#define	RADIO_POWER_POWER_Pos (0UL)

#define	RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos)

#define	RADIO_POWER_POWER_Disabled (0UL)

#define	RADIO_POWER_POWER_Enabled (1UL)

#define	RNG_SHORTS_VALRDY_STOP_Pos (0UL)

#define	RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos)

#define	RNG_SHORTS_VALRDY_STOP_Disabled (0UL)

#define	RNG_SHORTS_VALRDY_STOP_Enabled (1UL)

#define	RNG_INTENSET_VALRDY_Pos (0UL)

#define	RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos)

#define	RNG_INTENSET_VALRDY_Disabled (0UL)

#define	RNG_INTENSET_VALRDY_Enabled (1UL)

#define	RNG_INTENSET_VALRDY_Set (1UL)

#define	RNG_INTENCLR_VALRDY_Pos (0UL)

#define	RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos)

#define	RNG_INTENCLR_VALRDY_Disabled (0UL)

#define	RNG_INTENCLR_VALRDY_Enabled (1UL)

#define	RNG_INTENCLR_VALRDY_Clear (1UL)

#define	RNG_CONFIG_DERCEN_Pos (0UL)

#define	RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos)

#define	RNG_CONFIG_DERCEN_Disabled (0UL)

#define	RNG_CONFIG_DERCEN_Enabled (1UL)

#define	RNG_VALUE_VALUE_Pos (0UL)

#define	RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos)

#define	RNG_POWER_POWER_Pos (0UL)

#define	RNG_POWER_POWER_Msk (0x1UL << RNG_POWER_POWER_Pos)

#define	RNG_POWER_POWER_Disabled (0UL)

#define	RNG_POWER_POWER_Enabled (1UL)

#define	RTC_INTENSET_COMPARE3_Pos (19UL)

#define	RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos)

#define	RTC_INTENSET_COMPARE3_Disabled (0UL)

#define	RTC_INTENSET_COMPARE3_Enabled (1UL)

#define	RTC_INTENSET_COMPARE3_Set (1UL)

#define	RTC_INTENSET_COMPARE2_Pos (18UL)

#define	RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos)

#define	RTC_INTENSET_COMPARE2_Disabled (0UL)

#define	RTC_INTENSET_COMPARE2_Enabled (1UL)

#define	RTC_INTENSET_COMPARE2_Set (1UL)

#define	RTC_INTENSET_COMPARE1_Pos (17UL)

#define	RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos)

#define	RTC_INTENSET_COMPARE1_Disabled (0UL)

#define	RTC_INTENSET_COMPARE1_Enabled (1UL)

#define	RTC_INTENSET_COMPARE1_Set (1UL)

#define	RTC_INTENSET_COMPARE0_Pos (16UL)

#define	RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos)

#define	RTC_INTENSET_COMPARE0_Disabled (0UL)

#define	RTC_INTENSET_COMPARE0_Enabled (1UL)

#define	RTC_INTENSET_COMPARE0_Set (1UL)

#define	RTC_INTENSET_OVRFLW_Pos (1UL)

#define	RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos)

#define	RTC_INTENSET_OVRFLW_Disabled (0UL)

#define	RTC_INTENSET_OVRFLW_Enabled (1UL)

#define	RTC_INTENSET_OVRFLW_Set (1UL)

#define	RTC_INTENSET_TICK_Pos (0UL)

#define	RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos)

#define	RTC_INTENSET_TICK_Disabled (0UL)

#define	RTC_INTENSET_TICK_Enabled (1UL)

#define	RTC_INTENSET_TICK_Set (1UL)

#define	RTC_INTENCLR_COMPARE3_Pos (19UL)

#define	RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos)

#define	RTC_INTENCLR_COMPARE3_Disabled (0UL)

#define	RTC_INTENCLR_COMPARE3_Enabled (1UL)

#define	RTC_INTENCLR_COMPARE3_Clear (1UL)

#define	RTC_INTENCLR_COMPARE2_Pos (18UL)

#define	RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos)

#define	RTC_INTENCLR_COMPARE2_Disabled (0UL)

#define	RTC_INTENCLR_COMPARE2_Enabled (1UL)

#define	RTC_INTENCLR_COMPARE2_Clear (1UL)

#define	RTC_INTENCLR_COMPARE1_Pos (17UL)

#define	RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos)

#define	RTC_INTENCLR_COMPARE1_Disabled (0UL)

#define	RTC_INTENCLR_COMPARE1_Enabled (1UL)

#define	RTC_INTENCLR_COMPARE1_Clear (1UL)

#define	RTC_INTENCLR_COMPARE0_Pos (16UL)

#define	RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos)

#define	RTC_INTENCLR_COMPARE0_Disabled (0UL)

#define	RTC_INTENCLR_COMPARE0_Enabled (1UL)

#define	RTC_INTENCLR_COMPARE0_Clear (1UL)

#define	RTC_INTENCLR_OVRFLW_Pos (1UL)

#define	RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos)

#define	RTC_INTENCLR_OVRFLW_Disabled (0UL)

#define	RTC_INTENCLR_OVRFLW_Enabled (1UL)

#define	RTC_INTENCLR_OVRFLW_Clear (1UL)

#define	RTC_INTENCLR_TICK_Pos (0UL)

#define	RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos)

#define	RTC_INTENCLR_TICK_Disabled (0UL)

#define	RTC_INTENCLR_TICK_Enabled (1UL)

#define	RTC_INTENCLR_TICK_Clear (1UL)

#define	RTC_EVTEN_COMPARE3_Pos (19UL)

#define	RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos)

#define	RTC_EVTEN_COMPARE3_Disabled (0UL)

#define	RTC_EVTEN_COMPARE3_Enabled (1UL)

#define	RTC_EVTEN_COMPARE2_Pos (18UL)

#define	RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos)

#define	RTC_EVTEN_COMPARE2_Disabled (0UL)

#define	RTC_EVTEN_COMPARE2_Enabled (1UL)

#define	RTC_EVTEN_COMPARE1_Pos (17UL)

#define	RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos)

#define	RTC_EVTEN_COMPARE1_Disabled (0UL)

#define	RTC_EVTEN_COMPARE1_Enabled (1UL)

#define	RTC_EVTEN_COMPARE0_Pos (16UL)

#define	RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos)

#define	RTC_EVTEN_COMPARE0_Disabled (0UL)

#define	RTC_EVTEN_COMPARE0_Enabled (1UL)

#define	RTC_EVTEN_OVRFLW_Pos (1UL)

#define	RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos)

#define	RTC_EVTEN_OVRFLW_Disabled (0UL)

#define	RTC_EVTEN_OVRFLW_Enabled (1UL)

#define	RTC_EVTEN_TICK_Pos (0UL)

#define	RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos)

#define	RTC_EVTEN_TICK_Disabled (0UL)

#define	RTC_EVTEN_TICK_Enabled (1UL)

#define	RTC_EVTENSET_COMPARE3_Pos (19UL)

#define	RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos)

#define	RTC_EVTENSET_COMPARE3_Disabled (0UL)

#define	RTC_EVTENSET_COMPARE3_Enabled (1UL)

#define	RTC_EVTENSET_COMPARE3_Set (1UL)

#define	RTC_EVTENSET_COMPARE2_Pos (18UL)

#define	RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos)

#define	RTC_EVTENSET_COMPARE2_Disabled (0UL)

#define	RTC_EVTENSET_COMPARE2_Enabled (1UL)

#define	RTC_EVTENSET_COMPARE2_Set (1UL)

#define	RTC_EVTENSET_COMPARE1_Pos (17UL)

#define	RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos)

#define	RTC_EVTENSET_COMPARE1_Disabled (0UL)

#define	RTC_EVTENSET_COMPARE1_Enabled (1UL)

#define	RTC_EVTENSET_COMPARE1_Set (1UL)

#define	RTC_EVTENSET_COMPARE0_Pos (16UL)

#define	RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos)

#define	RTC_EVTENSET_COMPARE0_Disabled (0UL)

#define	RTC_EVTENSET_COMPARE0_Enabled (1UL)

#define	RTC_EVTENSET_COMPARE0_Set (1UL)

#define	RTC_EVTENSET_OVRFLW_Pos (1UL)

#define	RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos)

#define	RTC_EVTENSET_OVRFLW_Disabled (0UL)

#define	RTC_EVTENSET_OVRFLW_Enabled (1UL)

#define	RTC_EVTENSET_OVRFLW_Set (1UL)

#define	RTC_EVTENSET_TICK_Pos (0UL)

#define	RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos)

#define	RTC_EVTENSET_TICK_Disabled (0UL)

#define	RTC_EVTENSET_TICK_Enabled (1UL)

#define	RTC_EVTENSET_TICK_Set (1UL)

#define	RTC_EVTENCLR_COMPARE3_Pos (19UL)

#define	RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos)

#define	RTC_EVTENCLR_COMPARE3_Disabled (0UL)

#define	RTC_EVTENCLR_COMPARE3_Enabled (1UL)

#define	RTC_EVTENCLR_COMPARE3_Clear (1UL)

#define	RTC_EVTENCLR_COMPARE2_Pos (18UL)

#define	RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos)

#define	RTC_EVTENCLR_COMPARE2_Disabled (0UL)

#define	RTC_EVTENCLR_COMPARE2_Enabled (1UL)

#define	RTC_EVTENCLR_COMPARE2_Clear (1UL)

#define	RTC_EVTENCLR_COMPARE1_Pos (17UL)

#define	RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos)

#define	RTC_EVTENCLR_COMPARE1_Disabled (0UL)

#define	RTC_EVTENCLR_COMPARE1_Enabled (1UL)

#define	RTC_EVTENCLR_COMPARE1_Clear (1UL)

#define	RTC_EVTENCLR_COMPARE0_Pos (16UL)

#define	RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos)

#define	RTC_EVTENCLR_COMPARE0_Disabled (0UL)

#define	RTC_EVTENCLR_COMPARE0_Enabled (1UL)

#define	RTC_EVTENCLR_COMPARE0_Clear (1UL)

#define	RTC_EVTENCLR_OVRFLW_Pos (1UL)

#define	RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos)

#define	RTC_EVTENCLR_OVRFLW_Disabled (0UL)

#define	RTC_EVTENCLR_OVRFLW_Enabled (1UL)

#define	RTC_EVTENCLR_OVRFLW_Clear (1UL)

#define	RTC_EVTENCLR_TICK_Pos (0UL)

#define	RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos)

#define	RTC_EVTENCLR_TICK_Disabled (0UL)

#define	RTC_EVTENCLR_TICK_Enabled (1UL)

#define	RTC_EVTENCLR_TICK_Clear (1UL)

#define	RTC_COUNTER_COUNTER_Pos (0UL)

#define	RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos)

#define	RTC_PRESCALER_PRESCALER_Pos (0UL)

#define	RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos)

#define	RTC_CC_COMPARE_Pos (0UL)

#define	RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos)

#define	RTC_POWER_POWER_Pos (0UL)

#define	RTC_POWER_POWER_Msk (0x1UL << RTC_POWER_POWER_Pos)

#define	RTC_POWER_POWER_Disabled (0UL)

#define	RTC_POWER_POWER_Enabled (1UL)

#define	SPI_INTENSET_READY_Pos (2UL)

#define	SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos)

#define	SPI_INTENSET_READY_Disabled (0UL)

#define	SPI_INTENSET_READY_Enabled (1UL)

#define	SPI_INTENSET_READY_Set (1UL)

#define	SPI_INTENCLR_READY_Pos (2UL)

#define	SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos)

#define	SPI_INTENCLR_READY_Disabled (0UL)

#define	SPI_INTENCLR_READY_Enabled (1UL)

#define	SPI_INTENCLR_READY_Clear (1UL)

#define	SPI_ENABLE_ENABLE_Pos (0UL)

#define	SPI_ENABLE_ENABLE_Msk (0x7UL << SPI_ENABLE_ENABLE_Pos)

#define	SPI_ENABLE_ENABLE_Disabled (0x00UL)

#define	SPI_ENABLE_ENABLE_Enabled (0x01UL)

#define	SPI_RXD_RXD_Pos (0UL)

#define	SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos)

#define	SPI_TXD_TXD_Pos (0UL)

#define	SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos)

#define	SPI_FREQUENCY_FREQUENCY_Pos (0UL)

#define	SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos)

#define	SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL)

#define	SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL)

#define	SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL)

#define	SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL)

#define	SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL)

#define	SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL)

#define	SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL)

#define	SPI_CONFIG_CPOL_Pos (2UL)

#define	SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos)

#define	SPI_CONFIG_CPOL_ActiveHigh (0UL)

#define	SPI_CONFIG_CPOL_ActiveLow (1UL)

#define	SPI_CONFIG_CPHA_Pos (1UL)

#define	SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos)

#define	SPI_CONFIG_CPHA_Leading (0UL)

#define	SPI_CONFIG_CPHA_Trailing (1UL)

#define	SPI_CONFIG_ORDER_Pos (0UL)

#define	SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos)

#define	SPI_CONFIG_ORDER_MsbFirst (0UL)

#define	SPI_CONFIG_ORDER_LsbFirst (1UL)

#define	SPI_POWER_POWER_Pos (0UL)

#define	SPI_POWER_POWER_Msk (0x1UL << SPI_POWER_POWER_Pos)

#define	SPI_POWER_POWER_Disabled (0UL)

#define	SPI_POWER_POWER_Enabled (1UL)

#define	SPIM_SHORTS_END_START_Pos (17UL)

#define	SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos)

#define	SPIM_SHORTS_END_START_Disabled (0UL)

#define	SPIM_SHORTS_END_START_Enabled (1UL)

#define	SPIM_INTENSET_STARTED_Pos (19UL)

#define	SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos)

#define	SPIM_INTENSET_STARTED_Disabled (0UL)

#define	SPIM_INTENSET_STARTED_Enabled (1UL)

#define	SPIM_INTENSET_STARTED_Set (1UL)

#define	SPIM_INTENSET_ENDTX_Pos (8UL)

#define	SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos)

#define	SPIM_INTENSET_ENDTX_Disabled (0UL)

#define	SPIM_INTENSET_ENDTX_Enabled (1UL)

#define	SPIM_INTENSET_ENDTX_Set (1UL)

#define	SPIM_INTENSET_END_Pos (6UL)

#define	SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos)

#define	SPIM_INTENSET_END_Disabled (0UL)

#define	SPIM_INTENSET_END_Enabled (1UL)

#define	SPIM_INTENSET_END_Set (1UL)

#define	SPIM_INTENSET_ENDRX_Pos (4UL)

#define	SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos)

#define	SPIM_INTENSET_ENDRX_Disabled (0UL)

#define	SPIM_INTENSET_ENDRX_Enabled (1UL)

#define	SPIM_INTENSET_ENDRX_Set (1UL)

#define	SPIM_INTENSET_STOPPED_Pos (1UL)

#define	SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos)

#define	SPIM_INTENSET_STOPPED_Disabled (0UL)

#define	SPIM_INTENSET_STOPPED_Enabled (1UL)

#define	SPIM_INTENSET_STOPPED_Set (1UL)

#define	SPIM_INTENCLR_STARTED_Pos (19UL)

#define	SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos)

#define	SPIM_INTENCLR_STARTED_Disabled (0UL)

#define	SPIM_INTENCLR_STARTED_Enabled (1UL)

#define	SPIM_INTENCLR_STARTED_Clear (1UL)

#define	SPIM_INTENCLR_ENDTX_Pos (8UL)

#define	SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos)

#define	SPIM_INTENCLR_ENDTX_Disabled (0UL)

#define	SPIM_INTENCLR_ENDTX_Enabled (1UL)

#define	SPIM_INTENCLR_ENDTX_Clear (1UL)

#define	SPIM_INTENCLR_END_Pos (6UL)

#define	SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos)

#define	SPIM_INTENCLR_END_Disabled (0UL)

#define	SPIM_INTENCLR_END_Enabled (1UL)

#define	SPIM_INTENCLR_END_Clear (1UL)

#define	SPIM_INTENCLR_ENDRX_Pos (4UL)

#define	SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos)

#define	SPIM_INTENCLR_ENDRX_Disabled (0UL)

#define	SPIM_INTENCLR_ENDRX_Enabled (1UL)

#define	SPIM_INTENCLR_ENDRX_Clear (1UL)

#define	SPIM_INTENCLR_STOPPED_Pos (1UL)

#define	SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos)

#define	SPIM_INTENCLR_STOPPED_Disabled (0UL)

#define	SPIM_INTENCLR_STOPPED_Enabled (1UL)

#define	SPIM_INTENCLR_STOPPED_Clear (1UL)

#define	SPIM_ENABLE_ENABLE_Pos (0UL)

#define	SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos)

#define	SPIM_ENABLE_ENABLE_Disabled (0x00UL)

#define	SPIM_ENABLE_ENABLE_Enabled (0x07UL)

#define	SPIM_FREQUENCY_FREQUENCY_Pos (0UL)

#define	SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos)

#define	SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL)

#define	SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL)

#define	SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL)

#define	SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL)

#define	SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL)

#define	SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL)

#define	SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL)

#define	SPIM_RXD_PTR_PTR_Pos (0UL)

#define	SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos)

#define	SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL)

#define	SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos)

#define	SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL)

#define	SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos)

#define	SPIM_TXD_PTR_PTR_Pos (0UL)

#define	SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos)

#define	SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL)

#define	SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos)

#define	SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL)

#define	SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos)

#define	SPIM_CONFIG_CPOL_Pos (2UL)

#define	SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos)

#define	SPIM_CONFIG_CPOL_ActiveHigh (0UL)

#define	SPIM_CONFIG_CPOL_ActiveLow (1UL)

#define	SPIM_CONFIG_CPHA_Pos (1UL)

#define	SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos)

#define	SPIM_CONFIG_CPHA_Leading (0UL)

#define	SPIM_CONFIG_CPHA_Trailing (1UL)

#define	SPIM_CONFIG_ORDER_Pos (0UL)

#define	SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos)

#define	SPIM_CONFIG_ORDER_MsbFirst (0UL)

#define	SPIM_CONFIG_ORDER_LsbFirst (1UL)

#define	SPIM_ORC_ORC_Pos (0UL)

#define	SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos)

#define	SPIM_POWER_POWER_Pos (0UL)

#define	SPIM_POWER_POWER_Msk (0x1UL << SPIM_POWER_POWER_Pos)

#define	SPIM_POWER_POWER_Disabled (0UL)

#define	SPIM_POWER_POWER_Enabled (1UL)

#define	SPIS_SHORTS_END_ACQUIRE_Pos (2UL)

#define	SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos)

#define	SPIS_SHORTS_END_ACQUIRE_Disabled (0UL)

#define	SPIS_SHORTS_END_ACQUIRE_Enabled (1UL)

#define	SPIS_INTENSET_ACQUIRED_Pos (10UL)

#define	SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos)

#define	SPIS_INTENSET_ACQUIRED_Disabled (0UL)

#define	SPIS_INTENSET_ACQUIRED_Enabled (1UL)

#define	SPIS_INTENSET_ACQUIRED_Set (1UL)

#define	SPIS_INTENSET_END_Pos (1UL)

#define	SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos)

#define	SPIS_INTENSET_END_Disabled (0UL)

#define	SPIS_INTENSET_END_Enabled (1UL)

#define	SPIS_INTENSET_END_Set (1UL)

#define	SPIS_INTENCLR_ACQUIRED_Pos (10UL)

#define	SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos)

#define	SPIS_INTENCLR_ACQUIRED_Disabled (0UL)

#define	SPIS_INTENCLR_ACQUIRED_Enabled (1UL)

#define	SPIS_INTENCLR_ACQUIRED_Clear (1UL)

#define	SPIS_INTENCLR_END_Pos (1UL)

#define	SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos)

#define	SPIS_INTENCLR_END_Disabled (0UL)

#define	SPIS_INTENCLR_END_Enabled (1UL)

#define	SPIS_INTENCLR_END_Clear (1UL)

#define	SPIS_SEMSTAT_SEMSTAT_Pos (0UL)

#define	SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos)

#define	SPIS_SEMSTAT_SEMSTAT_Free (0x00UL)

#define	SPIS_SEMSTAT_SEMSTAT_CPU (0x01UL)

#define	SPIS_SEMSTAT_SEMSTAT_SPIS (0x02UL)

#define	SPIS_SEMSTAT_SEMSTAT_CPUPending (0x03UL)

#define	SPIS_STATUS_OVERFLOW_Pos (1UL)

#define	SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos)

#define	SPIS_STATUS_OVERFLOW_NotPresent (0UL)

#define	SPIS_STATUS_OVERFLOW_Present (1UL)

#define	SPIS_STATUS_OVERFLOW_Clear (1UL)

#define	SPIS_STATUS_OVERREAD_Pos (0UL)

#define	SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos)

#define	SPIS_STATUS_OVERREAD_NotPresent (0UL)

#define	SPIS_STATUS_OVERREAD_Present (1UL)

#define	SPIS_STATUS_OVERREAD_Clear (1UL)

#define	SPIS_ENABLE_ENABLE_Pos (0UL)

#define	SPIS_ENABLE_ENABLE_Msk (0x7UL << SPIS_ENABLE_ENABLE_Pos)

#define	SPIS_ENABLE_ENABLE_Disabled (0x00UL)

#define	SPIS_ENABLE_ENABLE_Enabled (0x02UL)

#define	SPIS_MAXRX_MAXRX_Pos (0UL)

#define	SPIS_MAXRX_MAXRX_Msk (0xFFUL << SPIS_MAXRX_MAXRX_Pos)

#define	SPIS_AMOUNTRX_AMOUNTRX_Pos (0UL)

#define	SPIS_AMOUNTRX_AMOUNTRX_Msk (0xFFUL << SPIS_AMOUNTRX_AMOUNTRX_Pos)

#define	SPIS_MAXTX_MAXTX_Pos (0UL)

#define	SPIS_MAXTX_MAXTX_Msk (0xFFUL << SPIS_MAXTX_MAXTX_Pos)

#define	SPIS_AMOUNTTX_AMOUNTTX_Pos (0UL)

#define	SPIS_AMOUNTTX_AMOUNTTX_Msk (0xFFUL << SPIS_AMOUNTTX_AMOUNTTX_Pos)

#define	SPIS_CONFIG_CPOL_Pos (2UL)

#define	SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos)

#define	SPIS_CONFIG_CPOL_ActiveHigh (0UL)

#define	SPIS_CONFIG_CPOL_ActiveLow (1UL)

#define	SPIS_CONFIG_CPHA_Pos (1UL)

#define	SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos)

#define	SPIS_CONFIG_CPHA_Leading (0UL)

#define	SPIS_CONFIG_CPHA_Trailing (1UL)

#define	SPIS_CONFIG_ORDER_Pos (0UL)

#define	SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos)

#define	SPIS_CONFIG_ORDER_MsbFirst (0UL)

#define	SPIS_CONFIG_ORDER_LsbFirst (1UL)

#define	SPIS_DEF_DEF_Pos (0UL)

#define	SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos)

#define	SPIS_ORC_ORC_Pos (0UL)

#define	SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos)

#define	SPIS_POWER_POWER_Pos (0UL)

#define	SPIS_POWER_POWER_Msk (0x1UL << SPIS_POWER_POWER_Pos)

#define	SPIS_POWER_POWER_Disabled (0UL)

#define	SPIS_POWER_POWER_Enabled (1UL)

#define	TEMP_INTENSET_DATARDY_Pos (0UL)

#define	TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos)

#define	TEMP_INTENSET_DATARDY_Disabled (0UL)

#define	TEMP_INTENSET_DATARDY_Enabled (1UL)

#define	TEMP_INTENSET_DATARDY_Set (1UL)

#define	TEMP_INTENCLR_DATARDY_Pos (0UL)

#define	TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos)

#define	TEMP_INTENCLR_DATARDY_Disabled (0UL)

#define	TEMP_INTENCLR_DATARDY_Enabled (1UL)

#define	TEMP_INTENCLR_DATARDY_Clear (1UL)

#define	TEMP_POWER_POWER_Pos (0UL)

#define	TEMP_POWER_POWER_Msk (0x1UL << TEMP_POWER_POWER_Pos)

#define	TEMP_POWER_POWER_Disabled (0UL)

#define	TEMP_POWER_POWER_Enabled (1UL)

#define	TIMER_SHORTS_COMPARE3_STOP_Pos (11UL)

#define	TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos)

#define	TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL)

#define	TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL)

#define	TIMER_SHORTS_COMPARE2_STOP_Pos (10UL)

#define	TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos)

#define	TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL)

#define	TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL)

#define	TIMER_SHORTS_COMPARE1_STOP_Pos (9UL)

#define	TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos)

#define	TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL)

#define	TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL)

#define	TIMER_SHORTS_COMPARE0_STOP_Pos (8UL)

#define	TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos)

#define	TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL)

#define	TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL)

#define	TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL)

#define	TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos)

#define	TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL)

#define	TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL)

#define	TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL)

#define	TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos)

#define	TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL)

#define	TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL)

#define	TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL)

#define	TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos)

#define	TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL)

#define	TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL)

#define	TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL)

#define	TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos)

#define	TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL)

#define	TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL)

#define	TIMER_INTENSET_COMPARE3_Pos (19UL)

#define	TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos)

#define	TIMER_INTENSET_COMPARE3_Disabled (0UL)

#define	TIMER_INTENSET_COMPARE3_Enabled (1UL)

#define	TIMER_INTENSET_COMPARE3_Set (1UL)

#define	TIMER_INTENSET_COMPARE2_Pos (18UL)

#define	TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos)

#define	TIMER_INTENSET_COMPARE2_Disabled (0UL)

#define	TIMER_INTENSET_COMPARE2_Enabled (1UL)

#define	TIMER_INTENSET_COMPARE2_Set (1UL)

#define	TIMER_INTENSET_COMPARE1_Pos (17UL)

#define	TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos)

#define	TIMER_INTENSET_COMPARE1_Disabled (0UL)

#define	TIMER_INTENSET_COMPARE1_Enabled (1UL)

#define	TIMER_INTENSET_COMPARE1_Set (1UL)

#define	TIMER_INTENSET_COMPARE0_Pos (16UL)

#define	TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos)

#define	TIMER_INTENSET_COMPARE0_Disabled (0UL)

#define	TIMER_INTENSET_COMPARE0_Enabled (1UL)

#define	TIMER_INTENSET_COMPARE0_Set (1UL)

#define	TIMER_INTENCLR_COMPARE3_Pos (19UL)

#define	TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos)

#define	TIMER_INTENCLR_COMPARE3_Disabled (0UL)

#define	TIMER_INTENCLR_COMPARE3_Enabled (1UL)

#define	TIMER_INTENCLR_COMPARE3_Clear (1UL)

#define	TIMER_INTENCLR_COMPARE2_Pos (18UL)

#define	TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos)

#define	TIMER_INTENCLR_COMPARE2_Disabled (0UL)

#define	TIMER_INTENCLR_COMPARE2_Enabled (1UL)

#define	TIMER_INTENCLR_COMPARE2_Clear (1UL)

#define	TIMER_INTENCLR_COMPARE1_Pos (17UL)

#define	TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos)

#define	TIMER_INTENCLR_COMPARE1_Disabled (0UL)

#define	TIMER_INTENCLR_COMPARE1_Enabled (1UL)

#define	TIMER_INTENCLR_COMPARE1_Clear (1UL)

#define	TIMER_INTENCLR_COMPARE0_Pos (16UL)

#define	TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos)

#define	TIMER_INTENCLR_COMPARE0_Disabled (0UL)

#define	TIMER_INTENCLR_COMPARE0_Enabled (1UL)

#define	TIMER_INTENCLR_COMPARE0_Clear (1UL)

#define	TIMER_MODE_MODE_Pos (0UL)

#define	TIMER_MODE_MODE_Msk (0x1UL << TIMER_MODE_MODE_Pos)

#define	TIMER_MODE_MODE_Timer (0UL)

#define	TIMER_MODE_MODE_Counter (1UL)

#define	TIMER_BITMODE_BITMODE_Pos (0UL)

#define	TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos)

#define	TIMER_BITMODE_BITMODE_16Bit (0x00UL)

#define	TIMER_BITMODE_BITMODE_08Bit (0x01UL)

#define	TIMER_BITMODE_BITMODE_24Bit (0x02UL)

#define	TIMER_BITMODE_BITMODE_32Bit (0x03UL)

#define	TIMER_PRESCALER_PRESCALER_Pos (0UL)

#define	TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos)

#define	TIMER_POWER_POWER_Pos (0UL)

#define	TIMER_POWER_POWER_Msk (0x1UL << TIMER_POWER_POWER_Pos)

#define	TIMER_POWER_POWER_Disabled (0UL)

#define	TIMER_POWER_POWER_Enabled (1UL)

#define	TWI_SHORTS_BB_STOP_Pos (1UL)

#define	TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos)

#define	TWI_SHORTS_BB_STOP_Disabled (0UL)

#define	TWI_SHORTS_BB_STOP_Enabled (1UL)

#define	TWI_SHORTS_BB_SUSPEND_Pos (0UL)

#define	TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos)

#define	TWI_SHORTS_BB_SUSPEND_Disabled (0UL)

#define	TWI_SHORTS_BB_SUSPEND_Enabled (1UL)

#define	TWI_INTENSET_SUSPENDED_Pos (18UL)

#define	TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos)

#define	TWI_INTENSET_SUSPENDED_Disabled (0UL)

#define	TWI_INTENSET_SUSPENDED_Enabled (1UL)

#define	TWI_INTENSET_SUSPENDED_Set (1UL)

#define	TWI_INTENSET_BB_Pos (14UL)

#define	TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos)

#define	TWI_INTENSET_BB_Disabled (0UL)

#define	TWI_INTENSET_BB_Enabled (1UL)

#define	TWI_INTENSET_BB_Set (1UL)

#define	TWI_INTENSET_ERROR_Pos (9UL)

#define	TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos)

#define	TWI_INTENSET_ERROR_Disabled (0UL)

#define	TWI_INTENSET_ERROR_Enabled (1UL)

#define	TWI_INTENSET_ERROR_Set (1UL)

#define	TWI_INTENSET_TXDSENT_Pos (7UL)

#define	TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos)

#define	TWI_INTENSET_TXDSENT_Disabled (0UL)

#define	TWI_INTENSET_TXDSENT_Enabled (1UL)

#define	TWI_INTENSET_TXDSENT_Set (1UL)

#define	TWI_INTENSET_RXDREADY_Pos (2UL)

#define	TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos)

#define	TWI_INTENSET_RXDREADY_Disabled (0UL)

#define	TWI_INTENSET_RXDREADY_Enabled (1UL)

#define	TWI_INTENSET_RXDREADY_Set (1UL)

#define	TWI_INTENSET_STOPPED_Pos (1UL)

#define	TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos)

#define	TWI_INTENSET_STOPPED_Disabled (0UL)

#define	TWI_INTENSET_STOPPED_Enabled (1UL)

#define	TWI_INTENSET_STOPPED_Set (1UL)

#define	TWI_INTENCLR_SUSPENDED_Pos (18UL)

#define	TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos)

#define	TWI_INTENCLR_SUSPENDED_Disabled (0UL)

#define	TWI_INTENCLR_SUSPENDED_Enabled (1UL)

#define	TWI_INTENCLR_SUSPENDED_Clear (1UL)

#define	TWI_INTENCLR_BB_Pos (14UL)

#define	TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos)

#define	TWI_INTENCLR_BB_Disabled (0UL)

#define	TWI_INTENCLR_BB_Enabled (1UL)

#define	TWI_INTENCLR_BB_Clear (1UL)

#define	TWI_INTENCLR_ERROR_Pos (9UL)

#define	TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos)

#define	TWI_INTENCLR_ERROR_Disabled (0UL)

#define	TWI_INTENCLR_ERROR_Enabled (1UL)

#define	TWI_INTENCLR_ERROR_Clear (1UL)

#define	TWI_INTENCLR_TXDSENT_Pos (7UL)

#define	TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos)

#define	TWI_INTENCLR_TXDSENT_Disabled (0UL)

#define	TWI_INTENCLR_TXDSENT_Enabled (1UL)

#define	TWI_INTENCLR_TXDSENT_Clear (1UL)

#define	TWI_INTENCLR_RXDREADY_Pos (2UL)

#define	TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos)

#define	TWI_INTENCLR_RXDREADY_Disabled (0UL)

#define	TWI_INTENCLR_RXDREADY_Enabled (1UL)

#define	TWI_INTENCLR_RXDREADY_Clear (1UL)

#define	TWI_INTENCLR_STOPPED_Pos (1UL)

#define	TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos)

#define	TWI_INTENCLR_STOPPED_Disabled (0UL)

#define	TWI_INTENCLR_STOPPED_Enabled (1UL)

#define	TWI_INTENCLR_STOPPED_Clear (1UL)

#define	TWI_ERRORSRC_DNACK_Pos (2UL)

#define	TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos)

#define	TWI_ERRORSRC_DNACK_NotPresent (0UL)

#define	TWI_ERRORSRC_DNACK_Present (1UL)

#define	TWI_ERRORSRC_DNACK_Clear (1UL)

#define	TWI_ERRORSRC_ANACK_Pos (1UL)

#define	TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos)

#define	TWI_ERRORSRC_ANACK_NotPresent (0UL)

#define	TWI_ERRORSRC_ANACK_Present (1UL)

#define	TWI_ERRORSRC_ANACK_Clear (1UL)

#define	TWI_ERRORSRC_OVERRUN_Pos (0UL)

#define	TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos)

#define	TWI_ERRORSRC_OVERRUN_NotPresent (0UL)

#define	TWI_ERRORSRC_OVERRUN_Present (1UL)

#define	TWI_ERRORSRC_OVERRUN_Clear (1UL)

#define	TWI_ENABLE_ENABLE_Pos (0UL)

#define	TWI_ENABLE_ENABLE_Msk (0x7UL << TWI_ENABLE_ENABLE_Pos)

#define	TWI_ENABLE_ENABLE_Disabled (0x00UL)

#define	TWI_ENABLE_ENABLE_Enabled (0x05UL)

#define	TWI_RXD_RXD_Pos (0UL)

#define	TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos)

#define	TWI_TXD_TXD_Pos (0UL)

#define	TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos)

#define	TWI_FREQUENCY_FREQUENCY_Pos (0UL)

#define	TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos)

#define	TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL)

#define	TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL)

#define	TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL)

#define	TWI_ADDRESS_ADDRESS_Pos (0UL)

#define	TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos)

#define	TWI_POWER_POWER_Pos (0UL)

#define	TWI_POWER_POWER_Msk (0x1UL << TWI_POWER_POWER_Pos)

#define	TWI_POWER_POWER_Disabled (0UL)

#define	TWI_POWER_POWER_Enabled (1UL)

#define	UART_INTENSET_RXTO_Pos (17UL)

#define	UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos)

#define	UART_INTENSET_RXTO_Disabled (0UL)

#define	UART_INTENSET_RXTO_Enabled (1UL)

#define	UART_INTENSET_RXTO_Set (1UL)

#define	UART_INTENSET_ERROR_Pos (9UL)

#define	UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos)

#define	UART_INTENSET_ERROR_Disabled (0UL)

#define	UART_INTENSET_ERROR_Enabled (1UL)

#define	UART_INTENSET_ERROR_Set (1UL)

#define	UART_INTENSET_TXDRDY_Pos (7UL)

#define	UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos)

#define	UART_INTENSET_TXDRDY_Disabled (0UL)

#define	UART_INTENSET_TXDRDY_Enabled (1UL)

#define	UART_INTENSET_TXDRDY_Set (1UL)

#define	UART_INTENSET_RXDRDY_Pos (2UL)

#define	UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos)

#define	UART_INTENSET_RXDRDY_Disabled (0UL)

#define	UART_INTENSET_RXDRDY_Enabled (1UL)

#define	UART_INTENSET_RXDRDY_Set (1UL)

#define	UART_INTENSET_NCTS_Pos (1UL)

#define	UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos)

#define	UART_INTENSET_NCTS_Disabled (0UL)

#define	UART_INTENSET_NCTS_Enabled (1UL)

#define	UART_INTENSET_NCTS_Set (1UL)

#define	UART_INTENSET_CTS_Pos (0UL)

#define	UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos)

#define	UART_INTENSET_CTS_Disabled (0UL)

#define	UART_INTENSET_CTS_Enabled (1UL)

#define	UART_INTENSET_CTS_Set (1UL)

#define	UART_INTENCLR_RXTO_Pos (17UL)

#define	UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos)

#define	UART_INTENCLR_RXTO_Disabled (0UL)

#define	UART_INTENCLR_RXTO_Enabled (1UL)

#define	UART_INTENCLR_RXTO_Clear (1UL)

#define	UART_INTENCLR_ERROR_Pos (9UL)

#define	UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos)

#define	UART_INTENCLR_ERROR_Disabled (0UL)

#define	UART_INTENCLR_ERROR_Enabled (1UL)

#define	UART_INTENCLR_ERROR_Clear (1UL)

#define	UART_INTENCLR_TXDRDY_Pos (7UL)

#define	UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos)

#define	UART_INTENCLR_TXDRDY_Disabled (0UL)

#define	UART_INTENCLR_TXDRDY_Enabled (1UL)

#define	UART_INTENCLR_TXDRDY_Clear (1UL)

#define	UART_INTENCLR_RXDRDY_Pos (2UL)

#define	UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos)

#define	UART_INTENCLR_RXDRDY_Disabled (0UL)

#define	UART_INTENCLR_RXDRDY_Enabled (1UL)

#define	UART_INTENCLR_RXDRDY_Clear (1UL)

#define	UART_INTENCLR_NCTS_Pos (1UL)

#define	UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos)

#define	UART_INTENCLR_NCTS_Disabled (0UL)

#define	UART_INTENCLR_NCTS_Enabled (1UL)

#define	UART_INTENCLR_NCTS_Clear (1UL)

#define	UART_INTENCLR_CTS_Pos (0UL)

#define	UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos)

#define	UART_INTENCLR_CTS_Disabled (0UL)

#define	UART_INTENCLR_CTS_Enabled (1UL)

#define	UART_INTENCLR_CTS_Clear (1UL)

#define	UART_ERRORSRC_BREAK_Pos (3UL)

#define	UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos)

#define	UART_ERRORSRC_BREAK_NotPresent (0UL)

#define	UART_ERRORSRC_BREAK_Present (1UL)

#define	UART_ERRORSRC_BREAK_Clear (1UL)

#define	UART_ERRORSRC_FRAMING_Pos (2UL)

#define	UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos)

#define	UART_ERRORSRC_FRAMING_NotPresent (0UL)

#define	UART_ERRORSRC_FRAMING_Present (1UL)

#define	UART_ERRORSRC_FRAMING_Clear (1UL)

#define	UART_ERRORSRC_PARITY_Pos (1UL)

#define	UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos)

#define	UART_ERRORSRC_PARITY_NotPresent (0UL)

#define	UART_ERRORSRC_PARITY_Present (1UL)

#define	UART_ERRORSRC_PARITY_Clear (1UL)

#define	UART_ERRORSRC_OVERRUN_Pos (0UL)

#define	UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos)

#define	UART_ERRORSRC_OVERRUN_NotPresent (0UL)

#define	UART_ERRORSRC_OVERRUN_Present (1UL)

#define	UART_ERRORSRC_OVERRUN_Clear (1UL)

#define	UART_ENABLE_ENABLE_Pos (0UL)

#define	UART_ENABLE_ENABLE_Msk (0x7UL << UART_ENABLE_ENABLE_Pos)

#define	UART_ENABLE_ENABLE_Disabled (0x00UL)

#define	UART_ENABLE_ENABLE_Enabled (0x04UL)

#define	UART_RXD_RXD_Pos (0UL)

#define	UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos)

#define	UART_TXD_TXD_Pos (0UL)

#define	UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos)

#define	UART_BAUDRATE_BAUDRATE_Pos (0UL)

#define	UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos)

#define	UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL)

#define	UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL)

#define	UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL)

#define	UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL)

#define	UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL)

#define	UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL)

#define	UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL)

#define	UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL)

#define	UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL)

#define	UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL)

#define	UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL)

#define	UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL)

#define	UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL)

#define	UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL)

#define	UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL)

#define	UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL)

#define	UART_CONFIG_PARITY_Pos (1UL)

#define	UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos)

#define	UART_CONFIG_PARITY_Excluded (0UL)

#define	UART_CONFIG_PARITY_Included (7UL)

#define	UART_CONFIG_HWFC_Pos (0UL)

#define	UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos)

#define	UART_CONFIG_HWFC_Disabled (0UL)

#define	UART_CONFIG_HWFC_Enabled (1UL)

#define	UART_POWER_POWER_Pos (0UL)

#define	UART_POWER_POWER_Msk (0x1UL << UART_POWER_POWER_Pos)

#define	UART_POWER_POWER_Disabled (0UL)

#define	UART_POWER_POWER_Enabled (1UL)

#define	UICR_RBPCONF_PALL_Pos (8UL)

#define	UICR_RBPCONF_PALL_Msk (0xFFUL << UICR_RBPCONF_PALL_Pos)

#define	UICR_RBPCONF_PALL_Enabled (0x00UL)

#define	UICR_RBPCONF_PALL_Disabled (0xFFUL)

#define	UICR_RBPCONF_PR0_Pos (0UL)

#define	UICR_RBPCONF_PR0_Msk (0xFFUL << UICR_RBPCONF_PR0_Pos)

#define	UICR_RBPCONF_PR0_Enabled (0x00UL)

#define	UICR_RBPCONF_PR0_Disabled (0xFFUL)

#define	UICR_XTALFREQ_XTALFREQ_Pos (0UL)

#define	UICR_XTALFREQ_XTALFREQ_Msk (0xFFUL << UICR_XTALFREQ_XTALFREQ_Pos)

#define	UICR_XTALFREQ_XTALFREQ_32MHz (0x00UL)

#define	UICR_XTALFREQ_XTALFREQ_16MHz (0xFFUL)

#define	UICR_FWID_FWID_Pos (0UL)

#define	UICR_FWID_FWID_Msk (0xFFFFUL << UICR_FWID_FWID_Pos)

#define	WDT_INTENSET_TIMEOUT_Pos (0UL)

#define	WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos)

#define	WDT_INTENSET_TIMEOUT_Disabled (0UL)

#define	WDT_INTENSET_TIMEOUT_Enabled (1UL)

#define	WDT_INTENSET_TIMEOUT_Set (1UL)

#define	WDT_INTENCLR_TIMEOUT_Pos (0UL)

#define	WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos)

#define	WDT_INTENCLR_TIMEOUT_Disabled (0UL)

#define	WDT_INTENCLR_TIMEOUT_Enabled (1UL)

#define	WDT_INTENCLR_TIMEOUT_Clear (1UL)

#define	WDT_RUNSTATUS_RUNSTATUS_Pos (0UL)

#define	WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos)

#define	WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL)

#define	WDT_RUNSTATUS_RUNSTATUS_Running (1UL)

#define	WDT_REQSTATUS_RR7_Pos (7UL)

#define	WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos)

#define	WDT_REQSTATUS_RR7_DisabledOrRequested (0UL)

#define	WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL)

#define	WDT_REQSTATUS_RR6_Pos (6UL)

#define	WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos)

#define	WDT_REQSTATUS_RR6_DisabledOrRequested (0UL)

#define	WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL)

#define	WDT_REQSTATUS_RR5_Pos (5UL)

#define	WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos)

#define	WDT_REQSTATUS_RR5_DisabledOrRequested (0UL)

#define	WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL)

#define	WDT_REQSTATUS_RR4_Pos (4UL)

#define	WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos)

#define	WDT_REQSTATUS_RR4_DisabledOrRequested (0UL)

#define	WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL)

#define	WDT_REQSTATUS_RR3_Pos (3UL)

#define	WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos)

#define	WDT_REQSTATUS_RR3_DisabledOrRequested (0UL)

#define	WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL)

#define	WDT_REQSTATUS_RR2_Pos (2UL)

#define	WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos)

#define	WDT_REQSTATUS_RR2_DisabledOrRequested (0UL)

#define	WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL)

#define	WDT_REQSTATUS_RR1_Pos (1UL)

#define	WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos)

#define	WDT_REQSTATUS_RR1_DisabledOrRequested (0UL)

#define	WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL)

#define	WDT_REQSTATUS_RR0_Pos (0UL)

#define	WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos)

#define	WDT_REQSTATUS_RR0_DisabledOrRequested (0UL)

#define	WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL)

#define	WDT_RREN_RR7_Pos (7UL)

#define	WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos)

#define	WDT_RREN_RR7_Disabled (0UL)

#define	WDT_RREN_RR7_Enabled (1UL)

#define	WDT_RREN_RR6_Pos (6UL)

#define	WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos)

#define	WDT_RREN_RR6_Disabled (0UL)

#define	WDT_RREN_RR6_Enabled (1UL)

#define	WDT_RREN_RR5_Pos (5UL)

#define	WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos)

#define	WDT_RREN_RR5_Disabled (0UL)

#define	WDT_RREN_RR5_Enabled (1UL)

#define	WDT_RREN_RR4_Pos (4UL)

#define	WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos)

#define	WDT_RREN_RR4_Disabled (0UL)

#define	WDT_RREN_RR4_Enabled (1UL)

#define	WDT_RREN_RR3_Pos (3UL)

#define	WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos)

#define	WDT_RREN_RR3_Disabled (0UL)

#define	WDT_RREN_RR3_Enabled (1UL)

#define	WDT_RREN_RR2_Pos (2UL)

#define	WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos)

#define	WDT_RREN_RR2_Disabled (0UL)

#define	WDT_RREN_RR2_Enabled (1UL)

#define	WDT_RREN_RR1_Pos (1UL)

#define	WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos)

#define	WDT_RREN_RR1_Disabled (0UL)

#define	WDT_RREN_RR1_Enabled (1UL)

#define	WDT_RREN_RR0_Pos (0UL)

#define	WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos)

#define	WDT_RREN_RR0_Disabled (0UL)

#define	WDT_RREN_RR0_Enabled (1UL)

#define	WDT_CONFIG_HALT_Pos (3UL)

#define	WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos)

#define	WDT_CONFIG_HALT_Pause (0UL)

#define	WDT_CONFIG_HALT_Run (1UL)

#define	WDT_CONFIG_SLEEP_Pos (0UL)

#define	WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos)

#define	WDT_CONFIG_SLEEP_Pause (0UL)

#define	WDT_CONFIG_SLEEP_Run (1UL)

#define	WDT_RR_RR_Pos (0UL)

#define	WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos)

#define	WDT_RR_RR_Reload (0x6E524635UL)

#define	WDT_POWER_POWER_Pos (0UL)

#define	WDT_POWER_POWER_Msk (0x1UL << WDT_POWER_POWER_Pos)

#define	WDT_POWER_POWER_Disabled (0UL)

#define	WDT_POWER_POWER_Enabled (1UL)

Macro Definition Documentation

◆ AAR_ENABLE_ENABLE_Disabled

#define AAR_ENABLE_ENABLE_Disabled (0x00UL)

Disabled AAR.

Definition at line 103 of file nrf51_bitfields.h.

◆ AAR_ENABLE_ENABLE_Enabled

#define AAR_ENABLE_ENABLE_Enabled (0x03UL)

Enable AAR.

Definition at line 104 of file nrf51_bitfields.h.

◆ AAR_ENABLE_ENABLE_Msk

#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos)

Bit mask of ENABLE field.

Definition at line 102 of file nrf51_bitfields.h.

◆ AAR_ENABLE_ENABLE_Pos

#define AAR_ENABLE_ENABLE_Pos (0UL)

Position of ENABLE field.

Definition at line 101 of file nrf51_bitfields.h.

◆ AAR_INTENCLR_END_Clear

#define AAR_INTENCLR_END_Clear (1UL)

Disable interrupt on write.

Definition at line 88 of file nrf51_bitfields.h.

◆ AAR_INTENCLR_END_Disabled

#define AAR_INTENCLR_END_Disabled (0UL)

Interrupt disabled.

Definition at line 86 of file nrf51_bitfields.h.

◆ AAR_INTENCLR_END_Enabled

#define AAR_INTENCLR_END_Enabled (1UL)

Interrupt enabled.

Definition at line 87 of file nrf51_bitfields.h.

◆ AAR_INTENCLR_END_Msk

#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos)

Bit mask of END field.

Definition at line 85 of file nrf51_bitfields.h.

◆ AAR_INTENCLR_END_Pos

#define AAR_INTENCLR_END_Pos (0UL)

Position of END field.

Definition at line 84 of file nrf51_bitfields.h.

◆ AAR_INTENCLR_NOTRESOLVED_Clear

#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL)

Disable interrupt on write.

Definition at line 74 of file nrf51_bitfields.h.

◆ AAR_INTENCLR_NOTRESOLVED_Disabled

#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL)

Interrupt disabled.

Definition at line 72 of file nrf51_bitfields.h.

◆ AAR_INTENCLR_NOTRESOLVED_Enabled

#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL)

Interrupt enabled.

Definition at line 73 of file nrf51_bitfields.h.

◆ AAR_INTENCLR_NOTRESOLVED_Msk

#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos)

Bit mask of NOTRESOLVED field.

Definition at line 71 of file nrf51_bitfields.h.

◆ AAR_INTENCLR_NOTRESOLVED_Pos

#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL)

Position of NOTRESOLVED field.

Definition at line 70 of file nrf51_bitfields.h.

◆ AAR_INTENCLR_RESOLVED_Clear

#define AAR_INTENCLR_RESOLVED_Clear (1UL)

Disable interrupt on write.

Definition at line 81 of file nrf51_bitfields.h.

◆ AAR_INTENCLR_RESOLVED_Disabled

#define AAR_INTENCLR_RESOLVED_Disabled (0UL)

Interrupt disabled.

Definition at line 79 of file nrf51_bitfields.h.

◆ AAR_INTENCLR_RESOLVED_Enabled

#define AAR_INTENCLR_RESOLVED_Enabled (1UL)

Interrupt enabled.

Definition at line 80 of file nrf51_bitfields.h.

◆ AAR_INTENCLR_RESOLVED_Msk

#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos)

Bit mask of RESOLVED field.

Definition at line 78 of file nrf51_bitfields.h.

◆ AAR_INTENCLR_RESOLVED_Pos

#define AAR_INTENCLR_RESOLVED_Pos (1UL)

Position of RESOLVED field.

Definition at line 77 of file nrf51_bitfields.h.

◆ AAR_INTENSET_END_Disabled

#define AAR_INTENSET_END_Disabled (0UL)

Interrupt disabled.

Definition at line 62 of file nrf51_bitfields.h.

◆ AAR_INTENSET_END_Enabled

#define AAR_INTENSET_END_Enabled (1UL)

Interrupt enabled.

Definition at line 63 of file nrf51_bitfields.h.

◆ AAR_INTENSET_END_Msk

#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos)

Bit mask of END field.

Definition at line 61 of file nrf51_bitfields.h.

◆ AAR_INTENSET_END_Pos

#define AAR_INTENSET_END_Pos (0UL)

Position of END field.

Definition at line 60 of file nrf51_bitfields.h.

◆ AAR_INTENSET_END_Set

#define AAR_INTENSET_END_Set (1UL)

Enable interrupt on write.

Definition at line 64 of file nrf51_bitfields.h.

◆ AAR_INTENSET_NOTRESOLVED_Disabled

#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL)

Interrupt disabled.

Definition at line 48 of file nrf51_bitfields.h.

◆ AAR_INTENSET_NOTRESOLVED_Enabled

#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL)

Interrupt enabled.

Definition at line 49 of file nrf51_bitfields.h.

◆ AAR_INTENSET_NOTRESOLVED_Msk

#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos)

Bit mask of NOTRESOLVED field.

Definition at line 47 of file nrf51_bitfields.h.

◆ AAR_INTENSET_NOTRESOLVED_Pos

#define AAR_INTENSET_NOTRESOLVED_Pos (2UL)

Position of NOTRESOLVED field.

Definition at line 46 of file nrf51_bitfields.h.

◆ AAR_INTENSET_NOTRESOLVED_Set

#define AAR_INTENSET_NOTRESOLVED_Set (1UL)

Enable interrupt on write.

Definition at line 50 of file nrf51_bitfields.h.

◆ AAR_INTENSET_RESOLVED_Disabled

#define AAR_INTENSET_RESOLVED_Disabled (0UL)

Interrupt disabled.

Definition at line 55 of file nrf51_bitfields.h.

◆ AAR_INTENSET_RESOLVED_Enabled

#define AAR_INTENSET_RESOLVED_Enabled (1UL)

Interrupt enabled.

Definition at line 56 of file nrf51_bitfields.h.

◆ AAR_INTENSET_RESOLVED_Msk

#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos)

Bit mask of RESOLVED field.

Definition at line 54 of file nrf51_bitfields.h.

◆ AAR_INTENSET_RESOLVED_Pos

#define AAR_INTENSET_RESOLVED_Pos (1UL)

Position of RESOLVED field.

Definition at line 53 of file nrf51_bitfields.h.

◆ AAR_INTENSET_RESOLVED_Set

#define AAR_INTENSET_RESOLVED_Set (1UL)

Enable interrupt on write.

Definition at line 57 of file nrf51_bitfields.h.

◆ AAR_NIRK_NIRK_Msk

#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos)

Bit mask of NIRK field.

Definition at line 111 of file nrf51_bitfields.h.

◆ AAR_NIRK_NIRK_Pos

#define AAR_NIRK_NIRK_Pos (0UL)

Position of NIRK field.

Definition at line 110 of file nrf51_bitfields.h.

◆ AAR_POWER_POWER_Disabled

#define AAR_POWER_POWER_Disabled (0UL)

Module power disabled.

Definition at line 119 of file nrf51_bitfields.h.

◆ AAR_POWER_POWER_Enabled

#define AAR_POWER_POWER_Enabled (1UL)

Module power enabled.

Definition at line 120 of file nrf51_bitfields.h.

◆ AAR_POWER_POWER_Msk

#define AAR_POWER_POWER_Msk (0x1UL << AAR_POWER_POWER_Pos)

Bit mask of POWER field.

Definition at line 118 of file nrf51_bitfields.h.

◆ AAR_POWER_POWER_Pos

#define AAR_POWER_POWER_Pos (0UL)

Position of POWER field.

Definition at line 117 of file nrf51_bitfields.h.

◆ AAR_STATUS_STATUS_Msk

#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos)

Bit mask of STATUS field.

Definition at line 95 of file nrf51_bitfields.h.

◆ AAR_STATUS_STATUS_Pos

#define AAR_STATUS_STATUS_Pos (0UL)

Position of STATUS field.

Definition at line 94 of file nrf51_bitfields.h.

◆ ADC_BUSY_BUSY_Busy

#define ADC_BUSY_BUSY_Busy (1UL)

An ADC conversion is taking place. ADC is busy.

Definition at line 153 of file nrf51_bitfields.h.

◆ ADC_BUSY_BUSY_Msk

#define ADC_BUSY_BUSY_Msk (0x1UL << ADC_BUSY_BUSY_Pos)

Bit mask of BUSY field.

Definition at line 151 of file nrf51_bitfields.h.

◆ ADC_BUSY_BUSY_Pos

#define ADC_BUSY_BUSY_Pos (0UL)

Position of BUSY field.

Definition at line 150 of file nrf51_bitfields.h.

◆ ADC_BUSY_BUSY_Ready

#define ADC_BUSY_BUSY_Ready (0UL)

No ongoing ADC conversion is taking place. ADC is ready.

Definition at line 152 of file nrf51_bitfields.h.

◆ ADC_CONFIG_EXTREFSEL_AnalogReference0

#define ADC_CONFIG_EXTREFSEL_AnalogReference0 (1UL)

Use analog reference 0 as reference.

Definition at line 171 of file nrf51_bitfields.h.

◆ ADC_CONFIG_EXTREFSEL_AnalogReference1

#define ADC_CONFIG_EXTREFSEL_AnalogReference1 (2UL)

Use analog reference 1 as reference.

Definition at line 172 of file nrf51_bitfields.h.

◆ ADC_CONFIG_EXTREFSEL_Msk

#define ADC_CONFIG_EXTREFSEL_Msk (0x3UL << ADC_CONFIG_EXTREFSEL_Pos)

Bit mask of EXTREFSEL field.

Definition at line 169 of file nrf51_bitfields.h.

◆ ADC_CONFIG_EXTREFSEL_None

#define ADC_CONFIG_EXTREFSEL_None (0UL)

Analog external reference inputs disabled.

Definition at line 170 of file nrf51_bitfields.h.

◆ ADC_CONFIG_EXTREFSEL_Pos

#define ADC_CONFIG_EXTREFSEL_Pos (16UL)

Position of EXTREFSEL field.

Definition at line 168 of file nrf51_bitfields.h.

◆ ADC_CONFIG_INPSEL_AnalogInputNoPrescaling

#define ADC_CONFIG_INPSEL_AnalogInputNoPrescaling (0x00UL)

Analog input specified by PSEL with no prescaling used as input for the conversion.

Definition at line 198 of file nrf51_bitfields.h.

◆ ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling

#define ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling (0x02UL)

Analog input specified by PSEL with 1/3 prescaling used as input for the conversion.

Definition at line 200 of file nrf51_bitfields.h.

◆ ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling

#define ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling (0x01UL)

Analog input specified by PSEL with 2/3 prescaling used as input for the conversion.

Definition at line 199 of file nrf51_bitfields.h.

◆ ADC_CONFIG_INPSEL_Msk

#define ADC_CONFIG_INPSEL_Msk (0x7UL << ADC_CONFIG_INPSEL_Pos)

Bit mask of INPSEL field.

Definition at line 197 of file nrf51_bitfields.h.

◆ ADC_CONFIG_INPSEL_Pos

#define ADC_CONFIG_INPSEL_Pos (2UL)

Position of INPSEL field.

Definition at line 196 of file nrf51_bitfields.h.

◆ ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling

#define ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling (0x06UL)

Supply voltage with 1/3 prescaling used as input for the conversion.

Definition at line 202 of file nrf51_bitfields.h.

◆ ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling

#define ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling (0x05UL)

Supply voltage with 2/3 prescaling used as input for the conversion.

Definition at line 201 of file nrf51_bitfields.h.

◆ ADC_CONFIG_PSEL_AnalogInput0

#define ADC_CONFIG_PSEL_AnalogInput0 (1UL)

Use analog input 0 as analog input.

Definition at line 178 of file nrf51_bitfields.h.

◆ ADC_CONFIG_PSEL_AnalogInput1

#define ADC_CONFIG_PSEL_AnalogInput1 (2UL)

Use analog input 1 as analog input.

Definition at line 179 of file nrf51_bitfields.h.

◆ ADC_CONFIG_PSEL_AnalogInput2

#define ADC_CONFIG_PSEL_AnalogInput2 (4UL)

Use analog input 2 as analog input.

Definition at line 180 of file nrf51_bitfields.h.

◆ ADC_CONFIG_PSEL_AnalogInput3

#define ADC_CONFIG_PSEL_AnalogInput3 (8UL)

Use analog input 3 as analog input.

Definition at line 181 of file nrf51_bitfields.h.

◆ ADC_CONFIG_PSEL_AnalogInput4

#define ADC_CONFIG_PSEL_AnalogInput4 (16UL)

Use analog input 4 as analog input.

Definition at line 182 of file nrf51_bitfields.h.

◆ ADC_CONFIG_PSEL_AnalogInput5

#define ADC_CONFIG_PSEL_AnalogInput5 (32UL)

Use analog input 5 as analog input.

Definition at line 183 of file nrf51_bitfields.h.

◆ ADC_CONFIG_PSEL_AnalogInput6

#define ADC_CONFIG_PSEL_AnalogInput6 (64UL)

Use analog input 6 as analog input.

Definition at line 184 of file nrf51_bitfields.h.

◆ ADC_CONFIG_PSEL_AnalogInput7

#define ADC_CONFIG_PSEL_AnalogInput7 (128UL)

Use analog input 7 as analog input.

Definition at line 185 of file nrf51_bitfields.h.

◆ ADC_CONFIG_PSEL_Disabled

#define ADC_CONFIG_PSEL_Disabled (0UL)

Analog input pins disabled.

Definition at line 177 of file nrf51_bitfields.h.

◆ ADC_CONFIG_PSEL_Msk

#define ADC_CONFIG_PSEL_Msk (0xFFUL << ADC_CONFIG_PSEL_Pos)

Bit mask of PSEL field.

Definition at line 176 of file nrf51_bitfields.h.

◆ ADC_CONFIG_PSEL_Pos

#define ADC_CONFIG_PSEL_Pos (8UL)

Position of PSEL field.

Definition at line 175 of file nrf51_bitfields.h.

◆ ADC_CONFIG_REFSEL_External

#define ADC_CONFIG_REFSEL_External (0x01UL)

Use external source configured by EXTREFSEL as reference for conversion.

Definition at line 191 of file nrf51_bitfields.h.

◆ ADC_CONFIG_REFSEL_Msk

#define ADC_CONFIG_REFSEL_Msk (0x3UL << ADC_CONFIG_REFSEL_Pos)

Bit mask of REFSEL field.

Definition at line 189 of file nrf51_bitfields.h.

◆ ADC_CONFIG_REFSEL_Pos

#define ADC_CONFIG_REFSEL_Pos (5UL)

Position of REFSEL field.

Definition at line 188 of file nrf51_bitfields.h.

◆ ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling

#define ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling (0x02UL)

Use supply voltage with 1/2 prescaling as reference for conversion. Only usable when supply voltage is between 1.7V and 2.6V.

Definition at line 192 of file nrf51_bitfields.h.

◆ ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling

#define ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling (0x03UL)

Use supply voltage with 1/3 prescaling as reference for conversion. Only usable when supply voltage is between 2.5V and 3.6V.

Definition at line 193 of file nrf51_bitfields.h.

◆ ADC_CONFIG_REFSEL_VBG

#define ADC_CONFIG_REFSEL_VBG (0x00UL)

Use internal 1.2V bandgap voltage as reference for conversion.

Definition at line 190 of file nrf51_bitfields.h.

◆ ADC_CONFIG_RES_10bit

#define ADC_CONFIG_RES_10bit (0x02UL)

10bit ADC resolution.

Definition at line 209 of file nrf51_bitfields.h.

◆ ADC_CONFIG_RES_8bit

#define ADC_CONFIG_RES_8bit (0x00UL)

8bit ADC resolution.

Definition at line 207 of file nrf51_bitfields.h.

◆ ADC_CONFIG_RES_9bit

#define ADC_CONFIG_RES_9bit (0x01UL)

9bit ADC resolution.

Definition at line 208 of file nrf51_bitfields.h.

◆ ADC_CONFIG_RES_Msk

#define ADC_CONFIG_RES_Msk (0x3UL << ADC_CONFIG_RES_Pos)

Bit mask of RES field.

Definition at line 206 of file nrf51_bitfields.h.

◆ ADC_CONFIG_RES_Pos

#define ADC_CONFIG_RES_Pos (0UL)

Position of RES field.

Definition at line 205 of file nrf51_bitfields.h.

◆ ADC_ENABLE_ENABLE_Disabled

#define ADC_ENABLE_ENABLE_Disabled (0x00UL)

ADC is disabled.

Definition at line 161 of file nrf51_bitfields.h.

◆ ADC_ENABLE_ENABLE_Enabled

#define ADC_ENABLE_ENABLE_Enabled (0x01UL)

ADC is enabled. If an analog input pin is selected as source of the conversion, the selected pin is configured as an analog input.

Definition at line 162 of file nrf51_bitfields.h.

◆ ADC_ENABLE_ENABLE_Msk

#define ADC_ENABLE_ENABLE_Msk (0x3UL << ADC_ENABLE_ENABLE_Pos)

Bit mask of ENABLE field.

Definition at line 160 of file nrf51_bitfields.h.

◆ ADC_ENABLE_ENABLE_Pos

#define ADC_ENABLE_ENABLE_Pos (0UL)

Position of ENABLE field.

Definition at line 159 of file nrf51_bitfields.h.

◆ ADC_INTENCLR_END_Clear

#define ADC_INTENCLR_END_Clear (1UL)

Disable interrupt on write.

Definition at line 144 of file nrf51_bitfields.h.

◆ ADC_INTENCLR_END_Disabled

#define ADC_INTENCLR_END_Disabled (0UL)

Interrupt disabled.

Definition at line 142 of file nrf51_bitfields.h.

◆ ADC_INTENCLR_END_Enabled

#define ADC_INTENCLR_END_Enabled (1UL)

Interrupt enabled.

Definition at line 143 of file nrf51_bitfields.h.

◆ ADC_INTENCLR_END_Msk

#define ADC_INTENCLR_END_Msk (0x1UL << ADC_INTENCLR_END_Pos)

Bit mask of END field.

Definition at line 141 of file nrf51_bitfields.h.

◆ ADC_INTENCLR_END_Pos

#define ADC_INTENCLR_END_Pos (0UL)

Position of END field.

Definition at line 140 of file nrf51_bitfields.h.

◆ ADC_INTENSET_END_Disabled

#define ADC_INTENSET_END_Disabled (0UL)

Interrupt disabled.

Definition at line 132 of file nrf51_bitfields.h.

◆ ADC_INTENSET_END_Enabled

#define ADC_INTENSET_END_Enabled (1UL)

Interrupt enabled.

Definition at line 133 of file nrf51_bitfields.h.

◆ ADC_INTENSET_END_Msk

#define ADC_INTENSET_END_Msk (0x1UL << ADC_INTENSET_END_Pos)

Bit mask of END field.

Definition at line 131 of file nrf51_bitfields.h.

◆ ADC_INTENSET_END_Pos

#define ADC_INTENSET_END_Pos (0UL)

Position of END field.

Definition at line 130 of file nrf51_bitfields.h.

◆ ADC_INTENSET_END_Set

#define ADC_INTENSET_END_Set (1UL)

Enable interrupt on write.

Definition at line 134 of file nrf51_bitfields.h.

◆ ADC_POWER_POWER_Disabled

#define ADC_POWER_POWER_Disabled (0UL)

Module power disabled.

Definition at line 224 of file nrf51_bitfields.h.

◆ ADC_POWER_POWER_Enabled

#define ADC_POWER_POWER_Enabled (1UL)

Module power enabled.

Definition at line 225 of file nrf51_bitfields.h.

◆ ADC_POWER_POWER_Msk

#define ADC_POWER_POWER_Msk (0x1UL << ADC_POWER_POWER_Pos)

Bit mask of POWER field.

Definition at line 223 of file nrf51_bitfields.h.

◆ ADC_POWER_POWER_Pos

#define ADC_POWER_POWER_Pos (0UL)

Position of POWER field.

Definition at line 222 of file nrf51_bitfields.h.

◆ ADC_RESULT_RESULT_Msk

#define ADC_RESULT_RESULT_Msk (0x3FFUL << ADC_RESULT_RESULT_Pos)

Bit mask of RESULT field.

Definition at line 216 of file nrf51_bitfields.h.

◆ ADC_RESULT_RESULT_Pos

#define ADC_RESULT_RESULT_Pos (0UL)

Position of RESULT field.

Definition at line 215 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM0_Msk

#define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos)

Bit mask of RAM0 field.

Definition at line 815 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM0_Pos

#define AMLI_RAMPRI_AAR_RAM0_Pos (0UL)

Position of RAM0 field.

Definition at line 814 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM0_Pri0

#define AMLI_RAMPRI_AAR_RAM0_Pri0 (0x0UL)

Priority 0.

Definition at line 816 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM0_Pri10

#define AMLI_RAMPRI_AAR_RAM0_Pri10 (0xAUL)

Priority 10.

Definition at line 821 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM0_Pri12

#define AMLI_RAMPRI_AAR_RAM0_Pri12 (0xCUL)

Priority 12.

Definition at line 822 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM0_Pri14

#define AMLI_RAMPRI_AAR_RAM0_Pri14 (0xEUL)

Priority 14.

Definition at line 823 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM0_Pri2

#define AMLI_RAMPRI_AAR_RAM0_Pri2 (0x2UL)

Priority 2.

Definition at line 817 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM0_Pri4

#define AMLI_RAMPRI_AAR_RAM0_Pri4 (0x4UL)

Priority 4.

Definition at line 818 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM0_Pri6

#define AMLI_RAMPRI_AAR_RAM0_Pri6 (0x6UL)

Priority 6.

Definition at line 819 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM0_Pri8

#define AMLI_RAMPRI_AAR_RAM0_Pri8 (0x8UL)

Priority 8.

Definition at line 820 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM1_Msk

#define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos)

Bit mask of RAM1 field.

Definition at line 803 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM1_Pos

#define AMLI_RAMPRI_AAR_RAM1_Pos (4UL)

Position of RAM1 field.

Definition at line 802 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM1_Pri0

#define AMLI_RAMPRI_AAR_RAM1_Pri0 (0x0UL)

Priority 0.

Definition at line 804 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM1_Pri10

#define AMLI_RAMPRI_AAR_RAM1_Pri10 (0xAUL)

Priority 10.

Definition at line 809 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM1_Pri12

#define AMLI_RAMPRI_AAR_RAM1_Pri12 (0xCUL)

Priority 12.

Definition at line 810 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM1_Pri14

#define AMLI_RAMPRI_AAR_RAM1_Pri14 (0xEUL)

Priority 14.

Definition at line 811 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM1_Pri2

#define AMLI_RAMPRI_AAR_RAM1_Pri2 (0x2UL)

Priority 2.

Definition at line 805 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM1_Pri4

#define AMLI_RAMPRI_AAR_RAM1_Pri4 (0x4UL)

Priority 4.

Definition at line 806 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM1_Pri6

#define AMLI_RAMPRI_AAR_RAM1_Pri6 (0x6UL)

Priority 6.

Definition at line 807 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM1_Pri8

#define AMLI_RAMPRI_AAR_RAM1_Pri8 (0x8UL)

Priority 8.

Definition at line 808 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM2_Msk

#define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos)

Bit mask of RAM2 field.

Definition at line 791 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM2_Pos

#define AMLI_RAMPRI_AAR_RAM2_Pos (8UL)

Position of RAM2 field.

Definition at line 790 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM2_Pri0

#define AMLI_RAMPRI_AAR_RAM2_Pri0 (0x0UL)

Priority 0.

Definition at line 792 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM2_Pri10

#define AMLI_RAMPRI_AAR_RAM2_Pri10 (0xAUL)

Priority 10.

Definition at line 797 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM2_Pri12

#define AMLI_RAMPRI_AAR_RAM2_Pri12 (0xCUL)

Priority 12.

Definition at line 798 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM2_Pri14

#define AMLI_RAMPRI_AAR_RAM2_Pri14 (0xEUL)

Priority 14.

Definition at line 799 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM2_Pri2

#define AMLI_RAMPRI_AAR_RAM2_Pri2 (0x2UL)

Priority 2.

Definition at line 793 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM2_Pri4

#define AMLI_RAMPRI_AAR_RAM2_Pri4 (0x4UL)

Priority 4.

Definition at line 794 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM2_Pri6

#define AMLI_RAMPRI_AAR_RAM2_Pri6 (0x6UL)

Priority 6.

Definition at line 795 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM2_Pri8

#define AMLI_RAMPRI_AAR_RAM2_Pri8 (0x8UL)

Priority 8.

Definition at line 796 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM3_Msk

#define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos)

Bit mask of RAM3 field.

Definition at line 779 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM3_Pos

#define AMLI_RAMPRI_AAR_RAM3_Pos (12UL)

Position of RAM3 field.

Definition at line 778 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM3_Pri0

#define AMLI_RAMPRI_AAR_RAM3_Pri0 (0x0UL)

Priority 0.

Definition at line 780 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM3_Pri10

#define AMLI_RAMPRI_AAR_RAM3_Pri10 (0xAUL)

Priority 10.

Definition at line 785 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM3_Pri12

#define AMLI_RAMPRI_AAR_RAM3_Pri12 (0xCUL)

Priority 12.

Definition at line 786 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM3_Pri14

#define AMLI_RAMPRI_AAR_RAM3_Pri14 (0xEUL)

Priority 14.

Definition at line 787 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM3_Pri2

#define AMLI_RAMPRI_AAR_RAM3_Pri2 (0x2UL)

Priority 2.

Definition at line 781 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM3_Pri4

#define AMLI_RAMPRI_AAR_RAM3_Pri4 (0x4UL)

Priority 4.

Definition at line 782 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM3_Pri6

#define AMLI_RAMPRI_AAR_RAM3_Pri6 (0x6UL)

Priority 6.

Definition at line 783 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM3_Pri8

#define AMLI_RAMPRI_AAR_RAM3_Pri8 (0x8UL)

Priority 8.

Definition at line 784 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM4_Msk

#define AMLI_RAMPRI_AAR_RAM4_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM4_Pos)

Bit mask of RAM4 field.

Definition at line 767 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM4_Pos

#define AMLI_RAMPRI_AAR_RAM4_Pos (16UL)

Position of RAM4 field.

Definition at line 766 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM4_Pri0

#define AMLI_RAMPRI_AAR_RAM4_Pri0 (0x0UL)

Priority 0.

Definition at line 768 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM4_Pri10

#define AMLI_RAMPRI_AAR_RAM4_Pri10 (0xAUL)

Priority 10.

Definition at line 773 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM4_Pri12

#define AMLI_RAMPRI_AAR_RAM4_Pri12 (0xCUL)

Priority 12.

Definition at line 774 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM4_Pri14

#define AMLI_RAMPRI_AAR_RAM4_Pri14 (0xEUL)

Priority 14.

Definition at line 775 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM4_Pri2

#define AMLI_RAMPRI_AAR_RAM4_Pri2 (0x2UL)

Priority 2.

Definition at line 769 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM4_Pri4

#define AMLI_RAMPRI_AAR_RAM4_Pri4 (0x4UL)

Priority 4.

Definition at line 770 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM4_Pri6

#define AMLI_RAMPRI_AAR_RAM4_Pri6 (0x6UL)

Priority 6.

Definition at line 771 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM4_Pri8

#define AMLI_RAMPRI_AAR_RAM4_Pri8 (0x8UL)

Priority 8.

Definition at line 772 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM5_Msk

#define AMLI_RAMPRI_AAR_RAM5_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM5_Pos)

Bit mask of RAM5 field.

Definition at line 755 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM5_Pos

#define AMLI_RAMPRI_AAR_RAM5_Pos (20UL)

Position of RAM5 field.

Definition at line 754 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM5_Pri0

#define AMLI_RAMPRI_AAR_RAM5_Pri0 (0x0UL)

Priority 0.

Definition at line 756 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM5_Pri10

#define AMLI_RAMPRI_AAR_RAM5_Pri10 (0xAUL)

Priority 10.

Definition at line 761 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM5_Pri12

#define AMLI_RAMPRI_AAR_RAM5_Pri12 (0xCUL)

Priority 12.

Definition at line 762 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM5_Pri14

#define AMLI_RAMPRI_AAR_RAM5_Pri14 (0xEUL)

Priority 14.

Definition at line 763 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM5_Pri2

#define AMLI_RAMPRI_AAR_RAM5_Pri2 (0x2UL)

Priority 2.

Definition at line 757 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM5_Pri4

#define AMLI_RAMPRI_AAR_RAM5_Pri4 (0x4UL)

Priority 4.

Definition at line 758 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM5_Pri6

#define AMLI_RAMPRI_AAR_RAM5_Pri6 (0x6UL)

Priority 6.

Definition at line 759 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM5_Pri8

#define AMLI_RAMPRI_AAR_RAM5_Pri8 (0x8UL)

Priority 8.

Definition at line 760 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM6_Msk

#define AMLI_RAMPRI_AAR_RAM6_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM6_Pos)

Bit mask of RAM6 field.

Definition at line 743 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM6_Pos

#define AMLI_RAMPRI_AAR_RAM6_Pos (24UL)

Position of RAM6 field.

Definition at line 742 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM6_Pri0

#define AMLI_RAMPRI_AAR_RAM6_Pri0 (0x0UL)

Priority 0.

Definition at line 744 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM6_Pri10

#define AMLI_RAMPRI_AAR_RAM6_Pri10 (0xAUL)

Priority 10.

Definition at line 749 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM6_Pri12

#define AMLI_RAMPRI_AAR_RAM6_Pri12 (0xCUL)

Priority 12.

Definition at line 750 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM6_Pri14

#define AMLI_RAMPRI_AAR_RAM6_Pri14 (0xEUL)

Priority 14.

Definition at line 751 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM6_Pri2

#define AMLI_RAMPRI_AAR_RAM6_Pri2 (0x2UL)

Priority 2.

Definition at line 745 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM6_Pri4

#define AMLI_RAMPRI_AAR_RAM6_Pri4 (0x4UL)

Priority 4.

Definition at line 746 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM6_Pri6

#define AMLI_RAMPRI_AAR_RAM6_Pri6 (0x6UL)

Priority 6.

Definition at line 747 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM6_Pri8

#define AMLI_RAMPRI_AAR_RAM6_Pri8 (0x8UL)

Priority 8.

Definition at line 748 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM7_Msk

#define AMLI_RAMPRI_AAR_RAM7_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM7_Pos)

Bit mask of RAM7 field.

Definition at line 731 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM7_Pos

#define AMLI_RAMPRI_AAR_RAM7_Pos (28UL)

Position of RAM7 field.

Definition at line 730 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM7_Pri0

#define AMLI_RAMPRI_AAR_RAM7_Pri0 (0x0UL)

Priority 0.

Definition at line 732 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM7_Pri10

#define AMLI_RAMPRI_AAR_RAM7_Pri10 (0xAUL)

Priority 10.

Definition at line 737 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM7_Pri12

#define AMLI_RAMPRI_AAR_RAM7_Pri12 (0xCUL)

Priority 12.

Definition at line 738 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM7_Pri14

#define AMLI_RAMPRI_AAR_RAM7_Pri14 (0xEUL)

Priority 14.

Definition at line 739 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM7_Pri2

#define AMLI_RAMPRI_AAR_RAM7_Pri2 (0x2UL)

Priority 2.

Definition at line 733 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM7_Pri4

#define AMLI_RAMPRI_AAR_RAM7_Pri4 (0x4UL)

Priority 4.

Definition at line 734 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM7_Pri6

#define AMLI_RAMPRI_AAR_RAM7_Pri6 (0x6UL)

Priority 6.

Definition at line 735 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_AAR_RAM7_Pri8

#define AMLI_RAMPRI_AAR_RAM7_Pri8 (0x8UL)

Priority 8.

Definition at line 736 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM0_Msk

#define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos)

Bit mask of RAM0 field.

Definition at line 716 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM0_Pos

#define AMLI_RAMPRI_CCM_RAM0_Pos (0UL)

Position of RAM0 field.

Definition at line 715 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM0_Pri0

#define AMLI_RAMPRI_CCM_RAM0_Pri0 (0x0UL)

Priority 0.

Definition at line 717 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM0_Pri10

#define AMLI_RAMPRI_CCM_RAM0_Pri10 (0xAUL)

Priority 10.

Definition at line 722 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM0_Pri12

#define AMLI_RAMPRI_CCM_RAM0_Pri12 (0xCUL)

Priority 12.

Definition at line 723 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM0_Pri14

#define AMLI_RAMPRI_CCM_RAM0_Pri14 (0xEUL)

Priority 14.

Definition at line 724 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM0_Pri2

#define AMLI_RAMPRI_CCM_RAM0_Pri2 (0x2UL)

Priority 2.

Definition at line 718 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM0_Pri4

#define AMLI_RAMPRI_CCM_RAM0_Pri4 (0x4UL)

Priority 4.

Definition at line 719 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM0_Pri6

#define AMLI_RAMPRI_CCM_RAM0_Pri6 (0x6UL)

Priority 6.

Definition at line 720 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM0_Pri8

#define AMLI_RAMPRI_CCM_RAM0_Pri8 (0x8UL)

Priority 8.

Definition at line 721 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM1_Msk

#define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos)

Bit mask of RAM1 field.

Definition at line 704 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM1_Pos

#define AMLI_RAMPRI_CCM_RAM1_Pos (4UL)

Position of RAM1 field.

Definition at line 703 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM1_Pri0

#define AMLI_RAMPRI_CCM_RAM1_Pri0 (0x0UL)

Priority 0.

Definition at line 705 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM1_Pri10

#define AMLI_RAMPRI_CCM_RAM1_Pri10 (0xAUL)

Priority 10.

Definition at line 710 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM1_Pri12

#define AMLI_RAMPRI_CCM_RAM1_Pri12 (0xCUL)

Priority 12.

Definition at line 711 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM1_Pri14

#define AMLI_RAMPRI_CCM_RAM1_Pri14 (0xEUL)

Priority 14.

Definition at line 712 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM1_Pri2

#define AMLI_RAMPRI_CCM_RAM1_Pri2 (0x2UL)

Priority 2.

Definition at line 706 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM1_Pri4

#define AMLI_RAMPRI_CCM_RAM1_Pri4 (0x4UL)

Priority 4.

Definition at line 707 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM1_Pri6

#define AMLI_RAMPRI_CCM_RAM1_Pri6 (0x6UL)

Priority 6.

Definition at line 708 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM1_Pri8

#define AMLI_RAMPRI_CCM_RAM1_Pri8 (0x8UL)

Priority 8.

Definition at line 709 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM2_Msk

#define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos)

Bit mask of RAM2 field.

Definition at line 692 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM2_Pos

#define AMLI_RAMPRI_CCM_RAM2_Pos (8UL)

Position of RAM2 field.

Definition at line 691 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM2_Pri0

#define AMLI_RAMPRI_CCM_RAM2_Pri0 (0x0UL)

Priority 0.

Definition at line 693 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM2_Pri10

#define AMLI_RAMPRI_CCM_RAM2_Pri10 (0xAUL)

Priority 10.

Definition at line 698 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM2_Pri12

#define AMLI_RAMPRI_CCM_RAM2_Pri12 (0xCUL)

Priority 12.

Definition at line 699 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM2_Pri14

#define AMLI_RAMPRI_CCM_RAM2_Pri14 (0xEUL)

Priority 14.

Definition at line 700 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM2_Pri2

#define AMLI_RAMPRI_CCM_RAM2_Pri2 (0x2UL)

Priority 2.

Definition at line 694 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM2_Pri4

#define AMLI_RAMPRI_CCM_RAM2_Pri4 (0x4UL)

Priority 4.

Definition at line 695 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM2_Pri6

#define AMLI_RAMPRI_CCM_RAM2_Pri6 (0x6UL)

Priority 6.

Definition at line 696 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM2_Pri8

#define AMLI_RAMPRI_CCM_RAM2_Pri8 (0x8UL)

Priority 8.

Definition at line 697 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM3_Msk

#define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos)

Bit mask of RAM3 field.

Definition at line 680 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM3_Pos

#define AMLI_RAMPRI_CCM_RAM3_Pos (12UL)

Position of RAM3 field.

Definition at line 679 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM3_Pri0

#define AMLI_RAMPRI_CCM_RAM3_Pri0 (0x0UL)

Priority 0.

Definition at line 681 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM3_Pri10

#define AMLI_RAMPRI_CCM_RAM3_Pri10 (0xAUL)

Priority 10.

Definition at line 686 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM3_Pri12

#define AMLI_RAMPRI_CCM_RAM3_Pri12 (0xCUL)

Priority 12.

Definition at line 687 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM3_Pri14

#define AMLI_RAMPRI_CCM_RAM3_Pri14 (0xEUL)

Priority 14.

Definition at line 688 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM3_Pri2

#define AMLI_RAMPRI_CCM_RAM3_Pri2 (0x2UL)

Priority 2.

Definition at line 682 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM3_Pri4

#define AMLI_RAMPRI_CCM_RAM3_Pri4 (0x4UL)

Priority 4.

Definition at line 683 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM3_Pri6

#define AMLI_RAMPRI_CCM_RAM3_Pri6 (0x6UL)

Priority 6.

Definition at line 684 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM3_Pri8

#define AMLI_RAMPRI_CCM_RAM3_Pri8 (0x8UL)

Priority 8.

Definition at line 685 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM4_Msk

#define AMLI_RAMPRI_CCM_RAM4_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM4_Pos)

Bit mask of RAM4 field.

Definition at line 668 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM4_Pos

#define AMLI_RAMPRI_CCM_RAM4_Pos (16UL)

Position of RAM4 field.

Definition at line 667 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM4_Pri0

#define AMLI_RAMPRI_CCM_RAM4_Pri0 (0x0UL)

Priority 0.

Definition at line 669 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM4_Pri10

#define AMLI_RAMPRI_CCM_RAM4_Pri10 (0xAUL)

Priority 10.

Definition at line 674 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM4_Pri12

#define AMLI_RAMPRI_CCM_RAM4_Pri12 (0xCUL)

Priority 12.

Definition at line 675 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM4_Pri14

#define AMLI_RAMPRI_CCM_RAM4_Pri14 (0xEUL)

Priority 14.

Definition at line 676 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM4_Pri2

#define AMLI_RAMPRI_CCM_RAM4_Pri2 (0x2UL)

Priority 2.

Definition at line 670 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM4_Pri4

#define AMLI_RAMPRI_CCM_RAM4_Pri4 (0x4UL)

Priority 4.

Definition at line 671 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM4_Pri6

#define AMLI_RAMPRI_CCM_RAM4_Pri6 (0x6UL)

Priority 6.

Definition at line 672 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM4_Pri8

#define AMLI_RAMPRI_CCM_RAM4_Pri8 (0x8UL)

Priority 8.

Definition at line 673 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM5_Msk

#define AMLI_RAMPRI_CCM_RAM5_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM5_Pos)

Bit mask of RAM5 field.

Definition at line 656 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM5_Pos

#define AMLI_RAMPRI_CCM_RAM5_Pos (20UL)

Position of RAM5 field.

Definition at line 655 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM5_Pri0

#define AMLI_RAMPRI_CCM_RAM5_Pri0 (0x0UL)

Priority 0.

Definition at line 657 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM5_Pri10

#define AMLI_RAMPRI_CCM_RAM5_Pri10 (0xAUL)

Priority 10.

Definition at line 662 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM5_Pri12

#define AMLI_RAMPRI_CCM_RAM5_Pri12 (0xCUL)

Priority 12.

Definition at line 663 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM5_Pri14

#define AMLI_RAMPRI_CCM_RAM5_Pri14 (0xEUL)

Priority 14.

Definition at line 664 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM5_Pri2

#define AMLI_RAMPRI_CCM_RAM5_Pri2 (0x2UL)

Priority 2.

Definition at line 658 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM5_Pri4

#define AMLI_RAMPRI_CCM_RAM5_Pri4 (0x4UL)

Priority 4.

Definition at line 659 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM5_Pri6

#define AMLI_RAMPRI_CCM_RAM5_Pri6 (0x6UL)

Priority 6.

Definition at line 660 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM5_Pri8

#define AMLI_RAMPRI_CCM_RAM5_Pri8 (0x8UL)

Priority 8.

Definition at line 661 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM6_Msk

#define AMLI_RAMPRI_CCM_RAM6_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM6_Pos)

Bit mask of RAM6 field.

Definition at line 644 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM6_Pos

#define AMLI_RAMPRI_CCM_RAM6_Pos (24UL)

Position of RAM6 field.

Definition at line 643 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM6_Pri0

#define AMLI_RAMPRI_CCM_RAM6_Pri0 (0x0UL)

Priority 0.

Definition at line 645 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM6_Pri10

#define AMLI_RAMPRI_CCM_RAM6_Pri10 (0xAUL)

Priority 10.

Definition at line 650 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM6_Pri12

#define AMLI_RAMPRI_CCM_RAM6_Pri12 (0xCUL)

Priority 12.

Definition at line 651 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM6_Pri14

#define AMLI_RAMPRI_CCM_RAM6_Pri14 (0xEUL)

Priority 14.

Definition at line 652 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM6_Pri2

#define AMLI_RAMPRI_CCM_RAM6_Pri2 (0x2UL)

Priority 2.

Definition at line 646 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM6_Pri4

#define AMLI_RAMPRI_CCM_RAM6_Pri4 (0x4UL)

Priority 4.

Definition at line 647 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM6_Pri6

#define AMLI_RAMPRI_CCM_RAM6_Pri6 (0x6UL)

Priority 6.

Definition at line 648 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM6_Pri8

#define AMLI_RAMPRI_CCM_RAM6_Pri8 (0x8UL)

Priority 8.

Definition at line 649 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM7_Msk

#define AMLI_RAMPRI_CCM_RAM7_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM7_Pos)

Bit mask of RAM7 field.

Definition at line 632 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM7_Pos

#define AMLI_RAMPRI_CCM_RAM7_Pos (28UL)

Position of RAM7 field.

Definition at line 631 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM7_Pri0

#define AMLI_RAMPRI_CCM_RAM7_Pri0 (0x0UL)

Priority 0.

Definition at line 633 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM7_Pri10

#define AMLI_RAMPRI_CCM_RAM7_Pri10 (0xAUL)

Priority 10.

Definition at line 638 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM7_Pri12

#define AMLI_RAMPRI_CCM_RAM7_Pri12 (0xCUL)

Priority 12.

Definition at line 639 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM7_Pri14

#define AMLI_RAMPRI_CCM_RAM7_Pri14 (0xEUL)

Priority 14.

Definition at line 640 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM7_Pri2

#define AMLI_RAMPRI_CCM_RAM7_Pri2 (0x2UL)

Priority 2.

Definition at line 634 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM7_Pri4

#define AMLI_RAMPRI_CCM_RAM7_Pri4 (0x4UL)

Priority 4.

Definition at line 635 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM7_Pri6

#define AMLI_RAMPRI_CCM_RAM7_Pri6 (0x6UL)

Priority 6.

Definition at line 636 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CCM_RAM7_Pri8

#define AMLI_RAMPRI_CCM_RAM7_Pri8 (0x8UL)

Priority 8.

Definition at line 637 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM0_Msk

#define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos)

Bit mask of RAM0 field.

Definition at line 320 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM0_Pos

#define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL)

Position of RAM0 field.

Definition at line 319 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM0_Pri0

#define AMLI_RAMPRI_CPU0_RAM0_Pri0 (0x0UL)

Priority 0.

Definition at line 321 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM0_Pri10

#define AMLI_RAMPRI_CPU0_RAM0_Pri10 (0xAUL)

Priority 10.

Definition at line 326 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM0_Pri12

#define AMLI_RAMPRI_CPU0_RAM0_Pri12 (0xCUL)

Priority 12.

Definition at line 327 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM0_Pri14

#define AMLI_RAMPRI_CPU0_RAM0_Pri14 (0xEUL)

Priority 14.

Definition at line 328 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM0_Pri2

#define AMLI_RAMPRI_CPU0_RAM0_Pri2 (0x2UL)

Priority 2.

Definition at line 322 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM0_Pri4

#define AMLI_RAMPRI_CPU0_RAM0_Pri4 (0x4UL)

Priority 4.

Definition at line 323 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM0_Pri6

#define AMLI_RAMPRI_CPU0_RAM0_Pri6 (0x6UL)

Priority 6.

Definition at line 324 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM0_Pri8

#define AMLI_RAMPRI_CPU0_RAM0_Pri8 (0x8UL)

Priority 8.

Definition at line 325 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM1_Msk

#define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos)

Bit mask of RAM1 field.

Definition at line 308 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM1_Pos

#define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL)

Position of RAM1 field.

Definition at line 307 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM1_Pri0

#define AMLI_RAMPRI_CPU0_RAM1_Pri0 (0x0UL)

Priority 0.

Definition at line 309 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM1_Pri10

#define AMLI_RAMPRI_CPU0_RAM1_Pri10 (0xAUL)

Priority 10.

Definition at line 314 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM1_Pri12

#define AMLI_RAMPRI_CPU0_RAM1_Pri12 (0xCUL)

Priority 12.

Definition at line 315 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM1_Pri14

#define AMLI_RAMPRI_CPU0_RAM1_Pri14 (0xEUL)

Priority 14.

Definition at line 316 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM1_Pri2

#define AMLI_RAMPRI_CPU0_RAM1_Pri2 (0x2UL)

Priority 2.

Definition at line 310 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM1_Pri4

#define AMLI_RAMPRI_CPU0_RAM1_Pri4 (0x4UL)

Priority 4.

Definition at line 311 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM1_Pri6

#define AMLI_RAMPRI_CPU0_RAM1_Pri6 (0x6UL)

Priority 6.

Definition at line 312 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM1_Pri8

#define AMLI_RAMPRI_CPU0_RAM1_Pri8 (0x8UL)

Priority 8.

Definition at line 313 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM2_Msk

#define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos)

Bit mask of RAM2 field.

Definition at line 296 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM2_Pos

#define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL)

Position of RAM2 field.

Definition at line 295 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM2_Pri0

#define AMLI_RAMPRI_CPU0_RAM2_Pri0 (0x0UL)

Priority 0.

Definition at line 297 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM2_Pri10

#define AMLI_RAMPRI_CPU0_RAM2_Pri10 (0xAUL)

Priority 10.

Definition at line 302 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM2_Pri12

#define AMLI_RAMPRI_CPU0_RAM2_Pri12 (0xCUL)

Priority 12.

Definition at line 303 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM2_Pri14

#define AMLI_RAMPRI_CPU0_RAM2_Pri14 (0xEUL)

Priority 14.

Definition at line 304 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM2_Pri2

#define AMLI_RAMPRI_CPU0_RAM2_Pri2 (0x2UL)

Priority 2.

Definition at line 298 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM2_Pri4

#define AMLI_RAMPRI_CPU0_RAM2_Pri4 (0x4UL)

Priority 4.

Definition at line 299 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM2_Pri6

#define AMLI_RAMPRI_CPU0_RAM2_Pri6 (0x6UL)

Priority 6.

Definition at line 300 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM2_Pri8

#define AMLI_RAMPRI_CPU0_RAM2_Pri8 (0x8UL)

Priority 8.

Definition at line 301 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM3_Msk

#define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos)

Bit mask of RAM3 field.

Definition at line 284 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM3_Pos

#define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL)

Position of RAM3 field.

Definition at line 283 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM3_Pri0

#define AMLI_RAMPRI_CPU0_RAM3_Pri0 (0x0UL)

Priority 0.

Definition at line 285 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM3_Pri10

#define AMLI_RAMPRI_CPU0_RAM3_Pri10 (0xAUL)

Priority 10.

Definition at line 290 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM3_Pri12

#define AMLI_RAMPRI_CPU0_RAM3_Pri12 (0xCUL)

Priority 12.

Definition at line 291 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM3_Pri14

#define AMLI_RAMPRI_CPU0_RAM3_Pri14 (0xEUL)

Priority 14.

Definition at line 292 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM3_Pri2

#define AMLI_RAMPRI_CPU0_RAM3_Pri2 (0x2UL)

Priority 2.

Definition at line 286 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM3_Pri4

#define AMLI_RAMPRI_CPU0_RAM3_Pri4 (0x4UL)

Priority 4.

Definition at line 287 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM3_Pri6

#define AMLI_RAMPRI_CPU0_RAM3_Pri6 (0x6UL)

Priority 6.

Definition at line 288 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM3_Pri8

#define AMLI_RAMPRI_CPU0_RAM3_Pri8 (0x8UL)

Priority 8.

Definition at line 289 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM4_Msk

#define AMLI_RAMPRI_CPU0_RAM4_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM4_Pos)

Bit mask of RAM4 field.

Definition at line 272 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM4_Pos

#define AMLI_RAMPRI_CPU0_RAM4_Pos (16UL)

Position of RAM4 field.

Definition at line 271 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM4_Pri0

#define AMLI_RAMPRI_CPU0_RAM4_Pri0 (0x0UL)

Priority 0.

Definition at line 273 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM4_Pri10

#define AMLI_RAMPRI_CPU0_RAM4_Pri10 (0xAUL)

Priority 10.

Definition at line 278 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM4_Pri12

#define AMLI_RAMPRI_CPU0_RAM4_Pri12 (0xCUL)

Priority 12.

Definition at line 279 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM4_Pri14

#define AMLI_RAMPRI_CPU0_RAM4_Pri14 (0xEUL)

Priority 14.

Definition at line 280 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM4_Pri2

#define AMLI_RAMPRI_CPU0_RAM4_Pri2 (0x2UL)

Priority 2.

Definition at line 274 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM4_Pri4

#define AMLI_RAMPRI_CPU0_RAM4_Pri4 (0x4UL)

Priority 4.

Definition at line 275 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM4_Pri6

#define AMLI_RAMPRI_CPU0_RAM4_Pri6 (0x6UL)

Priority 6.

Definition at line 276 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM4_Pri8

#define AMLI_RAMPRI_CPU0_RAM4_Pri8 (0x8UL)

Priority 8.

Definition at line 277 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM5_Msk

#define AMLI_RAMPRI_CPU0_RAM5_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM5_Pos)

Bit mask of RAM5 field.

Definition at line 260 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM5_Pos

#define AMLI_RAMPRI_CPU0_RAM5_Pos (20UL)

Position of RAM5 field.

Definition at line 259 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM5_Pri0

#define AMLI_RAMPRI_CPU0_RAM5_Pri0 (0x0UL)

Priority 0.

Definition at line 261 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM5_Pri10

#define AMLI_RAMPRI_CPU0_RAM5_Pri10 (0xAUL)

Priority 10.

Definition at line 266 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM5_Pri12

#define AMLI_RAMPRI_CPU0_RAM5_Pri12 (0xCUL)

Priority 12.

Definition at line 267 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM5_Pri14

#define AMLI_RAMPRI_CPU0_RAM5_Pri14 (0xEUL)

Priority 14.

Definition at line 268 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM5_Pri2

#define AMLI_RAMPRI_CPU0_RAM5_Pri2 (0x2UL)

Priority 2.

Definition at line 262 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM5_Pri4

#define AMLI_RAMPRI_CPU0_RAM5_Pri4 (0x4UL)

Priority 4.

Definition at line 263 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM5_Pri6

#define AMLI_RAMPRI_CPU0_RAM5_Pri6 (0x6UL)

Priority 6.

Definition at line 264 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM5_Pri8

#define AMLI_RAMPRI_CPU0_RAM5_Pri8 (0x8UL)

Priority 8.

Definition at line 265 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM6_Msk

#define AMLI_RAMPRI_CPU0_RAM6_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM6_Pos)

Bit mask of RAM6 field.

Definition at line 248 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM6_Pos

#define AMLI_RAMPRI_CPU0_RAM6_Pos (24UL)

Position of RAM6 field.

Definition at line 247 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM6_Pri0

#define AMLI_RAMPRI_CPU0_RAM6_Pri0 (0x0UL)

Priority 0.

Definition at line 249 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM6_Pri10

#define AMLI_RAMPRI_CPU0_RAM6_Pri10 (0xAUL)

Priority 10.

Definition at line 254 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM6_Pri12

#define AMLI_RAMPRI_CPU0_RAM6_Pri12 (0xCUL)

Priority 12.

Definition at line 255 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM6_Pri14

#define AMLI_RAMPRI_CPU0_RAM6_Pri14 (0xEUL)

Priority 14.

Definition at line 256 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM6_Pri2

#define AMLI_RAMPRI_CPU0_RAM6_Pri2 (0x2UL)

Priority 2.

Definition at line 250 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM6_Pri4

#define AMLI_RAMPRI_CPU0_RAM6_Pri4 (0x4UL)

Priority 4.

Definition at line 251 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM6_Pri6

#define AMLI_RAMPRI_CPU0_RAM6_Pri6 (0x6UL)

Priority 6.

Definition at line 252 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM6_Pri8

#define AMLI_RAMPRI_CPU0_RAM6_Pri8 (0x8UL)

Priority 8.

Definition at line 253 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM7_Msk

#define AMLI_RAMPRI_CPU0_RAM7_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM7_Pos)

Bit mask of RAM7 field.

Definition at line 236 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM7_Pos

#define AMLI_RAMPRI_CPU0_RAM7_Pos (28UL)

Position of RAM7 field.

Definition at line 235 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM7_Pri0

#define AMLI_RAMPRI_CPU0_RAM7_Pri0 (0x0UL)

Priority 0.

Definition at line 237 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM7_Pri10

#define AMLI_RAMPRI_CPU0_RAM7_Pri10 (0xAUL)

Priority 10.

Definition at line 242 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM7_Pri12

#define AMLI_RAMPRI_CPU0_RAM7_Pri12 (0xCUL)

Priority 12.

Definition at line 243 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM7_Pri14

#define AMLI_RAMPRI_CPU0_RAM7_Pri14 (0xEUL)

Priority 14.

Definition at line 244 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM7_Pri2

#define AMLI_RAMPRI_CPU0_RAM7_Pri2 (0x2UL)

Priority 2.

Definition at line 238 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM7_Pri4

#define AMLI_RAMPRI_CPU0_RAM7_Pri4 (0x4UL)

Priority 4.

Definition at line 239 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM7_Pri6

#define AMLI_RAMPRI_CPU0_RAM7_Pri6 (0x6UL)

Priority 6.

Definition at line 240 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_CPU0_RAM7_Pri8

#define AMLI_RAMPRI_CPU0_RAM7_Pri8 (0x8UL)

Priority 8.

Definition at line 241 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM0_Msk

#define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos)

Bit mask of RAM0 field.

Definition at line 617 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM0_Pos

#define AMLI_RAMPRI_ECB_RAM0_Pos (0UL)

Position of RAM0 field.

Definition at line 616 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM0_Pri0

#define AMLI_RAMPRI_ECB_RAM0_Pri0 (0x0UL)

Priority 0.

Definition at line 618 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM0_Pri10

#define AMLI_RAMPRI_ECB_RAM0_Pri10 (0xAUL)

Priority 10.

Definition at line 623 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM0_Pri12

#define AMLI_RAMPRI_ECB_RAM0_Pri12 (0xCUL)

Priority 12.

Definition at line 624 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM0_Pri14

#define AMLI_RAMPRI_ECB_RAM0_Pri14 (0xEUL)

Priority 14.

Definition at line 625 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM0_Pri2

#define AMLI_RAMPRI_ECB_RAM0_Pri2 (0x2UL)

Priority 2.

Definition at line 619 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM0_Pri4

#define AMLI_RAMPRI_ECB_RAM0_Pri4 (0x4UL)

Priority 4.

Definition at line 620 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM0_Pri6

#define AMLI_RAMPRI_ECB_RAM0_Pri6 (0x6UL)

Priority 6.

Definition at line 621 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM0_Pri8

#define AMLI_RAMPRI_ECB_RAM0_Pri8 (0x8UL)

Priority 8.

Definition at line 622 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM1_Msk

#define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos)

Bit mask of RAM1 field.

Definition at line 605 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM1_Pos

#define AMLI_RAMPRI_ECB_RAM1_Pos (4UL)

Position of RAM1 field.

Definition at line 604 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM1_Pri0

#define AMLI_RAMPRI_ECB_RAM1_Pri0 (0x0UL)

Priority 0.

Definition at line 606 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM1_Pri10

#define AMLI_RAMPRI_ECB_RAM1_Pri10 (0xAUL)

Priority 10.

Definition at line 611 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM1_Pri12

#define AMLI_RAMPRI_ECB_RAM1_Pri12 (0xCUL)

Priority 12.

Definition at line 612 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM1_Pri14

#define AMLI_RAMPRI_ECB_RAM1_Pri14 (0xEUL)

Priority 14.

Definition at line 613 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM1_Pri2

#define AMLI_RAMPRI_ECB_RAM1_Pri2 (0x2UL)

Priority 2.

Definition at line 607 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM1_Pri4

#define AMLI_RAMPRI_ECB_RAM1_Pri4 (0x4UL)

Priority 4.

Definition at line 608 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM1_Pri6

#define AMLI_RAMPRI_ECB_RAM1_Pri6 (0x6UL)

Priority 6.

Definition at line 609 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM1_Pri8

#define AMLI_RAMPRI_ECB_RAM1_Pri8 (0x8UL)

Priority 8.

Definition at line 610 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM2_Msk

#define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos)

Bit mask of RAM2 field.

Definition at line 593 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM2_Pos

#define AMLI_RAMPRI_ECB_RAM2_Pos (8UL)

Position of RAM2 field.

Definition at line 592 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM2_Pri0

#define AMLI_RAMPRI_ECB_RAM2_Pri0 (0x0UL)

Priority 0.

Definition at line 594 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM2_Pri10

#define AMLI_RAMPRI_ECB_RAM2_Pri10 (0xAUL)

Priority 10.

Definition at line 599 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM2_Pri12

#define AMLI_RAMPRI_ECB_RAM2_Pri12 (0xCUL)

Priority 12.

Definition at line 600 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM2_Pri14

#define AMLI_RAMPRI_ECB_RAM2_Pri14 (0xEUL)

Priority 14.

Definition at line 601 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM2_Pri2

#define AMLI_RAMPRI_ECB_RAM2_Pri2 (0x2UL)

Priority 2.

Definition at line 595 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM2_Pri4

#define AMLI_RAMPRI_ECB_RAM2_Pri4 (0x4UL)

Priority 4.

Definition at line 596 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM2_Pri6

#define AMLI_RAMPRI_ECB_RAM2_Pri6 (0x6UL)

Priority 6.

Definition at line 597 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM2_Pri8

#define AMLI_RAMPRI_ECB_RAM2_Pri8 (0x8UL)

Priority 8.

Definition at line 598 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM3_Msk

#define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos)

Bit mask of RAM3 field.

Definition at line 581 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM3_Pos

#define AMLI_RAMPRI_ECB_RAM3_Pos (12UL)

Position of RAM3 field.

Definition at line 580 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM3_Pri0

#define AMLI_RAMPRI_ECB_RAM3_Pri0 (0x0UL)

Priority 0.

Definition at line 582 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM3_Pri10

#define AMLI_RAMPRI_ECB_RAM3_Pri10 (0xAUL)

Priority 10.

Definition at line 587 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM3_Pri12

#define AMLI_RAMPRI_ECB_RAM3_Pri12 (0xCUL)

Priority 12.

Definition at line 588 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM3_Pri14

#define AMLI_RAMPRI_ECB_RAM3_Pri14 (0xEUL)

Priority 14.

Definition at line 589 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM3_Pri2

#define AMLI_RAMPRI_ECB_RAM3_Pri2 (0x2UL)

Priority 2.

Definition at line 583 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM3_Pri4

#define AMLI_RAMPRI_ECB_RAM3_Pri4 (0x4UL)

Priority 4.

Definition at line 584 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM3_Pri6

#define AMLI_RAMPRI_ECB_RAM3_Pri6 (0x6UL)

Priority 6.

Definition at line 585 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM3_Pri8

#define AMLI_RAMPRI_ECB_RAM3_Pri8 (0x8UL)

Priority 8.

Definition at line 586 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM4_Msk

#define AMLI_RAMPRI_ECB_RAM4_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM4_Pos)

Bit mask of RAM4 field.

Definition at line 569 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM4_Pos

#define AMLI_RAMPRI_ECB_RAM4_Pos (16UL)

Position of RAM4 field.

Definition at line 568 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM4_Pri0

#define AMLI_RAMPRI_ECB_RAM4_Pri0 (0x0UL)

Priority 0.

Definition at line 570 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM4_Pri10

#define AMLI_RAMPRI_ECB_RAM4_Pri10 (0xAUL)

Priority 10.

Definition at line 575 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM4_Pri12

#define AMLI_RAMPRI_ECB_RAM4_Pri12 (0xCUL)

Priority 12.

Definition at line 576 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM4_Pri14

#define AMLI_RAMPRI_ECB_RAM4_Pri14 (0xEUL)

Priority 14.

Definition at line 577 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM4_Pri2

#define AMLI_RAMPRI_ECB_RAM4_Pri2 (0x2UL)

Priority 2.

Definition at line 571 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM4_Pri4

#define AMLI_RAMPRI_ECB_RAM4_Pri4 (0x4UL)

Priority 4.

Definition at line 572 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM4_Pri6

#define AMLI_RAMPRI_ECB_RAM4_Pri6 (0x6UL)

Priority 6.

Definition at line 573 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM4_Pri8

#define AMLI_RAMPRI_ECB_RAM4_Pri8 (0x8UL)

Priority 8.

Definition at line 574 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM5_Msk

#define AMLI_RAMPRI_ECB_RAM5_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM5_Pos)

Bit mask of RAM5 field.

Definition at line 557 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM5_Pos

#define AMLI_RAMPRI_ECB_RAM5_Pos (20UL)

Position of RAM5 field.

Definition at line 556 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM5_Pri0

#define AMLI_RAMPRI_ECB_RAM5_Pri0 (0x0UL)

Priority 0.

Definition at line 558 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM5_Pri10

#define AMLI_RAMPRI_ECB_RAM5_Pri10 (0xAUL)

Priority 10.

Definition at line 563 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM5_Pri12

#define AMLI_RAMPRI_ECB_RAM5_Pri12 (0xCUL)

Priority 12.

Definition at line 564 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM5_Pri14

#define AMLI_RAMPRI_ECB_RAM5_Pri14 (0xEUL)

Priority 14.

Definition at line 565 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM5_Pri2

#define AMLI_RAMPRI_ECB_RAM5_Pri2 (0x2UL)

Priority 2.

Definition at line 559 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM5_Pri4

#define AMLI_RAMPRI_ECB_RAM5_Pri4 (0x4UL)

Priority 4.

Definition at line 560 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM5_Pri6

#define AMLI_RAMPRI_ECB_RAM5_Pri6 (0x6UL)

Priority 6.

Definition at line 561 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM5_Pri8

#define AMLI_RAMPRI_ECB_RAM5_Pri8 (0x8UL)

Priority 8.

Definition at line 562 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM6_Msk

#define AMLI_RAMPRI_ECB_RAM6_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM6_Pos)

Bit mask of RAM6 field.

Definition at line 545 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM6_Pos

#define AMLI_RAMPRI_ECB_RAM6_Pos (24UL)

Position of RAM6 field.

Definition at line 544 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM6_Pri0

#define AMLI_RAMPRI_ECB_RAM6_Pri0 (0x0UL)

Priority 0.

Definition at line 546 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM6_Pri10

#define AMLI_RAMPRI_ECB_RAM6_Pri10 (0xAUL)

Priority 10.

Definition at line 551 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM6_Pri12

#define AMLI_RAMPRI_ECB_RAM6_Pri12 (0xCUL)

Priority 12.

Definition at line 552 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM6_Pri14

#define AMLI_RAMPRI_ECB_RAM6_Pri14 (0xEUL)

Priority 14.

Definition at line 553 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM6_Pri2

#define AMLI_RAMPRI_ECB_RAM6_Pri2 (0x2UL)

Priority 2.

Definition at line 547 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM6_Pri4

#define AMLI_RAMPRI_ECB_RAM6_Pri4 (0x4UL)

Priority 4.

Definition at line 548 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM6_Pri6

#define AMLI_RAMPRI_ECB_RAM6_Pri6 (0x6UL)

Priority 6.

Definition at line 549 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM6_Pri8

#define AMLI_RAMPRI_ECB_RAM6_Pri8 (0x8UL)

Priority 8.

Definition at line 550 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM7_Msk

#define AMLI_RAMPRI_ECB_RAM7_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM7_Pos)

Bit mask of RAM7 field.

Definition at line 533 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM7_Pos

#define AMLI_RAMPRI_ECB_RAM7_Pos (28UL)

Position of RAM7 field.

Definition at line 532 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM7_Pri0

#define AMLI_RAMPRI_ECB_RAM7_Pri0 (0x0UL)

Priority 0.

Definition at line 534 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM7_Pri10

#define AMLI_RAMPRI_ECB_RAM7_Pri10 (0xAUL)

Priority 10.

Definition at line 539 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM7_Pri12

#define AMLI_RAMPRI_ECB_RAM7_Pri12 (0xCUL)

Priority 12.

Definition at line 540 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM7_Pri14

#define AMLI_RAMPRI_ECB_RAM7_Pri14 (0xEUL)

Priority 14.

Definition at line 541 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM7_Pri2

#define AMLI_RAMPRI_ECB_RAM7_Pri2 (0x2UL)

Priority 2.

Definition at line 535 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM7_Pri4

#define AMLI_RAMPRI_ECB_RAM7_Pri4 (0x4UL)

Priority 4.

Definition at line 536 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM7_Pri6

#define AMLI_RAMPRI_ECB_RAM7_Pri6 (0x6UL)

Priority 6.

Definition at line 537 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_ECB_RAM7_Pri8

#define AMLI_RAMPRI_ECB_RAM7_Pri8 (0x8UL)

Priority 8.

Definition at line 538 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM0_Msk

#define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos)

Bit mask of RAM0 field.

Definition at line 518 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM0_Pos

#define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL)

Position of RAM0 field.

Definition at line 517 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM0_Pri0

#define AMLI_RAMPRI_RADIO_RAM0_Pri0 (0x0UL)

Priority 0.

Definition at line 519 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM0_Pri10

#define AMLI_RAMPRI_RADIO_RAM0_Pri10 (0xAUL)

Priority 10.

Definition at line 524 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM0_Pri12

#define AMLI_RAMPRI_RADIO_RAM0_Pri12 (0xCUL)

Priority 12.

Definition at line 525 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM0_Pri14

#define AMLI_RAMPRI_RADIO_RAM0_Pri14 (0xEUL)

Priority 14.

Definition at line 526 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM0_Pri2

#define AMLI_RAMPRI_RADIO_RAM0_Pri2 (0x2UL)

Priority 2.

Definition at line 520 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM0_Pri4

#define AMLI_RAMPRI_RADIO_RAM0_Pri4 (0x4UL)

Priority 4.

Definition at line 521 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM0_Pri6

#define AMLI_RAMPRI_RADIO_RAM0_Pri6 (0x6UL)

Priority 6.

Definition at line 522 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM0_Pri8

#define AMLI_RAMPRI_RADIO_RAM0_Pri8 (0x8UL)

Priority 8.

Definition at line 523 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM1_Msk

#define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos)

Bit mask of RAM1 field.

Definition at line 506 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM1_Pos

#define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL)

Position of RAM1 field.

Definition at line 505 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM1_Pri0

#define AMLI_RAMPRI_RADIO_RAM1_Pri0 (0x0UL)

Priority 0.

Definition at line 507 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM1_Pri10

#define AMLI_RAMPRI_RADIO_RAM1_Pri10 (0xAUL)

Priority 10.

Definition at line 512 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM1_Pri12

#define AMLI_RAMPRI_RADIO_RAM1_Pri12 (0xCUL)

Priority 12.

Definition at line 513 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM1_Pri14

#define AMLI_RAMPRI_RADIO_RAM1_Pri14 (0xEUL)

Priority 14.

Definition at line 514 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM1_Pri2

#define AMLI_RAMPRI_RADIO_RAM1_Pri2 (0x2UL)

Priority 2.

Definition at line 508 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM1_Pri4

#define AMLI_RAMPRI_RADIO_RAM1_Pri4 (0x4UL)

Priority 4.

Definition at line 509 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM1_Pri6

#define AMLI_RAMPRI_RADIO_RAM1_Pri6 (0x6UL)

Priority 6.

Definition at line 510 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM1_Pri8

#define AMLI_RAMPRI_RADIO_RAM1_Pri8 (0x8UL)

Priority 8.

Definition at line 511 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM2_Msk

#define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos)

Bit mask of RAM2 field.

Definition at line 494 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM2_Pos

#define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL)

Position of RAM2 field.

Definition at line 493 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM2_Pri0

#define AMLI_RAMPRI_RADIO_RAM2_Pri0 (0x0UL)

Priority 0.

Definition at line 495 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM2_Pri10

#define AMLI_RAMPRI_RADIO_RAM2_Pri10 (0xAUL)

Priority 10.

Definition at line 500 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM2_Pri12

#define AMLI_RAMPRI_RADIO_RAM2_Pri12 (0xCUL)

Priority 12.

Definition at line 501 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM2_Pri14

#define AMLI_RAMPRI_RADIO_RAM2_Pri14 (0xEUL)

Priority 14.

Definition at line 502 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM2_Pri2

#define AMLI_RAMPRI_RADIO_RAM2_Pri2 (0x2UL)

Priority 2.

Definition at line 496 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM2_Pri4

#define AMLI_RAMPRI_RADIO_RAM2_Pri4 (0x4UL)

Priority 4.

Definition at line 497 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM2_Pri6

#define AMLI_RAMPRI_RADIO_RAM2_Pri6 (0x6UL)

Priority 6.

Definition at line 498 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM2_Pri8

#define AMLI_RAMPRI_RADIO_RAM2_Pri8 (0x8UL)

Priority 8.

Definition at line 499 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM3_Msk

#define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos)

Bit mask of RAM3 field.

Definition at line 482 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM3_Pos

#define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL)

Position of RAM3 field.

Definition at line 481 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM3_Pri0

#define AMLI_RAMPRI_RADIO_RAM3_Pri0 (0x0UL)

Priority 0.

Definition at line 483 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM3_Pri10

#define AMLI_RAMPRI_RADIO_RAM3_Pri10 (0xAUL)

Priority 10.

Definition at line 488 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM3_Pri12

#define AMLI_RAMPRI_RADIO_RAM3_Pri12 (0xCUL)

Priority 12.

Definition at line 489 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM3_Pri14

#define AMLI_RAMPRI_RADIO_RAM3_Pri14 (0xEUL)

Priority 14.

Definition at line 490 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM3_Pri2

#define AMLI_RAMPRI_RADIO_RAM3_Pri2 (0x2UL)

Priority 2.

Definition at line 484 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM3_Pri4

#define AMLI_RAMPRI_RADIO_RAM3_Pri4 (0x4UL)

Priority 4.

Definition at line 485 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM3_Pri6

#define AMLI_RAMPRI_RADIO_RAM3_Pri6 (0x6UL)

Priority 6.

Definition at line 486 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM3_Pri8

#define AMLI_RAMPRI_RADIO_RAM3_Pri8 (0x8UL)

Priority 8.

Definition at line 487 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM4_Msk

#define AMLI_RAMPRI_RADIO_RAM4_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM4_Pos)

Bit mask of RAM4 field.

Definition at line 470 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM4_Pos

#define AMLI_RAMPRI_RADIO_RAM4_Pos (16UL)

Position of RAM4 field.

Definition at line 469 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM4_Pri0

#define AMLI_RAMPRI_RADIO_RAM4_Pri0 (0x0UL)

Priority 0.

Definition at line 471 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM4_Pri10

#define AMLI_RAMPRI_RADIO_RAM4_Pri10 (0xAUL)

Priority 10.

Definition at line 476 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM4_Pri12

#define AMLI_RAMPRI_RADIO_RAM4_Pri12 (0xCUL)

Priority 12.

Definition at line 477 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM4_Pri14

#define AMLI_RAMPRI_RADIO_RAM4_Pri14 (0xEUL)

Priority 14.

Definition at line 478 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM4_Pri2

#define AMLI_RAMPRI_RADIO_RAM4_Pri2 (0x2UL)

Priority 2.

Definition at line 472 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM4_Pri4

#define AMLI_RAMPRI_RADIO_RAM4_Pri4 (0x4UL)

Priority 4.

Definition at line 473 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM4_Pri6

#define AMLI_RAMPRI_RADIO_RAM4_Pri6 (0x6UL)

Priority 6.

Definition at line 474 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM4_Pri8

#define AMLI_RAMPRI_RADIO_RAM4_Pri8 (0x8UL)

Priority 8.

Definition at line 475 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM5_Msk

#define AMLI_RAMPRI_RADIO_RAM5_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM5_Pos)

Bit mask of RAM5 field.

Definition at line 458 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM5_Pos

#define AMLI_RAMPRI_RADIO_RAM5_Pos (20UL)

Position of RAM5 field.

Definition at line 457 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM5_Pri0

#define AMLI_RAMPRI_RADIO_RAM5_Pri0 (0x0UL)

Priority 0.

Definition at line 459 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM5_Pri10

#define AMLI_RAMPRI_RADIO_RAM5_Pri10 (0xAUL)

Priority 10.

Definition at line 464 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM5_Pri12

#define AMLI_RAMPRI_RADIO_RAM5_Pri12 (0xCUL)

Priority 12.

Definition at line 465 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM5_Pri14

#define AMLI_RAMPRI_RADIO_RAM5_Pri14 (0xEUL)

Priority 14.

Definition at line 466 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM5_Pri2

#define AMLI_RAMPRI_RADIO_RAM5_Pri2 (0x2UL)

Priority 2.

Definition at line 460 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM5_Pri4

#define AMLI_RAMPRI_RADIO_RAM5_Pri4 (0x4UL)

Priority 4.

Definition at line 461 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM5_Pri6

#define AMLI_RAMPRI_RADIO_RAM5_Pri6 (0x6UL)

Priority 6.

Definition at line 462 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM5_Pri8

#define AMLI_RAMPRI_RADIO_RAM5_Pri8 (0x8UL)

Priority 8.

Definition at line 463 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM6_Msk

#define AMLI_RAMPRI_RADIO_RAM6_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM6_Pos)

Bit mask of RAM6 field.

Definition at line 446 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM6_Pos

#define AMLI_RAMPRI_RADIO_RAM6_Pos (24UL)

Position of RAM6 field.

Definition at line 445 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM6_Pri0

#define AMLI_RAMPRI_RADIO_RAM6_Pri0 (0x0UL)

Priority 0.

Definition at line 447 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM6_Pri10

#define AMLI_RAMPRI_RADIO_RAM6_Pri10 (0xAUL)

Priority 10.

Definition at line 452 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM6_Pri12

#define AMLI_RAMPRI_RADIO_RAM6_Pri12 (0xCUL)

Priority 12.

Definition at line 453 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM6_Pri14

#define AMLI_RAMPRI_RADIO_RAM6_Pri14 (0xEUL)

Priority 14.

Definition at line 454 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM6_Pri2

#define AMLI_RAMPRI_RADIO_RAM6_Pri2 (0x2UL)

Priority 2.

Definition at line 448 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM6_Pri4

#define AMLI_RAMPRI_RADIO_RAM6_Pri4 (0x4UL)

Priority 4.

Definition at line 449 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM6_Pri6

#define AMLI_RAMPRI_RADIO_RAM6_Pri6 (0x6UL)

Priority 6.

Definition at line 450 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM6_Pri8

#define AMLI_RAMPRI_RADIO_RAM6_Pri8 (0x8UL)

Priority 8.

Definition at line 451 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM7_Msk

#define AMLI_RAMPRI_RADIO_RAM7_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM7_Pos)

Bit mask of RAM7 field.

Definition at line 434 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM7_Pos

#define AMLI_RAMPRI_RADIO_RAM7_Pos (28UL)

Position of RAM7 field.

Definition at line 433 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM7_Pri0

#define AMLI_RAMPRI_RADIO_RAM7_Pri0 (0x0UL)

Priority 0.

Definition at line 435 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM7_Pri10

#define AMLI_RAMPRI_RADIO_RAM7_Pri10 (0xAUL)

Priority 10.

Definition at line 440 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM7_Pri12

#define AMLI_RAMPRI_RADIO_RAM7_Pri12 (0xCUL)

Priority 12.

Definition at line 441 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM7_Pri14

#define AMLI_RAMPRI_RADIO_RAM7_Pri14 (0xEUL)

Priority 14.

Definition at line 442 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM7_Pri2

#define AMLI_RAMPRI_RADIO_RAM7_Pri2 (0x2UL)

Priority 2.

Definition at line 436 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM7_Pri4

#define AMLI_RAMPRI_RADIO_RAM7_Pri4 (0x4UL)

Priority 4.

Definition at line 437 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM7_Pri6

#define AMLI_RAMPRI_RADIO_RAM7_Pri6 (0x6UL)

Priority 6.

Definition at line 438 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_RADIO_RAM7_Pri8

#define AMLI_RAMPRI_RADIO_RAM7_Pri8 (0x8UL)

Priority 8.

Definition at line 439 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM0_Msk

#define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos)

Bit mask of RAM0 field.

Definition at line 419 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM0_Pos

#define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL)

Position of RAM0 field.

Definition at line 418 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM0_Pri0

#define AMLI_RAMPRI_SPIS1_RAM0_Pri0 (0x0UL)

Priority 0.

Definition at line 420 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM0_Pri10

#define AMLI_RAMPRI_SPIS1_RAM0_Pri10 (0xAUL)

Priority 10.

Definition at line 425 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM0_Pri12

#define AMLI_RAMPRI_SPIS1_RAM0_Pri12 (0xCUL)

Priority 12.

Definition at line 426 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM0_Pri14

#define AMLI_RAMPRI_SPIS1_RAM0_Pri14 (0xEUL)

Priority 14.

Definition at line 427 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM0_Pri2

#define AMLI_RAMPRI_SPIS1_RAM0_Pri2 (0x2UL)

Priority 2.

Definition at line 421 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM0_Pri4

#define AMLI_RAMPRI_SPIS1_RAM0_Pri4 (0x4UL)

Priority 4.

Definition at line 422 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM0_Pri6

#define AMLI_RAMPRI_SPIS1_RAM0_Pri6 (0x6UL)

Priority 6.

Definition at line 423 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM0_Pri8

#define AMLI_RAMPRI_SPIS1_RAM0_Pri8 (0x8UL)

Priority 8.

Definition at line 424 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM1_Msk

#define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos)

Bit mask of RAM1 field.

Definition at line 407 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM1_Pos

#define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL)

Position of RAM1 field.

Definition at line 406 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM1_Pri0

#define AMLI_RAMPRI_SPIS1_RAM1_Pri0 (0x0UL)

Priority 0.

Definition at line 408 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM1_Pri10

#define AMLI_RAMPRI_SPIS1_RAM1_Pri10 (0xAUL)

Priority 10.

Definition at line 413 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM1_Pri12

#define AMLI_RAMPRI_SPIS1_RAM1_Pri12 (0xCUL)

Priority 12.

Definition at line 414 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM1_Pri14

#define AMLI_RAMPRI_SPIS1_RAM1_Pri14 (0xEUL)

Priority 14.

Definition at line 415 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM1_Pri2

#define AMLI_RAMPRI_SPIS1_RAM1_Pri2 (0x2UL)

Priority 2.

Definition at line 409 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM1_Pri4

#define AMLI_RAMPRI_SPIS1_RAM1_Pri4 (0x4UL)

Priority 4.

Definition at line 410 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM1_Pri6

#define AMLI_RAMPRI_SPIS1_RAM1_Pri6 (0x6UL)

Priority 6.

Definition at line 411 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM1_Pri8

#define AMLI_RAMPRI_SPIS1_RAM1_Pri8 (0x8UL)

Priority 8.

Definition at line 412 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM2_Msk

#define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos)

Bit mask of RAM2 field.

Definition at line 395 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM2_Pos

#define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL)

Position of RAM2 field.

Definition at line 394 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM2_Pri0

#define AMLI_RAMPRI_SPIS1_RAM2_Pri0 (0x0UL)

Priority 0.

Definition at line 396 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM2_Pri10

#define AMLI_RAMPRI_SPIS1_RAM2_Pri10 (0xAUL)

Priority 10.

Definition at line 401 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM2_Pri12

#define AMLI_RAMPRI_SPIS1_RAM2_Pri12 (0xCUL)

Priority 12.

Definition at line 402 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM2_Pri14

#define AMLI_RAMPRI_SPIS1_RAM2_Pri14 (0xEUL)

Priority 14.

Definition at line 403 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM2_Pri2

#define AMLI_RAMPRI_SPIS1_RAM2_Pri2 (0x2UL)

Priority 2.

Definition at line 397 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM2_Pri4

#define AMLI_RAMPRI_SPIS1_RAM2_Pri4 (0x4UL)

Priority 4.

Definition at line 398 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM2_Pri6

#define AMLI_RAMPRI_SPIS1_RAM2_Pri6 (0x6UL)

Priority 6.

Definition at line 399 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM2_Pri8

#define AMLI_RAMPRI_SPIS1_RAM2_Pri8 (0x8UL)

Priority 8.

Definition at line 400 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM3_Msk

#define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos)

Bit mask of RAM3 field.

Definition at line 383 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM3_Pos

#define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL)

Position of RAM3 field.

Definition at line 382 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM3_Pri0

#define AMLI_RAMPRI_SPIS1_RAM3_Pri0 (0x0UL)

Priority 0.

Definition at line 384 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM3_Pri10

#define AMLI_RAMPRI_SPIS1_RAM3_Pri10 (0xAUL)

Priority 10.

Definition at line 389 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM3_Pri12

#define AMLI_RAMPRI_SPIS1_RAM3_Pri12 (0xCUL)

Priority 12.

Definition at line 390 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM3_Pri14

#define AMLI_RAMPRI_SPIS1_RAM3_Pri14 (0xEUL)

Priority 14.

Definition at line 391 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM3_Pri2

#define AMLI_RAMPRI_SPIS1_RAM3_Pri2 (0x2UL)

Priority 2.

Definition at line 385 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM3_Pri4

#define AMLI_RAMPRI_SPIS1_RAM3_Pri4 (0x4UL)

Priority 4.

Definition at line 386 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM3_Pri6

#define AMLI_RAMPRI_SPIS1_RAM3_Pri6 (0x6UL)

Priority 6.

Definition at line 387 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM3_Pri8

#define AMLI_RAMPRI_SPIS1_RAM3_Pri8 (0x8UL)

Priority 8.

Definition at line 388 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM4_Msk

#define AMLI_RAMPRI_SPIS1_RAM4_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM4_Pos)

Bit mask of RAM4 field.

Definition at line 371 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM4_Pos

#define AMLI_RAMPRI_SPIS1_RAM4_Pos (16UL)

Position of RAM4 field.

Definition at line 370 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM4_Pri0

#define AMLI_RAMPRI_SPIS1_RAM4_Pri0 (0x0UL)

Priority 0.

Definition at line 372 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM4_Pri10

#define AMLI_RAMPRI_SPIS1_RAM4_Pri10 (0xAUL)

Priority 10.

Definition at line 377 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM4_Pri12

#define AMLI_RAMPRI_SPIS1_RAM4_Pri12 (0xCUL)

Priority 12.

Definition at line 378 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM4_Pri14

#define AMLI_RAMPRI_SPIS1_RAM4_Pri14 (0xEUL)

Priority 14.

Definition at line 379 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM4_Pri2

#define AMLI_RAMPRI_SPIS1_RAM4_Pri2 (0x2UL)

Priority 2.

Definition at line 373 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM4_Pri4

#define AMLI_RAMPRI_SPIS1_RAM4_Pri4 (0x4UL)

Priority 4.

Definition at line 374 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM4_Pri6

#define AMLI_RAMPRI_SPIS1_RAM4_Pri6 (0x6UL)

Priority 6.

Definition at line 375 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM4_Pri8

#define AMLI_RAMPRI_SPIS1_RAM4_Pri8 (0x8UL)

Priority 8.

Definition at line 376 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM5_Msk

#define AMLI_RAMPRI_SPIS1_RAM5_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM5_Pos)

Bit mask of RAM5 field.

Definition at line 359 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM5_Pos

#define AMLI_RAMPRI_SPIS1_RAM5_Pos (20UL)

Position of RAM5 field.

Definition at line 358 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM5_Pri0

#define AMLI_RAMPRI_SPIS1_RAM5_Pri0 (0x0UL)

Priority 0.

Definition at line 360 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM5_Pri10

#define AMLI_RAMPRI_SPIS1_RAM5_Pri10 (0xAUL)

Priority 10.

Definition at line 365 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM5_Pri12

#define AMLI_RAMPRI_SPIS1_RAM5_Pri12 (0xCUL)

Priority 12.

Definition at line 366 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM5_Pri14

#define AMLI_RAMPRI_SPIS1_RAM5_Pri14 (0xEUL)

Priority 14.

Definition at line 367 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM5_Pri2

#define AMLI_RAMPRI_SPIS1_RAM5_Pri2 (0x2UL)

Priority 2.

Definition at line 361 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM5_Pri4

#define AMLI_RAMPRI_SPIS1_RAM5_Pri4 (0x4UL)

Priority 4.

Definition at line 362 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM5_Pri6

#define AMLI_RAMPRI_SPIS1_RAM5_Pri6 (0x6UL)

Priority 6.

Definition at line 363 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM5_Pri8

#define AMLI_RAMPRI_SPIS1_RAM5_Pri8 (0x8UL)

Priority 8.

Definition at line 364 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM6_Msk

#define AMLI_RAMPRI_SPIS1_RAM6_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM6_Pos)

Bit mask of RAM6 field.

Definition at line 347 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM6_Pos

#define AMLI_RAMPRI_SPIS1_RAM6_Pos (24UL)

Position of RAM6 field.

Definition at line 346 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM6_Pri0

#define AMLI_RAMPRI_SPIS1_RAM6_Pri0 (0x0UL)

Priority 0.

Definition at line 348 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM6_Pri10

#define AMLI_RAMPRI_SPIS1_RAM6_Pri10 (0xAUL)

Priority 10.

Definition at line 353 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM6_Pri12

#define AMLI_RAMPRI_SPIS1_RAM6_Pri12 (0xCUL)

Priority 12.

Definition at line 354 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM6_Pri14

#define AMLI_RAMPRI_SPIS1_RAM6_Pri14 (0xEUL)

Priority 14.

Definition at line 355 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM6_Pri2

#define AMLI_RAMPRI_SPIS1_RAM6_Pri2 (0x2UL)

Priority 2.

Definition at line 349 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM6_Pri4

#define AMLI_RAMPRI_SPIS1_RAM6_Pri4 (0x4UL)

Priority 4.

Definition at line 350 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM6_Pri6

#define AMLI_RAMPRI_SPIS1_RAM6_Pri6 (0x6UL)

Priority 6.

Definition at line 351 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM6_Pri8

#define AMLI_RAMPRI_SPIS1_RAM6_Pri8 (0x8UL)

Priority 8.

Definition at line 352 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM7_Msk

#define AMLI_RAMPRI_SPIS1_RAM7_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM7_Pos)

Bit mask of RAM7 field.

Definition at line 335 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM7_Pos

#define AMLI_RAMPRI_SPIS1_RAM7_Pos (28UL)

Position of RAM7 field.

Definition at line 334 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM7_Pri0

#define AMLI_RAMPRI_SPIS1_RAM7_Pri0 (0x0UL)

Priority 0.

Definition at line 336 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM7_Pri10

#define AMLI_RAMPRI_SPIS1_RAM7_Pri10 (0xAUL)

Priority 10.

Definition at line 341 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM7_Pri12

#define AMLI_RAMPRI_SPIS1_RAM7_Pri12 (0xCUL)

Priority 12.

Definition at line 342 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM7_Pri14

#define AMLI_RAMPRI_SPIS1_RAM7_Pri14 (0xEUL)

Priority 14.

Definition at line 343 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM7_Pri2

#define AMLI_RAMPRI_SPIS1_RAM7_Pri2 (0x2UL)

Priority 2.

Definition at line 337 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM7_Pri4

#define AMLI_RAMPRI_SPIS1_RAM7_Pri4 (0x4UL)

Priority 4.

Definition at line 338 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM7_Pri6

#define AMLI_RAMPRI_SPIS1_RAM7_Pri6 (0x6UL)

Priority 6.

Definition at line 339 of file nrf51_bitfields.h.

◆ AMLI_RAMPRI_SPIS1_RAM7_Pri8

#define AMLI_RAMPRI_SPIS1_RAM7_Pri8 (0x8UL)

Priority 8.

Definition at line 340 of file nrf51_bitfields.h.

◆ CCM_ENABLE_ENABLE_Disabled

#define CCM_ENABLE_ENABLE_Disabled (0x00UL)

CCM is disabled.

Definition at line 901 of file nrf51_bitfields.h.

◆ CCM_ENABLE_ENABLE_Enabled

#define CCM_ENABLE_ENABLE_Enabled (0x02UL)

CCM is enabled.

Definition at line 902 of file nrf51_bitfields.h.

◆ CCM_ENABLE_ENABLE_Msk

#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos)

Bit mask of ENABLE field.

Definition at line 900 of file nrf51_bitfields.h.

◆ CCM_ENABLE_ENABLE_Pos

#define CCM_ENABLE_ENABLE_Pos (0UL)

Position of ENABLE field.

Definition at line 899 of file nrf51_bitfields.h.

◆ CCM_INTENCLR_ENDCRYPT_Clear

#define CCM_INTENCLR_ENDCRYPT_Clear (1UL)

Disable interrupt on write.

Definition at line 877 of file nrf51_bitfields.h.

◆ CCM_INTENCLR_ENDCRYPT_Disabled

#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL)

Interrupt disabled.

Definition at line 875 of file nrf51_bitfields.h.

◆ CCM_INTENCLR_ENDCRYPT_Enabled

#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL)

Interrupt enabled.

Definition at line 876 of file nrf51_bitfields.h.

◆ CCM_INTENCLR_ENDCRYPT_Msk

#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos)

Bit mask of ENDCRYPT field.

Definition at line 874 of file nrf51_bitfields.h.

◆ CCM_INTENCLR_ENDCRYPT_Pos

#define CCM_INTENCLR_ENDCRYPT_Pos (1UL)

Position of ENDCRYPT field.

Definition at line 873 of file nrf51_bitfields.h.

◆ CCM_INTENCLR_ENDKSGEN_Clear

#define CCM_INTENCLR_ENDKSGEN_Clear (1UL)

Disable interrupt on write.

Definition at line 884 of file nrf51_bitfields.h.

◆ CCM_INTENCLR_ENDKSGEN_Disabled

#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL)

Interrupt disabled.

Definition at line 882 of file nrf51_bitfields.h.

◆ CCM_INTENCLR_ENDKSGEN_Enabled

#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL)

Interrupt enabled.

Definition at line 883 of file nrf51_bitfields.h.

◆ CCM_INTENCLR_ENDKSGEN_Msk

#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos)

Bit mask of ENDKSGEN field.

Definition at line 881 of file nrf51_bitfields.h.

◆ CCM_INTENCLR_ENDKSGEN_Pos

#define CCM_INTENCLR_ENDKSGEN_Pos (0UL)

Position of ENDKSGEN field.

Definition at line 880 of file nrf51_bitfields.h.

◆ CCM_INTENCLR_ERROR_Clear

#define CCM_INTENCLR_ERROR_Clear (1UL)

Disable interrupt on write.

Definition at line 870 of file nrf51_bitfields.h.

◆ CCM_INTENCLR_ERROR_Disabled

#define CCM_INTENCLR_ERROR_Disabled (0UL)

Interrupt disabled.

Definition at line 868 of file nrf51_bitfields.h.

◆ CCM_INTENCLR_ERROR_Enabled

#define CCM_INTENCLR_ERROR_Enabled (1UL)

Interrupt enabled.

Definition at line 869 of file nrf51_bitfields.h.

◆ CCM_INTENCLR_ERROR_Msk

#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos)

Bit mask of ERROR field.

Definition at line 867 of file nrf51_bitfields.h.

◆ CCM_INTENCLR_ERROR_Pos

#define CCM_INTENCLR_ERROR_Pos (2UL)

Position of ERROR field.

Definition at line 866 of file nrf51_bitfields.h.

◆ CCM_INTENSET_ENDCRYPT_Disabled

#define CCM_INTENSET_ENDCRYPT_Disabled (0UL)

Interrupt disabled.

Definition at line 851 of file nrf51_bitfields.h.

◆ CCM_INTENSET_ENDCRYPT_Enabled

#define CCM_INTENSET_ENDCRYPT_Enabled (1UL)

Interrupt enabled.

Definition at line 852 of file nrf51_bitfields.h.

◆ CCM_INTENSET_ENDCRYPT_Msk

#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos)

Bit mask of ENDCRYPT field.

Definition at line 850 of file nrf51_bitfields.h.

◆ CCM_INTENSET_ENDCRYPT_Pos

#define CCM_INTENSET_ENDCRYPT_Pos (1UL)

Position of ENDCRYPT field.

Definition at line 849 of file nrf51_bitfields.h.

◆ CCM_INTENSET_ENDCRYPT_Set

#define CCM_INTENSET_ENDCRYPT_Set (1UL)

Enable interrupt on write.

Definition at line 853 of file nrf51_bitfields.h.

◆ CCM_INTENSET_ENDKSGEN_Disabled

#define CCM_INTENSET_ENDKSGEN_Disabled (0UL)

Interrupt disabled.

Definition at line 858 of file nrf51_bitfields.h.

◆ CCM_INTENSET_ENDKSGEN_Enabled

#define CCM_INTENSET_ENDKSGEN_Enabled (1UL)

Interrupt enabled.

Definition at line 859 of file nrf51_bitfields.h.

◆ CCM_INTENSET_ENDKSGEN_Msk

#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos)

Bit mask of ENDKSGEN field.

Definition at line 857 of file nrf51_bitfields.h.

◆ CCM_INTENSET_ENDKSGEN_Pos

#define CCM_INTENSET_ENDKSGEN_Pos (0UL)

Position of ENDKSGEN field.

Definition at line 856 of file nrf51_bitfields.h.

◆ CCM_INTENSET_ENDKSGEN_Set

#define CCM_INTENSET_ENDKSGEN_Set (1UL)

Enable interrupt on write.

Definition at line 860 of file nrf51_bitfields.h.

◆ CCM_INTENSET_ERROR_Disabled

#define CCM_INTENSET_ERROR_Disabled (0UL)

Interrupt disabled.

Definition at line 844 of file nrf51_bitfields.h.

◆ CCM_INTENSET_ERROR_Enabled

#define CCM_INTENSET_ERROR_Enabled (1UL)

Interrupt enabled.

Definition at line 845 of file nrf51_bitfields.h.

◆ CCM_INTENSET_ERROR_Msk

#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos)

Bit mask of ERROR field.

Definition at line 843 of file nrf51_bitfields.h.

◆ CCM_INTENSET_ERROR_Pos

#define CCM_INTENSET_ERROR_Pos (2UL)

Position of ERROR field.

Definition at line 842 of file nrf51_bitfields.h.

◆ CCM_INTENSET_ERROR_Set

#define CCM_INTENSET_ERROR_Set (1UL)

Enable interrupt on write.

Definition at line 846 of file nrf51_bitfields.h.

◆ CCM_MICSTATUS_MICSTATUS_CheckFailed

#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL)

MIC check failed.

Definition at line 892 of file nrf51_bitfields.h.

◆ CCM_MICSTATUS_MICSTATUS_CheckPassed

#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL)

MIC check passed.

Definition at line 893 of file nrf51_bitfields.h.

◆ CCM_MICSTATUS_MICSTATUS_Msk

#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos)

Bit mask of MICSTATUS field.

Definition at line 891 of file nrf51_bitfields.h.

◆ CCM_MICSTATUS_MICSTATUS_Pos

#define CCM_MICSTATUS_MICSTATUS_Pos (0UL)

Position of MICSTATUS field.

Definition at line 890 of file nrf51_bitfields.h.

◆ CCM_MODE_MODE_Decryption

#define CCM_MODE_MODE_Decryption (1UL)

CCM mode TX

Definition at line 911 of file nrf51_bitfields.h.

◆ CCM_MODE_MODE_Encryption

#define CCM_MODE_MODE_Encryption (0UL)

CCM mode TX

Definition at line 910 of file nrf51_bitfields.h.

◆ CCM_MODE_MODE_Msk

#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos)

Bit mask of MODE field.

Definition at line 909 of file nrf51_bitfields.h.

◆ CCM_MODE_MODE_Pos

#define CCM_MODE_MODE_Pos (0UL)

Position of MODE field.

Definition at line 908 of file nrf51_bitfields.h.

◆ CCM_POWER_POWER_Disabled

#define CCM_POWER_POWER_Disabled (0UL)

Module power disabled.

Definition at line 919 of file nrf51_bitfields.h.

◆ CCM_POWER_POWER_Enabled

#define CCM_POWER_POWER_Enabled (1UL)

Module power enabled.

Definition at line 920 of file nrf51_bitfields.h.

◆ CCM_POWER_POWER_Msk

#define CCM_POWER_POWER_Msk (0x1UL << CCM_POWER_POWER_Pos)

Bit mask of POWER field.

Definition at line 918 of file nrf51_bitfields.h.

◆ CCM_POWER_POWER_Pos

#define CCM_POWER_POWER_Pos (0UL)

Position of POWER field.

Definition at line 917 of file nrf51_bitfields.h.

◆ CCM_SHORTS_ENDKSGEN_CRYPT_Disabled

#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL)

Shortcut disabled.

Definition at line 835 of file nrf51_bitfields.h.

◆ CCM_SHORTS_ENDKSGEN_CRYPT_Enabled

#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL)

Shortcut enabled.

Definition at line 836 of file nrf51_bitfields.h.

◆ CCM_SHORTS_ENDKSGEN_CRYPT_Msk

#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos)

Bit mask of ENDKSGEN_CRYPT field.

Definition at line 834 of file nrf51_bitfields.h.

◆ CCM_SHORTS_ENDKSGEN_CRYPT_Pos

#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL)

Position of ENDKSGEN_CRYPT field.

Definition at line 833 of file nrf51_bitfields.h.

◆ CLOCK_CTIV_CTIV_Msk

#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos)

Bit mask of CTIV field.

Definition at line 1062 of file nrf51_bitfields.h.

◆ CLOCK_CTIV_CTIV_Pos

#define CLOCK_CTIV_CTIV_Pos (0UL)

Position of CTIV field.

Definition at line 1061 of file nrf51_bitfields.h.

◆ CLOCK_HFCLKRUN_STATUS_Msk

#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos)

Bit mask of STATUS field.

Definition at line 993 of file nrf51_bitfields.h.

◆ CLOCK_HFCLKRUN_STATUS_NotTriggered

#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL)

Task HFCLKSTART has not been triggered.

Definition at line 994 of file nrf51_bitfields.h.

◆ CLOCK_HFCLKRUN_STATUS_Pos

#define CLOCK_HFCLKRUN_STATUS_Pos (0UL)

Position of STATUS field.

Definition at line 992 of file nrf51_bitfields.h.

◆ CLOCK_HFCLKRUN_STATUS_Triggered

#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL)

Task HFCLKSTART has been triggered.

Definition at line 995 of file nrf51_bitfields.h.

◆ CLOCK_HFCLKSTAT_SRC_Msk

#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos)

Bit mask of SRC field.

Definition at line 1008 of file nrf51_bitfields.h.

◆ CLOCK_HFCLKSTAT_SRC_Pos

#define CLOCK_HFCLKSTAT_SRC_Pos (0UL)

Position of SRC field.

Definition at line 1007 of file nrf51_bitfields.h.

◆ CLOCK_HFCLKSTAT_SRC_RC

#define CLOCK_HFCLKSTAT_SRC_RC (0UL)

Internal 16MHz RC oscillator running and generating the HFCLK clock.

Definition at line 1009 of file nrf51_bitfields.h.

◆ CLOCK_HFCLKSTAT_SRC_Xtal

#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL)

External 16MHz/32MHz crystal oscillator running and generating the HFCLK clock.

Definition at line 1010 of file nrf51_bitfields.h.

◆ CLOCK_HFCLKSTAT_STATE_Msk

#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos)

Bit mask of STATE field.

Definition at line 1002 of file nrf51_bitfields.h.

◆ CLOCK_HFCLKSTAT_STATE_NotRunning

#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL)

HFCLK clock not running.

Definition at line 1003 of file nrf51_bitfields.h.

◆ CLOCK_HFCLKSTAT_STATE_Pos

#define CLOCK_HFCLKSTAT_STATE_Pos (16UL)

Position of STATE field.

Definition at line 1001 of file nrf51_bitfields.h.

◆ CLOCK_HFCLKSTAT_STATE_Running

#define CLOCK_HFCLKSTAT_STATE_Running (1UL)

HFCLK clock running.

Definition at line 1004 of file nrf51_bitfields.h.

◆ CLOCK_INTENCLR_CTTO_Clear

#define CLOCK_INTENCLR_CTTO_Clear (1UL)

Disable interrupt on write.

Definition at line 965 of file nrf51_bitfields.h.

◆ CLOCK_INTENCLR_CTTO_Disabled

#define CLOCK_INTENCLR_CTTO_Disabled (0UL)

Interrupt disabled.

Definition at line 963 of file nrf51_bitfields.h.

◆ CLOCK_INTENCLR_CTTO_Enabled

#define CLOCK_INTENCLR_CTTO_Enabled (1UL)

Interrupt enabled.

Definition at line 964 of file nrf51_bitfields.h.

◆ CLOCK_INTENCLR_CTTO_Msk

#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos)

Bit mask of CTTO field.

Definition at line 962 of file nrf51_bitfields.h.

◆ CLOCK_INTENCLR_CTTO_Pos

#define CLOCK_INTENCLR_CTTO_Pos (4UL)

Position of CTTO field.

Definition at line 961 of file nrf51_bitfields.h.

◆ CLOCK_INTENCLR_DONE_Clear

#define CLOCK_INTENCLR_DONE_Clear (1UL)

Disable interrupt on write.

Definition at line 972 of file nrf51_bitfields.h.

◆ CLOCK_INTENCLR_DONE_Disabled

#define CLOCK_INTENCLR_DONE_Disabled (0UL)

Interrupt disabled.

Definition at line 970 of file nrf51_bitfields.h.

◆ CLOCK_INTENCLR_DONE_Enabled

#define CLOCK_INTENCLR_DONE_Enabled (1UL)

Interrupt enabled.

Definition at line 971 of file nrf51_bitfields.h.

◆ CLOCK_INTENCLR_DONE_Msk

#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos)

Bit mask of DONE field.

Definition at line 969 of file nrf51_bitfields.h.

◆ CLOCK_INTENCLR_DONE_Pos

#define CLOCK_INTENCLR_DONE_Pos (3UL)

Position of DONE field.

Definition at line 968 of file nrf51_bitfields.h.

◆ CLOCK_INTENCLR_HFCLKSTARTED_Clear

#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL)

Disable interrupt on write.

Definition at line 986 of file nrf51_bitfields.h.

◆ CLOCK_INTENCLR_HFCLKSTARTED_Disabled

#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL)

Interrupt disabled.

Definition at line 984 of file nrf51_bitfields.h.

◆ CLOCK_INTENCLR_HFCLKSTARTED_Enabled

#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL)

Interrupt enabled.

Definition at line 985 of file nrf51_bitfields.h.

◆ CLOCK_INTENCLR_HFCLKSTARTED_Msk

#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos)

Bit mask of HFCLKSTARTED field.

Definition at line 983 of file nrf51_bitfields.h.

◆ CLOCK_INTENCLR_HFCLKSTARTED_Pos

#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL)

Position of HFCLKSTARTED field.

Definition at line 982 of file nrf51_bitfields.h.

◆ CLOCK_INTENCLR_LFCLKSTARTED_Clear

#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL)

Disable interrupt on write.

Definition at line 979 of file nrf51_bitfields.h.

◆ CLOCK_INTENCLR_LFCLKSTARTED_Disabled

#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL)

Interrupt disabled.

Definition at line 977 of file nrf51_bitfields.h.

◆ CLOCK_INTENCLR_LFCLKSTARTED_Enabled

#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL)

Interrupt enabled.

Definition at line 978 of file nrf51_bitfields.h.

◆ CLOCK_INTENCLR_LFCLKSTARTED_Msk

#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos)

Bit mask of LFCLKSTARTED field.

Definition at line 976 of file nrf51_bitfields.h.

◆ CLOCK_INTENCLR_LFCLKSTARTED_Pos

#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL)

Position of LFCLKSTARTED field.

Definition at line 975 of file nrf51_bitfields.h.

◆ CLOCK_INTENSET_CTTO_Disabled

#define CLOCK_INTENSET_CTTO_Disabled (0UL)

Interrupt disabled.

Definition at line 932 of file nrf51_bitfields.h.

◆ CLOCK_INTENSET_CTTO_Enabled

#define CLOCK_INTENSET_CTTO_Enabled (1UL)

Interrupt enabled.

Definition at line 933 of file nrf51_bitfields.h.

◆ CLOCK_INTENSET_CTTO_Msk

#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos)

Bit mask of CTTO field.

Definition at line 931 of file nrf51_bitfields.h.

◆ CLOCK_INTENSET_CTTO_Pos

#define CLOCK_INTENSET_CTTO_Pos (4UL)

Position of CTTO field.

Definition at line 930 of file nrf51_bitfields.h.

◆ CLOCK_INTENSET_CTTO_Set

#define CLOCK_INTENSET_CTTO_Set (1UL)

Enable interrupt on write.

Definition at line 934 of file nrf51_bitfields.h.

◆ CLOCK_INTENSET_DONE_Disabled

#define CLOCK_INTENSET_DONE_Disabled (0UL)

Interrupt disabled.

Definition at line 939 of file nrf51_bitfields.h.

◆ CLOCK_INTENSET_DONE_Enabled

#define CLOCK_INTENSET_DONE_Enabled (1UL)

Interrupt enabled.

Definition at line 940 of file nrf51_bitfields.h.

◆ CLOCK_INTENSET_DONE_Msk

#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos)

Bit mask of DONE field.

Definition at line 938 of file nrf51_bitfields.h.

◆ CLOCK_INTENSET_DONE_Pos

#define CLOCK_INTENSET_DONE_Pos (3UL)

Position of DONE field.

Definition at line 937 of file nrf51_bitfields.h.

◆ CLOCK_INTENSET_DONE_Set

#define CLOCK_INTENSET_DONE_Set (1UL)

Enable interrupt on write.

Definition at line 941 of file nrf51_bitfields.h.

◆ CLOCK_INTENSET_HFCLKSTARTED_Disabled

#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL)

Interrupt disabled.

Definition at line 953 of file nrf51_bitfields.h.

◆ CLOCK_INTENSET_HFCLKSTARTED_Enabled

#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL)

Interrupt enabled.

Definition at line 954 of file nrf51_bitfields.h.

◆ CLOCK_INTENSET_HFCLKSTARTED_Msk

#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos)

Bit mask of HFCLKSTARTED field.

Definition at line 952 of file nrf51_bitfields.h.

◆ CLOCK_INTENSET_HFCLKSTARTED_Pos

#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL)

Position of HFCLKSTARTED field.

Definition at line 951 of file nrf51_bitfields.h.

◆ CLOCK_INTENSET_HFCLKSTARTED_Set

#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL)

Enable interrupt on write.

Definition at line 955 of file nrf51_bitfields.h.

◆ CLOCK_INTENSET_LFCLKSTARTED_Disabled

#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL)

Interrupt disabled.

Definition at line 946 of file nrf51_bitfields.h.

◆ CLOCK_INTENSET_LFCLKSTARTED_Enabled

#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL)

Interrupt enabled.

Definition at line 947 of file nrf51_bitfields.h.

◆ CLOCK_INTENSET_LFCLKSTARTED_Msk

#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos)

Bit mask of LFCLKSTARTED field.

Definition at line 945 of file nrf51_bitfields.h.

◆ CLOCK_INTENSET_LFCLKSTARTED_Pos

#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL)

Position of LFCLKSTARTED field.

Definition at line 944 of file nrf51_bitfields.h.

◆ CLOCK_INTENSET_LFCLKSTARTED_Set

#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL)

Enable interrupt on write.

Definition at line 948 of file nrf51_bitfields.h.

◆ CLOCK_LFCLKRUN_STATUS_Msk

#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos)

Bit mask of STATUS field.

Definition at line 1017 of file nrf51_bitfields.h.

◆ CLOCK_LFCLKRUN_STATUS_NotTriggered

#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL)

Task LFCLKSTART has not been triggered.

Definition at line 1018 of file nrf51_bitfields.h.

◆ CLOCK_LFCLKRUN_STATUS_Pos

#define CLOCK_LFCLKRUN_STATUS_Pos (0UL)

Position of STATUS field.

Definition at line 1016 of file nrf51_bitfields.h.

◆ CLOCK_LFCLKRUN_STATUS_Triggered

#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL)

Task LFCLKSTART has been triggered.

Definition at line 1019 of file nrf51_bitfields.h.

◆ CLOCK_LFCLKSRC_SRC_Msk

#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos)

Bit mask of SRC field.

Definition at line 1052 of file nrf51_bitfields.h.

◆ CLOCK_LFCLKSRC_SRC_Pos

#define CLOCK_LFCLKSRC_SRC_Pos (0UL)

Position of SRC field.

Definition at line 1051 of file nrf51_bitfields.h.

◆ CLOCK_LFCLKSRC_SRC_RC

#define CLOCK_LFCLKSRC_SRC_RC (0UL)

Internal 32KiHz RC oscillator.

Definition at line 1053 of file nrf51_bitfields.h.

◆ CLOCK_LFCLKSRC_SRC_Synth

#define CLOCK_LFCLKSRC_SRC_Synth (2UL)

Internal 32KiHz synthesizer from HFCLK system clock.

Definition at line 1055 of file nrf51_bitfields.h.

◆ CLOCK_LFCLKSRC_SRC_Xtal

#define CLOCK_LFCLKSRC_SRC_Xtal (1UL)

External 32KiHz crystal.

Definition at line 1054 of file nrf51_bitfields.h.

◆ CLOCK_LFCLKSRCCOPY_SRC_Msk

#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos)

Bit mask of SRC field.

Definition at line 1042 of file nrf51_bitfields.h.

◆ CLOCK_LFCLKSRCCOPY_SRC_Pos

#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL)

Position of SRC field.

Definition at line 1041 of file nrf51_bitfields.h.

◆ CLOCK_LFCLKSRCCOPY_SRC_RC

#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL)

Internal 32KiHz RC oscillator.

Definition at line 1043 of file nrf51_bitfields.h.

◆ CLOCK_LFCLKSRCCOPY_SRC_Synth

#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL)

Internal 32KiHz synthesizer from HFCLK system clock.

Definition at line 1045 of file nrf51_bitfields.h.

◆ CLOCK_LFCLKSRCCOPY_SRC_Xtal

#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL)

External 32KiHz crystal.

Definition at line 1044 of file nrf51_bitfields.h.

◆ CLOCK_LFCLKSTAT_SRC_Msk

#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos)

Bit mask of SRC field.

Definition at line 1032 of file nrf51_bitfields.h.

◆ CLOCK_LFCLKSTAT_SRC_Pos

#define CLOCK_LFCLKSTAT_SRC_Pos (0UL)

Position of SRC field.

Definition at line 1031 of file nrf51_bitfields.h.

◆ CLOCK_LFCLKSTAT_SRC_RC

#define CLOCK_LFCLKSTAT_SRC_RC (0UL)

Internal 32KiHz RC oscillator running and generating the LFCLK clock.

Definition at line 1033 of file nrf51_bitfields.h.

◆ CLOCK_LFCLKSTAT_SRC_Synth

#define CLOCK_LFCLKSTAT_SRC_Synth (2UL)

Internal 32KiHz synthesizer from the HFCLK running and generating the LFCLK clock.

Definition at line 1035 of file nrf51_bitfields.h.

◆ CLOCK_LFCLKSTAT_SRC_Xtal

#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL)

External 32KiHz crystal oscillator running and generating the LFCLK clock.

Definition at line 1034 of file nrf51_bitfields.h.

◆ CLOCK_LFCLKSTAT_STATE_Msk

#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos)

Bit mask of STATE field.

Definition at line 1026 of file nrf51_bitfields.h.

◆ CLOCK_LFCLKSTAT_STATE_NotRunning

#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL)

LFCLK clock not running.

Definition at line 1027 of file nrf51_bitfields.h.

◆ CLOCK_LFCLKSTAT_STATE_Pos

#define CLOCK_LFCLKSTAT_STATE_Pos (16UL)

Position of STATE field.

Definition at line 1025 of file nrf51_bitfields.h.

◆ CLOCK_LFCLKSTAT_STATE_Running

#define CLOCK_LFCLKSTAT_STATE_Running (1UL)

LFCLK clock running.

Definition at line 1028 of file nrf51_bitfields.h.

◆ CLOCK_XTALFREQ_XTALFREQ_16MHz

#define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL)

16MHz xtal is used as source for the HFCLK oscillator.

Definition at line 1071 of file nrf51_bitfields.h.

◆ CLOCK_XTALFREQ_XTALFREQ_32MHz

#define CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL)

32MHz xtal is used as source for the HFCLK oscillator.

Definition at line 1070 of file nrf51_bitfields.h.

◆ CLOCK_XTALFREQ_XTALFREQ_Msk

#define CLOCK_XTALFREQ_XTALFREQ_Msk (0xFFUL << CLOCK_XTALFREQ_XTALFREQ_Pos)

Bit mask of XTALFREQ field.

Definition at line 1069 of file nrf51_bitfields.h.

◆ CLOCK_XTALFREQ_XTALFREQ_Pos

#define CLOCK_XTALFREQ_XTALFREQ_Pos (0UL)

Position of XTALFREQ field.

Definition at line 1068 of file nrf51_bitfields.h.

◆ ECB_INTENCLR_ENDECB_Clear

#define ECB_INTENCLR_ENDECB_Clear (1UL)

Disable interrupt on write.

Definition at line 1109 of file nrf51_bitfields.h.

◆ ECB_INTENCLR_ENDECB_Disabled

#define ECB_INTENCLR_ENDECB_Disabled (0UL)

Interrupt disabled.

Definition at line 1107 of file nrf51_bitfields.h.

◆ ECB_INTENCLR_ENDECB_Enabled

#define ECB_INTENCLR_ENDECB_Enabled (1UL)

Interrupt enabled.

Definition at line 1108 of file nrf51_bitfields.h.

◆ ECB_INTENCLR_ENDECB_Msk

#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos)

Bit mask of ENDECB field.

Definition at line 1106 of file nrf51_bitfields.h.

◆ ECB_INTENCLR_ENDECB_Pos

#define ECB_INTENCLR_ENDECB_Pos (0UL)

Position of ENDECB field.

Definition at line 1105 of file nrf51_bitfields.h.

◆ ECB_INTENCLR_ERRORECB_Clear

#define ECB_INTENCLR_ERRORECB_Clear (1UL)

Disable interrupt on write.

Definition at line 1102 of file nrf51_bitfields.h.

◆ ECB_INTENCLR_ERRORECB_Disabled

#define ECB_INTENCLR_ERRORECB_Disabled (0UL)

Interrupt disabled.

Definition at line 1100 of file nrf51_bitfields.h.

◆ ECB_INTENCLR_ERRORECB_Enabled

#define ECB_INTENCLR_ERRORECB_Enabled (1UL)

Interrupt enabled.

Definition at line 1101 of file nrf51_bitfields.h.

◆ ECB_INTENCLR_ERRORECB_Msk

#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos)

Bit mask of ERRORECB field.

Definition at line 1099 of file nrf51_bitfields.h.

◆ ECB_INTENCLR_ERRORECB_Pos

#define ECB_INTENCLR_ERRORECB_Pos (1UL)

Position of ERRORECB field.

Definition at line 1098 of file nrf51_bitfields.h.

◆ ECB_INTENSET_ENDECB_Disabled

#define ECB_INTENSET_ENDECB_Disabled (0UL)

Interrupt disabled.

Definition at line 1090 of file nrf51_bitfields.h.

◆ ECB_INTENSET_ENDECB_Enabled

#define ECB_INTENSET_ENDECB_Enabled (1UL)

Interrupt enabled.

Definition at line 1091 of file nrf51_bitfields.h.

◆ ECB_INTENSET_ENDECB_Msk

#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos)

Bit mask of ENDECB field.

Definition at line 1089 of file nrf51_bitfields.h.

◆ ECB_INTENSET_ENDECB_Pos

#define ECB_INTENSET_ENDECB_Pos (0UL)

Position of ENDECB field.

Definition at line 1088 of file nrf51_bitfields.h.

◆ ECB_INTENSET_ENDECB_Set

#define ECB_INTENSET_ENDECB_Set (1UL)

Enable interrupt on write.

Definition at line 1092 of file nrf51_bitfields.h.

◆ ECB_INTENSET_ERRORECB_Disabled

#define ECB_INTENSET_ERRORECB_Disabled (0UL)

Interrupt disabled.

Definition at line 1083 of file nrf51_bitfields.h.

◆ ECB_INTENSET_ERRORECB_Enabled

#define ECB_INTENSET_ERRORECB_Enabled (1UL)

Interrupt enabled.

Definition at line 1084 of file nrf51_bitfields.h.

◆ ECB_INTENSET_ERRORECB_Msk

#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos)

Bit mask of ERRORECB field.

Definition at line 1082 of file nrf51_bitfields.h.

◆ ECB_INTENSET_ERRORECB_Pos

#define ECB_INTENSET_ERRORECB_Pos (1UL)

Position of ERRORECB field.

Definition at line 1081 of file nrf51_bitfields.h.

◆ ECB_INTENSET_ERRORECB_Set

#define ECB_INTENSET_ERRORECB_Set (1UL)

Enable interrupt on write.

Definition at line 1085 of file nrf51_bitfields.h.

◆ ECB_POWER_POWER_Disabled

#define ECB_POWER_POWER_Disabled (0UL)

Module power disabled.

Definition at line 1117 of file nrf51_bitfields.h.

◆ ECB_POWER_POWER_Enabled

#define ECB_POWER_POWER_Enabled (1UL)

Module power enabled.

Definition at line 1118 of file nrf51_bitfields.h.

◆ ECB_POWER_POWER_Msk

#define ECB_POWER_POWER_Msk (0x1UL << ECB_POWER_POWER_Pos)

Bit mask of POWER field.

Definition at line 1116 of file nrf51_bitfields.h.

◆ ECB_POWER_POWER_Pos

#define ECB_POWER_POWER_Pos (0UL)

Position of POWER field.

Definition at line 1115 of file nrf51_bitfields.h.

◆ FICR_CONFIGID_FWID_Msk

#define FICR_CONFIGID_FWID_Msk (0xFFFFUL << FICR_CONFIGID_FWID_Pos)

Bit mask of FWID field.

Definition at line 1138 of file nrf51_bitfields.h.

◆ FICR_CONFIGID_FWID_Pos

#define FICR_CONFIGID_FWID_Pos (16UL)

Position of FWID field.

Definition at line 1137 of file nrf51_bitfields.h.

◆ FICR_CONFIGID_HWID_Msk

#define FICR_CONFIGID_HWID_Msk (0xFFFFUL << FICR_CONFIGID_HWID_Pos)

Bit mask of HWID field.

Definition at line 1142 of file nrf51_bitfields.h.

◆ FICR_CONFIGID_HWID_Pos

#define FICR_CONFIGID_HWID_Pos (0UL)

Position of HWID field.

Definition at line 1141 of file nrf51_bitfields.h.

◆ FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk

#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos)

Bit mask of DEVICEADDRTYPE field.

Definition at line 1149 of file nrf51_bitfields.h.

◆ FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos

#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL)

Position of DEVICEADDRTYPE field.

Definition at line 1148 of file nrf51_bitfields.h.

◆ FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public

#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL)

Public address.

Definition at line 1150 of file nrf51_bitfields.h.

◆ FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random

#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL)

Random address.

Definition at line 1151 of file nrf51_bitfields.h.

◆ FICR_OVERRIDEEN_BLE_1MBIT_Msk

#define FICR_OVERRIDEEN_BLE_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_BLE_1MBIT_Pos)

Bit mask of BLE_1MBIT field.

Definition at line 1158 of file nrf51_bitfields.h.

◆ FICR_OVERRIDEEN_BLE_1MBIT_NotOverride

#define FICR_OVERRIDEEN_BLE_1MBIT_NotOverride (1UL)

Do not override the default values for BLE_1Mbit mode.

Definition at line 1160 of file nrf51_bitfields.h.

◆ FICR_OVERRIDEEN_BLE_1MBIT_Override

#define FICR_OVERRIDEEN_BLE_1MBIT_Override (0UL)

Override the default values for BLE_1Mbit mode.

Definition at line 1159 of file nrf51_bitfields.h.

◆ FICR_OVERRIDEEN_BLE_1MBIT_Pos

#define FICR_OVERRIDEEN_BLE_1MBIT_Pos (3UL)

Position of BLE_1MBIT field.

Definition at line 1157 of file nrf51_bitfields.h.

◆ FICR_OVERRIDEEN_NRF_1MBIT_Msk

#define FICR_OVERRIDEEN_NRF_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_NRF_1MBIT_Pos)

Bit mask of NRF_1MBIT field.

Definition at line 1164 of file nrf51_bitfields.h.

◆ FICR_OVERRIDEEN_NRF_1MBIT_NotOverride

#define FICR_OVERRIDEEN_NRF_1MBIT_NotOverride (1UL)

Do not override the default values for NRF_1Mbit mode.

Definition at line 1166 of file nrf51_bitfields.h.

◆ FICR_OVERRIDEEN_NRF_1MBIT_Override

#define FICR_OVERRIDEEN_NRF_1MBIT_Override (0UL)

Override the default values for NRF_1Mbit mode.

Definition at line 1165 of file nrf51_bitfields.h.

◆ FICR_OVERRIDEEN_NRF_1MBIT_Pos

#define FICR_OVERRIDEEN_NRF_1MBIT_Pos (0UL)

Position of NRF_1MBIT field.

Definition at line 1163 of file nrf51_bitfields.h.

◆ FICR_PPFC_PPFC_Msk

#define FICR_PPFC_PPFC_Msk (0xFFUL << FICR_PPFC_PPFC_Pos)

Bit mask of PPFC field.

Definition at line 1129 of file nrf51_bitfields.h.

◆ FICR_PPFC_PPFC_NotPresent

#define FICR_PPFC_PPFC_NotPresent (0xFFUL)

Not present.

Definition at line 1131 of file nrf51_bitfields.h.

◆ FICR_PPFC_PPFC_Pos

#define FICR_PPFC_PPFC_Pos (0UL)

Position of PPFC field.

Definition at line 1128 of file nrf51_bitfields.h.

◆ FICR_PPFC_PPFC_Present

#define FICR_PPFC_PPFC_Present (0x00UL)

Present.

Definition at line 1130 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN0_Input

#define GPIO_DIR_PIN0_Input (0UL)

Pin set as input.

Definition at line 2208 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN0_Msk

#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos)

Bit mask of PIN0 field.

Definition at line 2207 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN0_Output

#define GPIO_DIR_PIN0_Output (1UL)

Pin set as output.

Definition at line 2209 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN0_Pos

#define GPIO_DIR_PIN0_Pos (0UL)

Position of PIN0 field.

Definition at line 2206 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN10_Input

#define GPIO_DIR_PIN10_Input (0UL)

Pin set as input.

Definition at line 2148 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN10_Msk

#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos)

Bit mask of PIN10 field.

Definition at line 2147 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN10_Output

#define GPIO_DIR_PIN10_Output (1UL)

Pin set as output.

Definition at line 2149 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN10_Pos

#define GPIO_DIR_PIN10_Pos (10UL)

Position of PIN10 field.

Definition at line 2146 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN11_Input

#define GPIO_DIR_PIN11_Input (0UL)

Pin set as input.

Definition at line 2142 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN11_Msk

#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos)

Bit mask of PIN11 field.

Definition at line 2141 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN11_Output

#define GPIO_DIR_PIN11_Output (1UL)

Pin set as output.

Definition at line 2143 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN11_Pos

#define GPIO_DIR_PIN11_Pos (11UL)

Position of PIN11 field.

Definition at line 2140 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN12_Input

#define GPIO_DIR_PIN12_Input (0UL)

Pin set as input.

Definition at line 2136 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN12_Msk

#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos)

Bit mask of PIN12 field.

Definition at line 2135 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN12_Output

#define GPIO_DIR_PIN12_Output (1UL)

Pin set as output.

Definition at line 2137 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN12_Pos

#define GPIO_DIR_PIN12_Pos (12UL)

Position of PIN12 field.

Definition at line 2134 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN13_Input

#define GPIO_DIR_PIN13_Input (0UL)

Pin set as input.

Definition at line 2130 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN13_Msk

#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos)

Bit mask of PIN13 field.

Definition at line 2129 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN13_Output

#define GPIO_DIR_PIN13_Output (1UL)

Pin set as output.

Definition at line 2131 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN13_Pos

#define GPIO_DIR_PIN13_Pos (13UL)

Position of PIN13 field.

Definition at line 2128 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN14_Input

#define GPIO_DIR_PIN14_Input (0UL)

Pin set as input.

Definition at line 2124 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN14_Msk

#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos)

Bit mask of PIN14 field.

Definition at line 2123 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN14_Output

#define GPIO_DIR_PIN14_Output (1UL)

Pin set as output.

Definition at line 2125 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN14_Pos

#define GPIO_DIR_PIN14_Pos (14UL)

Position of PIN14 field.

Definition at line 2122 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN15_Input

#define GPIO_DIR_PIN15_Input (0UL)

Pin set as input.

Definition at line 2118 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN15_Msk

#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos)

Bit mask of PIN15 field.

Definition at line 2117 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN15_Output

#define GPIO_DIR_PIN15_Output (1UL)

Pin set as output.

Definition at line 2119 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN15_Pos

#define GPIO_DIR_PIN15_Pos (15UL)

Position of PIN15 field.

Definition at line 2116 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN16_Input

#define GPIO_DIR_PIN16_Input (0UL)

Pin set as input.

Definition at line 2112 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN16_Msk

#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos)

Bit mask of PIN16 field.

Definition at line 2111 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN16_Output

#define GPIO_DIR_PIN16_Output (1UL)

Pin set as output.

Definition at line 2113 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN16_Pos

#define GPIO_DIR_PIN16_Pos (16UL)

Position of PIN16 field.

Definition at line 2110 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN17_Input

#define GPIO_DIR_PIN17_Input (0UL)

Pin set as input.

Definition at line 2106 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN17_Msk

#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos)

Bit mask of PIN17 field.

Definition at line 2105 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN17_Output

#define GPIO_DIR_PIN17_Output (1UL)

Pin set as output.

Definition at line 2107 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN17_Pos

#define GPIO_DIR_PIN17_Pos (17UL)

Position of PIN17 field.

Definition at line 2104 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN18_Input

#define GPIO_DIR_PIN18_Input (0UL)

Pin set as input.

Definition at line 2100 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN18_Msk

#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos)

Bit mask of PIN18 field.

Definition at line 2099 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN18_Output

#define GPIO_DIR_PIN18_Output (1UL)

Pin set as output.

Definition at line 2101 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN18_Pos

#define GPIO_DIR_PIN18_Pos (18UL)

Position of PIN18 field.

Definition at line 2098 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN19_Input

#define GPIO_DIR_PIN19_Input (0UL)

Pin set as input.

Definition at line 2094 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN19_Msk

#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos)

Bit mask of PIN19 field.

Definition at line 2093 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN19_Output

#define GPIO_DIR_PIN19_Output (1UL)

Pin set as output.

Definition at line 2095 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN19_Pos

#define GPIO_DIR_PIN19_Pos (19UL)

Position of PIN19 field.

Definition at line 2092 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN1_Input

#define GPIO_DIR_PIN1_Input (0UL)

Pin set as input.

Definition at line 2202 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN1_Msk

#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos)

Bit mask of PIN1 field.

Definition at line 2201 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN1_Output

#define GPIO_DIR_PIN1_Output (1UL)

Pin set as output.

Definition at line 2203 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN1_Pos

#define GPIO_DIR_PIN1_Pos (1UL)

Position of PIN1 field.

Definition at line 2200 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN20_Input

#define GPIO_DIR_PIN20_Input (0UL)

Pin set as input.

Definition at line 2088 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN20_Msk

#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos)

Bit mask of PIN20 field.

Definition at line 2087 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN20_Output

#define GPIO_DIR_PIN20_Output (1UL)

Pin set as output.

Definition at line 2089 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN20_Pos

#define GPIO_DIR_PIN20_Pos (20UL)

Position of PIN20 field.

Definition at line 2086 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN21_Input

#define GPIO_DIR_PIN21_Input (0UL)

Pin set as input.

Definition at line 2082 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN21_Msk

#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos)

Bit mask of PIN21 field.

Definition at line 2081 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN21_Output

#define GPIO_DIR_PIN21_Output (1UL)

Pin set as output.

Definition at line 2083 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN21_Pos

#define GPIO_DIR_PIN21_Pos (21UL)

Position of PIN21 field.

Definition at line 2080 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN22_Input

#define GPIO_DIR_PIN22_Input (0UL)

Pin set as input.

Definition at line 2076 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN22_Msk

#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos)

Bit mask of PIN22 field.

Definition at line 2075 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN22_Output

#define GPIO_DIR_PIN22_Output (1UL)

Pin set as output.

Definition at line 2077 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN22_Pos

#define GPIO_DIR_PIN22_Pos (22UL)

Position of PIN22 field.

Definition at line 2074 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN23_Input

#define GPIO_DIR_PIN23_Input (0UL)

Pin set as input.

Definition at line 2070 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN23_Msk

#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos)

Bit mask of PIN23 field.

Definition at line 2069 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN23_Output

#define GPIO_DIR_PIN23_Output (1UL)

Pin set as output.

Definition at line 2071 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN23_Pos

#define GPIO_DIR_PIN23_Pos (23UL)

Position of PIN23 field.

Definition at line 2068 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN24_Input

#define GPIO_DIR_PIN24_Input (0UL)

Pin set as input.

Definition at line 2064 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN24_Msk

#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos)

Bit mask of PIN24 field.

Definition at line 2063 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN24_Output

#define GPIO_DIR_PIN24_Output (1UL)

Pin set as output.

Definition at line 2065 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN24_Pos

#define GPIO_DIR_PIN24_Pos (24UL)

Position of PIN24 field.

Definition at line 2062 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN25_Input

#define GPIO_DIR_PIN25_Input (0UL)

Pin set as input.

Definition at line 2058 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN25_Msk

#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos)

Bit mask of PIN25 field.

Definition at line 2057 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN25_Output

#define GPIO_DIR_PIN25_Output (1UL)

Pin set as output.

Definition at line 2059 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN25_Pos

#define GPIO_DIR_PIN25_Pos (25UL)

Position of PIN25 field.

Definition at line 2056 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN26_Input

#define GPIO_DIR_PIN26_Input (0UL)

Pin set as input.

Definition at line 2052 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN26_Msk

#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos)

Bit mask of PIN26 field.

Definition at line 2051 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN26_Output

#define GPIO_DIR_PIN26_Output (1UL)

Pin set as output.

Definition at line 2053 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN26_Pos

#define GPIO_DIR_PIN26_Pos (26UL)

Position of PIN26 field.

Definition at line 2050 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN27_Input

#define GPIO_DIR_PIN27_Input (0UL)

Pin set as input.

Definition at line 2046 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN27_Msk

#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos)

Bit mask of PIN27 field.

Definition at line 2045 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN27_Output

#define GPIO_DIR_PIN27_Output (1UL)

Pin set as output.

Definition at line 2047 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN27_Pos

#define GPIO_DIR_PIN27_Pos (27UL)

Position of PIN27 field.

Definition at line 2044 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN28_Input

#define GPIO_DIR_PIN28_Input (0UL)

Pin set as input.

Definition at line 2040 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN28_Msk

#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos)

Bit mask of PIN28 field.

Definition at line 2039 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN28_Output

#define GPIO_DIR_PIN28_Output (1UL)

Pin set as output.

Definition at line 2041 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN28_Pos

#define GPIO_DIR_PIN28_Pos (28UL)

Position of PIN28 field.

Definition at line 2038 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN29_Input

#define GPIO_DIR_PIN29_Input (0UL)

Pin set as input.

Definition at line 2034 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN29_Msk

#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos)

Bit mask of PIN29 field.

Definition at line 2033 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN29_Output

#define GPIO_DIR_PIN29_Output (1UL)

Pin set as output.

Definition at line 2035 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN29_Pos

#define GPIO_DIR_PIN29_Pos (29UL)

Position of PIN29 field.

Definition at line 2032 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN2_Input

#define GPIO_DIR_PIN2_Input (0UL)

Pin set as input.

Definition at line 2196 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN2_Msk

#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos)

Bit mask of PIN2 field.

Definition at line 2195 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN2_Output

#define GPIO_DIR_PIN2_Output (1UL)

Pin set as output.

Definition at line 2197 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN2_Pos

#define GPIO_DIR_PIN2_Pos (2UL)

Position of PIN2 field.

Definition at line 2194 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN30_Input

#define GPIO_DIR_PIN30_Input (0UL)

Pin set as input.

Definition at line 2028 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN30_Msk

#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos)

Bit mask of PIN30 field.

Definition at line 2027 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN30_Output

#define GPIO_DIR_PIN30_Output (1UL)

Pin set as output.

Definition at line 2029 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN30_Pos

#define GPIO_DIR_PIN30_Pos (30UL)

Position of PIN30 field.

Definition at line 2026 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN31_Input

#define GPIO_DIR_PIN31_Input (0UL)

Pin set as input.

Definition at line 2022 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN31_Msk

#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos)

Bit mask of PIN31 field.

Definition at line 2021 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN31_Output

#define GPIO_DIR_PIN31_Output (1UL)

Pin set as output.

Definition at line 2023 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN31_Pos

#define GPIO_DIR_PIN31_Pos (31UL)

Position of PIN31 field.

Definition at line 2020 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN3_Input

#define GPIO_DIR_PIN3_Input (0UL)

Pin set as input.

Definition at line 2190 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN3_Msk

#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos)

Bit mask of PIN3 field.

Definition at line 2189 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN3_Output

#define GPIO_DIR_PIN3_Output (1UL)

Pin set as output.

Definition at line 2191 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN3_Pos

#define GPIO_DIR_PIN3_Pos (3UL)

Position of PIN3 field.

Definition at line 2188 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN4_Input

#define GPIO_DIR_PIN4_Input (0UL)

Pin set as input.

Definition at line 2184 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN4_Msk

#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos)

Bit mask of PIN4 field.

Definition at line 2183 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN4_Output

#define GPIO_DIR_PIN4_Output (1UL)

Pin set as output.

Definition at line 2185 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN4_Pos

#define GPIO_DIR_PIN4_Pos (4UL)

Position of PIN4 field.

Definition at line 2182 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN5_Input

#define GPIO_DIR_PIN5_Input (0UL)

Pin set as input.

Definition at line 2178 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN5_Msk

#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos)

Bit mask of PIN5 field.

Definition at line 2177 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN5_Output

#define GPIO_DIR_PIN5_Output (1UL)

Pin set as output.

Definition at line 2179 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN5_Pos

#define GPIO_DIR_PIN5_Pos (5UL)

Position of PIN5 field.

Definition at line 2176 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN6_Input

#define GPIO_DIR_PIN6_Input (0UL)

Pin set as input.

Definition at line 2172 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN6_Msk

#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos)

Bit mask of PIN6 field.

Definition at line 2171 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN6_Output

#define GPIO_DIR_PIN6_Output (1UL)

Pin set as output.

Definition at line 2173 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN6_Pos

#define GPIO_DIR_PIN6_Pos (6UL)

Position of PIN6 field.

Definition at line 2170 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN7_Input

#define GPIO_DIR_PIN7_Input (0UL)

Pin set as input.

Definition at line 2166 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN7_Msk

#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos)

Bit mask of PIN7 field.

Definition at line 2165 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN7_Output

#define GPIO_DIR_PIN7_Output (1UL)

Pin set as output.

Definition at line 2167 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN7_Pos

#define GPIO_DIR_PIN7_Pos (7UL)

Position of PIN7 field.

Definition at line 2164 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN8_Input

#define GPIO_DIR_PIN8_Input (0UL)

Pin set as input.

Definition at line 2160 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN8_Msk

#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos)

Bit mask of PIN8 field.

Definition at line 2159 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN8_Output

#define GPIO_DIR_PIN8_Output (1UL)

Pin set as output.

Definition at line 2161 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN8_Pos

#define GPIO_DIR_PIN8_Pos (8UL)

Position of PIN8 field.

Definition at line 2158 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN9_Input

#define GPIO_DIR_PIN9_Input (0UL)

Pin set as input.

Definition at line 2154 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN9_Msk

#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos)

Bit mask of PIN9 field.

Definition at line 2153 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN9_Output

#define GPIO_DIR_PIN9_Output (1UL)

Pin set as output.

Definition at line 2155 of file nrf51_bitfields.h.

◆ GPIO_DIR_PIN9_Pos

#define GPIO_DIR_PIN9_Pos (9UL)

Position of PIN9 field.

Definition at line 2152 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN0_Clear

#define GPIO_DIRCLR_PIN0_Clear (1UL)

Set pin as input.

Definition at line 2663 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN0_Input

#define GPIO_DIRCLR_PIN0_Input (0UL)

Pin set as input.

Definition at line 2661 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN0_Msk

#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos)

Bit mask of PIN0 field.

Definition at line 2660 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN0_Output

#define GPIO_DIRCLR_PIN0_Output (1UL)

Pin set as output.

Definition at line 2662 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN0_Pos

#define GPIO_DIRCLR_PIN0_Pos (0UL)

Position of PIN0 field.

Definition at line 2659 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN10_Clear

#define GPIO_DIRCLR_PIN10_Clear (1UL)

Set pin as input.

Definition at line 2593 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN10_Input

#define GPIO_DIRCLR_PIN10_Input (0UL)

Pin set as input.

Definition at line 2591 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN10_Msk

#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos)

Bit mask of PIN10 field.

Definition at line 2590 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN10_Output

#define GPIO_DIRCLR_PIN10_Output (1UL)

Pin set as output.

Definition at line 2592 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN10_Pos

#define GPIO_DIRCLR_PIN10_Pos (10UL)

Position of PIN10 field.

Definition at line 2589 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN11_Clear

#define GPIO_DIRCLR_PIN11_Clear (1UL)

Set pin as input.

Definition at line 2586 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN11_Input

#define GPIO_DIRCLR_PIN11_Input (0UL)

Pin set as input.

Definition at line 2584 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN11_Msk

#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos)

Bit mask of PIN11 field.

Definition at line 2583 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN11_Output

#define GPIO_DIRCLR_PIN11_Output (1UL)

Pin set as output.

Definition at line 2585 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN11_Pos

#define GPIO_DIRCLR_PIN11_Pos (11UL)

Position of PIN11 field.

Definition at line 2582 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN12_Clear

#define GPIO_DIRCLR_PIN12_Clear (1UL)

Set pin as input.

Definition at line 2579 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN12_Input

#define GPIO_DIRCLR_PIN12_Input (0UL)

Pin set as input.

Definition at line 2577 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN12_Msk

#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos)

Bit mask of PIN12 field.

Definition at line 2576 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN12_Output

#define GPIO_DIRCLR_PIN12_Output (1UL)

Pin set as output.

Definition at line 2578 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN12_Pos

#define GPIO_DIRCLR_PIN12_Pos (12UL)

Position of PIN12 field.

Definition at line 2575 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN13_Clear

#define GPIO_DIRCLR_PIN13_Clear (1UL)

Set pin as input.

Definition at line 2572 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN13_Input

#define GPIO_DIRCLR_PIN13_Input (0UL)

Pin set as input.

Definition at line 2570 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN13_Msk

#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos)

Bit mask of PIN13 field.

Definition at line 2569 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN13_Output

#define GPIO_DIRCLR_PIN13_Output (1UL)

Pin set as output.

Definition at line 2571 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN13_Pos

#define GPIO_DIRCLR_PIN13_Pos (13UL)

Position of PIN13 field.

Definition at line 2568 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN14_Clear

#define GPIO_DIRCLR_PIN14_Clear (1UL)

Set pin as input.

Definition at line 2565 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN14_Input

#define GPIO_DIRCLR_PIN14_Input (0UL)

Pin set as input.

Definition at line 2563 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN14_Msk

#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos)

Bit mask of PIN14 field.

Definition at line 2562 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN14_Output

#define GPIO_DIRCLR_PIN14_Output (1UL)

Pin set as output.

Definition at line 2564 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN14_Pos

#define GPIO_DIRCLR_PIN14_Pos (14UL)

Position of PIN14 field.

Definition at line 2561 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN15_Clear

#define GPIO_DIRCLR_PIN15_Clear (1UL)

Set pin as input.

Definition at line 2558 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN15_Input

#define GPIO_DIRCLR_PIN15_Input (0UL)

Pin set as input.

Definition at line 2556 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN15_Msk

#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos)

Bit mask of PIN15 field.

Definition at line 2555 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN15_Output

#define GPIO_DIRCLR_PIN15_Output (1UL)

Pin set as output.

Definition at line 2557 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN15_Pos

#define GPIO_DIRCLR_PIN15_Pos (15UL)

Position of PIN15 field.

Definition at line 2554 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN16_Clear

#define GPIO_DIRCLR_PIN16_Clear (1UL)

Set pin as input.

Definition at line 2551 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN16_Input

#define GPIO_DIRCLR_PIN16_Input (0UL)

Pin set as input.

Definition at line 2549 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN16_Msk

#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos)

Bit mask of PIN16 field.

Definition at line 2548 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN16_Output

#define GPIO_DIRCLR_PIN16_Output (1UL)

Pin set as output.

Definition at line 2550 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN16_Pos

#define GPIO_DIRCLR_PIN16_Pos (16UL)

Position of PIN16 field.

Definition at line 2547 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN17_Clear

#define GPIO_DIRCLR_PIN17_Clear (1UL)

Set pin as input.

Definition at line 2544 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN17_Input

#define GPIO_DIRCLR_PIN17_Input (0UL)

Pin set as input.

Definition at line 2542 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN17_Msk

#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos)

Bit mask of PIN17 field.

Definition at line 2541 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN17_Output

#define GPIO_DIRCLR_PIN17_Output (1UL)

Pin set as output.

Definition at line 2543 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN17_Pos

#define GPIO_DIRCLR_PIN17_Pos (17UL)

Position of PIN17 field.

Definition at line 2540 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN18_Clear

#define GPIO_DIRCLR_PIN18_Clear (1UL)

Set pin as input.

Definition at line 2537 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN18_Input

#define GPIO_DIRCLR_PIN18_Input (0UL)

Pin set as input.

Definition at line 2535 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN18_Msk

#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos)

Bit mask of PIN18 field.

Definition at line 2534 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN18_Output

#define GPIO_DIRCLR_PIN18_Output (1UL)

Pin set as output.

Definition at line 2536 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN18_Pos

#define GPIO_DIRCLR_PIN18_Pos (18UL)

Position of PIN18 field.

Definition at line 2533 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN19_Clear

#define GPIO_DIRCLR_PIN19_Clear (1UL)

Set pin as input.

Definition at line 2530 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN19_Input

#define GPIO_DIRCLR_PIN19_Input (0UL)

Pin set as input.

Definition at line 2528 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN19_Msk

#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos)

Bit mask of PIN19 field.

Definition at line 2527 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN19_Output

#define GPIO_DIRCLR_PIN19_Output (1UL)

Pin set as output.

Definition at line 2529 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN19_Pos

#define GPIO_DIRCLR_PIN19_Pos (19UL)

Position of PIN19 field.

Definition at line 2526 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN1_Clear

#define GPIO_DIRCLR_PIN1_Clear (1UL)

Set pin as input.

Definition at line 2656 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN1_Input

#define GPIO_DIRCLR_PIN1_Input (0UL)

Pin set as input.

Definition at line 2654 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN1_Msk

#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos)

Bit mask of PIN1 field.

Definition at line 2653 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN1_Output

#define GPIO_DIRCLR_PIN1_Output (1UL)

Pin set as output.

Definition at line 2655 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN1_Pos

#define GPIO_DIRCLR_PIN1_Pos (1UL)

Position of PIN1 field.

Definition at line 2652 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN20_Clear

#define GPIO_DIRCLR_PIN20_Clear (1UL)

Set pin as input.

Definition at line 2523 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN20_Input

#define GPIO_DIRCLR_PIN20_Input (0UL)

Pin set as input.

Definition at line 2521 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN20_Msk

#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos)

Bit mask of PIN20 field.

Definition at line 2520 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN20_Output

#define GPIO_DIRCLR_PIN20_Output (1UL)

Pin set as output.

Definition at line 2522 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN20_Pos

#define GPIO_DIRCLR_PIN20_Pos (20UL)

Position of PIN20 field.

Definition at line 2519 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN21_Clear

#define GPIO_DIRCLR_PIN21_Clear (1UL)

Set pin as input.

Definition at line 2516 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN21_Input

#define GPIO_DIRCLR_PIN21_Input (0UL)

Pin set as input.

Definition at line 2514 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN21_Msk

#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos)

Bit mask of PIN21 field.

Definition at line 2513 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN21_Output

#define GPIO_DIRCLR_PIN21_Output (1UL)

Pin set as output.

Definition at line 2515 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN21_Pos

#define GPIO_DIRCLR_PIN21_Pos (21UL)

Position of PIN21 field.

Definition at line 2512 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN22_Clear

#define GPIO_DIRCLR_PIN22_Clear (1UL)

Set pin as input.

Definition at line 2509 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN22_Input

#define GPIO_DIRCLR_PIN22_Input (0UL)

Pin set as input.

Definition at line 2507 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN22_Msk

#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos)

Bit mask of PIN22 field.

Definition at line 2506 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN22_Output

#define GPIO_DIRCLR_PIN22_Output (1UL)

Pin set as output.

Definition at line 2508 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN22_Pos

#define GPIO_DIRCLR_PIN22_Pos (22UL)

Position of PIN22 field.

Definition at line 2505 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN23_Clear

#define GPIO_DIRCLR_PIN23_Clear (1UL)

Set pin as input.

Definition at line 2502 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN23_Input

#define GPIO_DIRCLR_PIN23_Input (0UL)

Pin set as input.

Definition at line 2500 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN23_Msk

#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos)

Bit mask of PIN23 field.

Definition at line 2499 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN23_Output

#define GPIO_DIRCLR_PIN23_Output (1UL)

Pin set as output.

Definition at line 2501 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN23_Pos

#define GPIO_DIRCLR_PIN23_Pos (23UL)

Position of PIN23 field.

Definition at line 2498 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN24_Clear

#define GPIO_DIRCLR_PIN24_Clear (1UL)

Set pin as input.

Definition at line 2495 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN24_Input

#define GPIO_DIRCLR_PIN24_Input (0UL)

Pin set as input.

Definition at line 2493 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN24_Msk

#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos)

Bit mask of PIN24 field.

Definition at line 2492 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN24_Output

#define GPIO_DIRCLR_PIN24_Output (1UL)

Pin set as output.

Definition at line 2494 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN24_Pos

#define GPIO_DIRCLR_PIN24_Pos (24UL)

Position of PIN24 field.

Definition at line 2491 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN25_Clear

#define GPIO_DIRCLR_PIN25_Clear (1UL)

Set pin as input.

Definition at line 2488 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN25_Input

#define GPIO_DIRCLR_PIN25_Input (0UL)

Pin set as input.

Definition at line 2486 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN25_Msk

#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos)

Bit mask of PIN25 field.

Definition at line 2485 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN25_Output

#define GPIO_DIRCLR_PIN25_Output (1UL)

Pin set as output.

Definition at line 2487 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN25_Pos

#define GPIO_DIRCLR_PIN25_Pos (25UL)

Position of PIN25 field.

Definition at line 2484 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN26_Clear

#define GPIO_DIRCLR_PIN26_Clear (1UL)

Set pin as input.

Definition at line 2481 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN26_Input

#define GPIO_DIRCLR_PIN26_Input (0UL)

Pin set as input.

Definition at line 2479 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN26_Msk

#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos)

Bit mask of PIN26 field.

Definition at line 2478 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN26_Output

#define GPIO_DIRCLR_PIN26_Output (1UL)

Pin set as output.

Definition at line 2480 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN26_Pos

#define GPIO_DIRCLR_PIN26_Pos (26UL)

Position of PIN26 field.

Definition at line 2477 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN27_Clear

#define GPIO_DIRCLR_PIN27_Clear (1UL)

Set pin as input.

Definition at line 2474 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN27_Input

#define GPIO_DIRCLR_PIN27_Input (0UL)

Pin set as input.

Definition at line 2472 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN27_Msk

#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos)

Bit mask of PIN27 field.

Definition at line 2471 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN27_Output

#define GPIO_DIRCLR_PIN27_Output (1UL)

Pin set as output.

Definition at line 2473 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN27_Pos

#define GPIO_DIRCLR_PIN27_Pos (27UL)

Position of PIN27 field.

Definition at line 2470 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN28_Clear

#define GPIO_DIRCLR_PIN28_Clear (1UL)

Set pin as input.

Definition at line 2467 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN28_Input

#define GPIO_DIRCLR_PIN28_Input (0UL)

Pin set as input.

Definition at line 2465 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN28_Msk

#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos)

Bit mask of PIN28 field.

Definition at line 2464 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN28_Output

#define GPIO_DIRCLR_PIN28_Output (1UL)

Pin set as output.

Definition at line 2466 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN28_Pos

#define GPIO_DIRCLR_PIN28_Pos (28UL)

Position of PIN28 field.

Definition at line 2463 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN29_Clear

#define GPIO_DIRCLR_PIN29_Clear (1UL)

Set pin as input.

Definition at line 2460 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN29_Input

#define GPIO_DIRCLR_PIN29_Input (0UL)

Pin set as input.

Definition at line 2458 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN29_Msk

#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos)

Bit mask of PIN29 field.

Definition at line 2457 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN29_Output

#define GPIO_DIRCLR_PIN29_Output (1UL)

Pin set as output.

Definition at line 2459 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN29_Pos

#define GPIO_DIRCLR_PIN29_Pos (29UL)

Position of PIN29 field.

Definition at line 2456 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN2_Clear

#define GPIO_DIRCLR_PIN2_Clear (1UL)

Set pin as input.

Definition at line 2649 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN2_Input

#define GPIO_DIRCLR_PIN2_Input (0UL)

Pin set as input.

Definition at line 2647 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN2_Msk

#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos)

Bit mask of PIN2 field.

Definition at line 2646 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN2_Output

#define GPIO_DIRCLR_PIN2_Output (1UL)

Pin set as output.

Definition at line 2648 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN2_Pos

#define GPIO_DIRCLR_PIN2_Pos (2UL)

Position of PIN2 field.

Definition at line 2645 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN30_Clear

#define GPIO_DIRCLR_PIN30_Clear (1UL)

Set pin as input.

Definition at line 2453 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN30_Input

#define GPIO_DIRCLR_PIN30_Input (0UL)

Pin set as input.

Definition at line 2451 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN30_Msk

#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos)

Bit mask of PIN30 field.

Definition at line 2450 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN30_Output

#define GPIO_DIRCLR_PIN30_Output (1UL)

Pin set as output.

Definition at line 2452 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN30_Pos

#define GPIO_DIRCLR_PIN30_Pos (30UL)

Position of PIN30 field.

Definition at line 2449 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN31_Clear

#define GPIO_DIRCLR_PIN31_Clear (1UL)

Set pin as input.

Definition at line 2446 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN31_Input

#define GPIO_DIRCLR_PIN31_Input (0UL)

Pin set as input.

Definition at line 2444 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN31_Msk

#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos)

Bit mask of PIN31 field.

Definition at line 2443 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN31_Output

#define GPIO_DIRCLR_PIN31_Output (1UL)

Pin set as output.

Definition at line 2445 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN31_Pos

#define GPIO_DIRCLR_PIN31_Pos (31UL)

Position of PIN31 field.

Definition at line 2442 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN3_Clear

#define GPIO_DIRCLR_PIN3_Clear (1UL)

Set pin as input.

Definition at line 2642 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN3_Input

#define GPIO_DIRCLR_PIN3_Input (0UL)

Pin set as input.

Definition at line 2640 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN3_Msk

#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos)

Bit mask of PIN3 field.

Definition at line 2639 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN3_Output

#define GPIO_DIRCLR_PIN3_Output (1UL)

Pin set as output.

Definition at line 2641 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN3_Pos

#define GPIO_DIRCLR_PIN3_Pos (3UL)

Position of PIN3 field.

Definition at line 2638 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN4_Clear

#define GPIO_DIRCLR_PIN4_Clear (1UL)

Set pin as input.

Definition at line 2635 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN4_Input

#define GPIO_DIRCLR_PIN4_Input (0UL)

Pin set as input.

Definition at line 2633 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN4_Msk

#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos)

Bit mask of PIN4 field.

Definition at line 2632 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN4_Output

#define GPIO_DIRCLR_PIN4_Output (1UL)

Pin set as output.

Definition at line 2634 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN4_Pos

#define GPIO_DIRCLR_PIN4_Pos (4UL)

Position of PIN4 field.

Definition at line 2631 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN5_Clear

#define GPIO_DIRCLR_PIN5_Clear (1UL)

Set pin as input.

Definition at line 2628 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN5_Input

#define GPIO_DIRCLR_PIN5_Input (0UL)

Pin set as input.

Definition at line 2626 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN5_Msk

#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos)

Bit mask of PIN5 field.

Definition at line 2625 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN5_Output

#define GPIO_DIRCLR_PIN5_Output (1UL)

Pin set as output.

Definition at line 2627 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN5_Pos

#define GPIO_DIRCLR_PIN5_Pos (5UL)

Position of PIN5 field.

Definition at line 2624 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN6_Clear

#define GPIO_DIRCLR_PIN6_Clear (1UL)

Set pin as input.

Definition at line 2621 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN6_Input

#define GPIO_DIRCLR_PIN6_Input (0UL)

Pin set as input.

Definition at line 2619 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN6_Msk

#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos)

Bit mask of PIN6 field.

Definition at line 2618 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN6_Output

#define GPIO_DIRCLR_PIN6_Output (1UL)

Pin set as output.

Definition at line 2620 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN6_Pos

#define GPIO_DIRCLR_PIN6_Pos (6UL)

Position of PIN6 field.

Definition at line 2617 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN7_Clear

#define GPIO_DIRCLR_PIN7_Clear (1UL)

Set pin as input.

Definition at line 2614 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN7_Input

#define GPIO_DIRCLR_PIN7_Input (0UL)

Pin set as input.

Definition at line 2612 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN7_Msk

#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos)

Bit mask of PIN7 field.

Definition at line 2611 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN7_Output

#define GPIO_DIRCLR_PIN7_Output (1UL)

Pin set as output.

Definition at line 2613 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN7_Pos

#define GPIO_DIRCLR_PIN7_Pos (7UL)

Position of PIN7 field.

Definition at line 2610 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN8_Clear

#define GPIO_DIRCLR_PIN8_Clear (1UL)

Set pin as input.

Definition at line 2607 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN8_Input

#define GPIO_DIRCLR_PIN8_Input (0UL)

Pin set as input.

Definition at line 2605 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN8_Msk

#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos)

Bit mask of PIN8 field.

Definition at line 2604 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN8_Output

#define GPIO_DIRCLR_PIN8_Output (1UL)

Pin set as output.

Definition at line 2606 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN8_Pos

#define GPIO_DIRCLR_PIN8_Pos (8UL)

Position of PIN8 field.

Definition at line 2603 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN9_Clear

#define GPIO_DIRCLR_PIN9_Clear (1UL)

Set pin as input.

Definition at line 2600 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN9_Input

#define GPIO_DIRCLR_PIN9_Input (0UL)

Pin set as input.

Definition at line 2598 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN9_Msk

#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos)

Bit mask of PIN9 field.

Definition at line 2597 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN9_Output

#define GPIO_DIRCLR_PIN9_Output (1UL)

Pin set as output.

Definition at line 2599 of file nrf51_bitfields.h.

◆ GPIO_DIRCLR_PIN9_Pos

#define GPIO_DIRCLR_PIN9_Pos (9UL)

Position of PIN9 field.

Definition at line 2596 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN0_Input

#define GPIO_DIRSET_PIN0_Input (0UL)

Pin set as input.

Definition at line 2434 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN0_Msk

#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos)

Bit mask of PIN0 field.

Definition at line 2433 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN0_Output

#define GPIO_DIRSET_PIN0_Output (1UL)

Pin set as output.

Definition at line 2435 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN0_Pos

#define GPIO_DIRSET_PIN0_Pos (0UL)

Position of PIN0 field.

Definition at line 2432 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN0_Set

#define GPIO_DIRSET_PIN0_Set (1UL)

Set pin as output.

Definition at line 2436 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN10_Input

#define GPIO_DIRSET_PIN10_Input (0UL)

Pin set as input.

Definition at line 2364 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN10_Msk

#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos)

Bit mask of PIN10 field.

Definition at line 2363 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN10_Output

#define GPIO_DIRSET_PIN10_Output (1UL)

Pin set as output.

Definition at line 2365 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN10_Pos

#define GPIO_DIRSET_PIN10_Pos (10UL)

Position of PIN10 field.

Definition at line 2362 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN10_Set

#define GPIO_DIRSET_PIN10_Set (1UL)

Set pin as output.

Definition at line 2366 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN11_Input

#define GPIO_DIRSET_PIN11_Input (0UL)

Pin set as input.

Definition at line 2357 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN11_Msk

#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos)

Bit mask of PIN11 field.

Definition at line 2356 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN11_Output

#define GPIO_DIRSET_PIN11_Output (1UL)

Pin set as output.

Definition at line 2358 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN11_Pos

#define GPIO_DIRSET_PIN11_Pos (11UL)

Position of PIN11 field.

Definition at line 2355 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN11_Set

#define GPIO_DIRSET_PIN11_Set (1UL)

Set pin as output.

Definition at line 2359 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN12_Input

#define GPIO_DIRSET_PIN12_Input (0UL)

Pin set as input.

Definition at line 2350 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN12_Msk

#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos)

Bit mask of PIN12 field.

Definition at line 2349 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN12_Output

#define GPIO_DIRSET_PIN12_Output (1UL)

Pin set as output.

Definition at line 2351 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN12_Pos

#define GPIO_DIRSET_PIN12_Pos (12UL)

Position of PIN12 field.

Definition at line 2348 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN12_Set

#define GPIO_DIRSET_PIN12_Set (1UL)

Set pin as output.

Definition at line 2352 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN13_Input

#define GPIO_DIRSET_PIN13_Input (0UL)

Pin set as input.

Definition at line 2343 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN13_Msk

#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos)

Bit mask of PIN13 field.

Definition at line 2342 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN13_Output

#define GPIO_DIRSET_PIN13_Output (1UL)

Pin set as output.

Definition at line 2344 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN13_Pos

#define GPIO_DIRSET_PIN13_Pos (13UL)

Position of PIN13 field.

Definition at line 2341 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN13_Set

#define GPIO_DIRSET_PIN13_Set (1UL)

Set pin as output.

Definition at line 2345 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN14_Input

#define GPIO_DIRSET_PIN14_Input (0UL)

Pin set as input.

Definition at line 2336 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN14_Msk

#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos)

Bit mask of PIN14 field.

Definition at line 2335 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN14_Output

#define GPIO_DIRSET_PIN14_Output (1UL)

Pin set as output.

Definition at line 2337 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN14_Pos

#define GPIO_DIRSET_PIN14_Pos (14UL)

Position of PIN14 field.

Definition at line 2334 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN14_Set

#define GPIO_DIRSET_PIN14_Set (1UL)

Set pin as output.

Definition at line 2338 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN15_Input

#define GPIO_DIRSET_PIN15_Input (0UL)

Pin set as input.

Definition at line 2329 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN15_Msk

#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos)

Bit mask of PIN15 field.

Definition at line 2328 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN15_Output

#define GPIO_DIRSET_PIN15_Output (1UL)

Pin set as output.

Definition at line 2330 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN15_Pos

#define GPIO_DIRSET_PIN15_Pos (15UL)

Position of PIN15 field.

Definition at line 2327 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN15_Set

#define GPIO_DIRSET_PIN15_Set (1UL)

Set pin as output.

Definition at line 2331 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN16_Input

#define GPIO_DIRSET_PIN16_Input (0UL)

Pin set as input.

Definition at line 2322 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN16_Msk

#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos)

Bit mask of PIN16 field.

Definition at line 2321 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN16_Output

#define GPIO_DIRSET_PIN16_Output (1UL)

Pin set as output.

Definition at line 2323 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN16_Pos

#define GPIO_DIRSET_PIN16_Pos (16UL)

Position of PIN16 field.

Definition at line 2320 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN16_Set

#define GPIO_DIRSET_PIN16_Set (1UL)

Set pin as output.

Definition at line 2324 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN17_Input

#define GPIO_DIRSET_PIN17_Input (0UL)

Pin set as input.

Definition at line 2315 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN17_Msk

#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos)

Bit mask of PIN17 field.

Definition at line 2314 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN17_Output

#define GPIO_DIRSET_PIN17_Output (1UL)

Pin set as output.

Definition at line 2316 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN17_Pos

#define GPIO_DIRSET_PIN17_Pos (17UL)

Position of PIN17 field.

Definition at line 2313 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN17_Set

#define GPIO_DIRSET_PIN17_Set (1UL)

Set pin as output.

Definition at line 2317 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN18_Input

#define GPIO_DIRSET_PIN18_Input (0UL)

Pin set as input.

Definition at line 2308 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN18_Msk

#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos)

Bit mask of PIN18 field.

Definition at line 2307 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN18_Output

#define GPIO_DIRSET_PIN18_Output (1UL)

Pin set as output.

Definition at line 2309 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN18_Pos

#define GPIO_DIRSET_PIN18_Pos (18UL)

Position of PIN18 field.

Definition at line 2306 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN18_Set

#define GPIO_DIRSET_PIN18_Set (1UL)

Set pin as output.

Definition at line 2310 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN19_Input

#define GPIO_DIRSET_PIN19_Input (0UL)

Pin set as input.

Definition at line 2301 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN19_Msk

#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos)

Bit mask of PIN19 field.

Definition at line 2300 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN19_Output

#define GPIO_DIRSET_PIN19_Output (1UL)

Pin set as output.

Definition at line 2302 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN19_Pos

#define GPIO_DIRSET_PIN19_Pos (19UL)

Position of PIN19 field.

Definition at line 2299 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN19_Set

#define GPIO_DIRSET_PIN19_Set (1UL)

Set pin as output.

Definition at line 2303 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN1_Input

#define GPIO_DIRSET_PIN1_Input (0UL)

Pin set as input.

Definition at line 2427 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN1_Msk

#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos)

Bit mask of PIN1 field.

Definition at line 2426 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN1_Output

#define GPIO_DIRSET_PIN1_Output (1UL)

Pin set as output.

Definition at line 2428 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN1_Pos

#define GPIO_DIRSET_PIN1_Pos (1UL)

Position of PIN1 field.

Definition at line 2425 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN1_Set

#define GPIO_DIRSET_PIN1_Set (1UL)

Set pin as output.

Definition at line 2429 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN20_Input

#define GPIO_DIRSET_PIN20_Input (0UL)

Pin set as input.

Definition at line 2294 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN20_Msk

#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos)

Bit mask of PIN20 field.

Definition at line 2293 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN20_Output

#define GPIO_DIRSET_PIN20_Output (1UL)

Pin set as output.

Definition at line 2295 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN20_Pos

#define GPIO_DIRSET_PIN20_Pos (20UL)

Position of PIN20 field.

Definition at line 2292 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN20_Set

#define GPIO_DIRSET_PIN20_Set (1UL)

Set pin as output.

Definition at line 2296 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN21_Input

#define GPIO_DIRSET_PIN21_Input (0UL)

Pin set as input.

Definition at line 2287 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN21_Msk

#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos)

Bit mask of PIN21 field.

Definition at line 2286 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN21_Output

#define GPIO_DIRSET_PIN21_Output (1UL)

Pin set as output.

Definition at line 2288 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN21_Pos

#define GPIO_DIRSET_PIN21_Pos (21UL)

Position of PIN21 field.

Definition at line 2285 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN21_Set

#define GPIO_DIRSET_PIN21_Set (1UL)

Set pin as output.

Definition at line 2289 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN22_Input

#define GPIO_DIRSET_PIN22_Input (0UL)

Pin set as input.

Definition at line 2280 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN22_Msk

#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos)

Bit mask of PIN22 field.

Definition at line 2279 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN22_Output

#define GPIO_DIRSET_PIN22_Output (1UL)

Pin set as output.

Definition at line 2281 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN22_Pos

#define GPIO_DIRSET_PIN22_Pos (22UL)

Position of PIN22 field.

Definition at line 2278 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN22_Set

#define GPIO_DIRSET_PIN22_Set (1UL)

Set pin as output.

Definition at line 2282 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN23_Input

#define GPIO_DIRSET_PIN23_Input (0UL)

Pin set as input.

Definition at line 2273 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN23_Msk

#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos)

Bit mask of PIN23 field.

Definition at line 2272 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN23_Output

#define GPIO_DIRSET_PIN23_Output (1UL)

Pin set as output.

Definition at line 2274 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN23_Pos

#define GPIO_DIRSET_PIN23_Pos (23UL)

Position of PIN23 field.

Definition at line 2271 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN23_Set

#define GPIO_DIRSET_PIN23_Set (1UL)

Set pin as output.

Definition at line 2275 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN24_Input

#define GPIO_DIRSET_PIN24_Input (0UL)

Pin set as input.

Definition at line 2266 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN24_Msk

#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos)

Bit mask of PIN24 field.

Definition at line 2265 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN24_Output

#define GPIO_DIRSET_PIN24_Output (1UL)

Pin set as output.

Definition at line 2267 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN24_Pos

#define GPIO_DIRSET_PIN24_Pos (24UL)

Position of PIN24 field.

Definition at line 2264 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN24_Set

#define GPIO_DIRSET_PIN24_Set (1UL)

Set pin as output.

Definition at line 2268 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN25_Input

#define GPIO_DIRSET_PIN25_Input (0UL)

Pin set as input.

Definition at line 2259 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN25_Msk

#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos)

Bit mask of PIN25 field.

Definition at line 2258 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN25_Output

#define GPIO_DIRSET_PIN25_Output (1UL)

Pin set as output.

Definition at line 2260 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN25_Pos

#define GPIO_DIRSET_PIN25_Pos (25UL)

Position of PIN25 field.

Definition at line 2257 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN25_Set

#define GPIO_DIRSET_PIN25_Set (1UL)

Set pin as output.

Definition at line 2261 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN26_Input

#define GPIO_DIRSET_PIN26_Input (0UL)

Pin set as input.

Definition at line 2252 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN26_Msk

#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos)

Bit mask of PIN26 field.

Definition at line 2251 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN26_Output

#define GPIO_DIRSET_PIN26_Output (1UL)

Pin set as output.

Definition at line 2253 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN26_Pos

#define GPIO_DIRSET_PIN26_Pos (26UL)

Position of PIN26 field.

Definition at line 2250 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN26_Set

#define GPIO_DIRSET_PIN26_Set (1UL)

Set pin as output.

Definition at line 2254 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN27_Input

#define GPIO_DIRSET_PIN27_Input (0UL)

Pin set as input.

Definition at line 2245 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN27_Msk

#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos)

Bit mask of PIN27 field.

Definition at line 2244 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN27_Output

#define GPIO_DIRSET_PIN27_Output (1UL)

Pin set as output.

Definition at line 2246 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN27_Pos

#define GPIO_DIRSET_PIN27_Pos (27UL)

Position of PIN27 field.

Definition at line 2243 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN27_Set

#define GPIO_DIRSET_PIN27_Set (1UL)

Set pin as output.

Definition at line 2247 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN28_Input

#define GPIO_DIRSET_PIN28_Input (0UL)

Pin set as input.

Definition at line 2238 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN28_Msk

#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos)

Bit mask of PIN28 field.

Definition at line 2237 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN28_Output

#define GPIO_DIRSET_PIN28_Output (1UL)

Pin set as output.

Definition at line 2239 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN28_Pos

#define GPIO_DIRSET_PIN28_Pos (28UL)

Position of PIN28 field.

Definition at line 2236 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN28_Set

#define GPIO_DIRSET_PIN28_Set (1UL)

Set pin as output.

Definition at line 2240 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN29_Input

#define GPIO_DIRSET_PIN29_Input (0UL)

Pin set as input.

Definition at line 2231 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN29_Msk

#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos)

Bit mask of PIN29 field.

Definition at line 2230 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN29_Output

#define GPIO_DIRSET_PIN29_Output (1UL)

Pin set as output.

Definition at line 2232 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN29_Pos

#define GPIO_DIRSET_PIN29_Pos (29UL)

Position of PIN29 field.

Definition at line 2229 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN29_Set

#define GPIO_DIRSET_PIN29_Set (1UL)

Set pin as output.

Definition at line 2233 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN2_Input

#define GPIO_DIRSET_PIN2_Input (0UL)

Pin set as input.

Definition at line 2420 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN2_Msk

#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos)

Bit mask of PIN2 field.

Definition at line 2419 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN2_Output

#define GPIO_DIRSET_PIN2_Output (1UL)

Pin set as output.

Definition at line 2421 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN2_Pos

#define GPIO_DIRSET_PIN2_Pos (2UL)

Position of PIN2 field.

Definition at line 2418 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN2_Set

#define GPIO_DIRSET_PIN2_Set (1UL)

Set pin as output.

Definition at line 2422 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN30_Input

#define GPIO_DIRSET_PIN30_Input (0UL)

Pin set as input.

Definition at line 2224 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN30_Msk

#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos)

Bit mask of PIN30 field.

Definition at line 2223 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN30_Output

#define GPIO_DIRSET_PIN30_Output (1UL)

Pin set as output.

Definition at line 2225 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN30_Pos

#define GPIO_DIRSET_PIN30_Pos (30UL)

Position of PIN30 field.

Definition at line 2222 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN30_Set

#define GPIO_DIRSET_PIN30_Set (1UL)

Set pin as output.

Definition at line 2226 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN31_Input

#define GPIO_DIRSET_PIN31_Input (0UL)

Pin set as input.

Definition at line 2217 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN31_Msk

#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos)

Bit mask of PIN31 field.

Definition at line 2216 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN31_Output

#define GPIO_DIRSET_PIN31_Output (1UL)

Pin set as output.

Definition at line 2218 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN31_Pos

#define GPIO_DIRSET_PIN31_Pos (31UL)

Position of PIN31 field.

Definition at line 2215 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN31_Set

#define GPIO_DIRSET_PIN31_Set (1UL)

Set pin as output.

Definition at line 2219 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN3_Input

#define GPIO_DIRSET_PIN3_Input (0UL)

Pin set as input.

Definition at line 2413 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN3_Msk

#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos)

Bit mask of PIN3 field.

Definition at line 2412 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN3_Output

#define GPIO_DIRSET_PIN3_Output (1UL)

Pin set as output.

Definition at line 2414 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN3_Pos

#define GPIO_DIRSET_PIN3_Pos (3UL)

Position of PIN3 field.

Definition at line 2411 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN3_Set

#define GPIO_DIRSET_PIN3_Set (1UL)

Set pin as output.

Definition at line 2415 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN4_Input

#define GPIO_DIRSET_PIN4_Input (0UL)

Pin set as input.

Definition at line 2406 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN4_Msk

#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos)

Bit mask of PIN4 field.

Definition at line 2405 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN4_Output

#define GPIO_DIRSET_PIN4_Output (1UL)

Pin set as output.

Definition at line 2407 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN4_Pos

#define GPIO_DIRSET_PIN4_Pos (4UL)

Position of PIN4 field.

Definition at line 2404 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN4_Set

#define GPIO_DIRSET_PIN4_Set (1UL)

Set pin as output.

Definition at line 2408 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN5_Input

#define GPIO_DIRSET_PIN5_Input (0UL)

Pin set as input.

Definition at line 2399 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN5_Msk

#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos)

Bit mask of PIN5 field.

Definition at line 2398 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN5_Output

#define GPIO_DIRSET_PIN5_Output (1UL)

Pin set as output.

Definition at line 2400 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN5_Pos

#define GPIO_DIRSET_PIN5_Pos (5UL)

Position of PIN5 field.

Definition at line 2397 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN5_Set

#define GPIO_DIRSET_PIN5_Set (1UL)

Set pin as output.

Definition at line 2401 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN6_Input

#define GPIO_DIRSET_PIN6_Input (0UL)

Pin set as input.

Definition at line 2392 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN6_Msk

#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos)

Bit mask of PIN6 field.

Definition at line 2391 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN6_Output

#define GPIO_DIRSET_PIN6_Output (1UL)

Pin set as output.

Definition at line 2393 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN6_Pos

#define GPIO_DIRSET_PIN6_Pos (6UL)

Position of PIN6 field.

Definition at line 2390 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN6_Set

#define GPIO_DIRSET_PIN6_Set (1UL)

Set pin as output.

Definition at line 2394 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN7_Input

#define GPIO_DIRSET_PIN7_Input (0UL)

Pin set as input.

Definition at line 2385 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN7_Msk

#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos)

Bit mask of PIN7 field.

Definition at line 2384 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN7_Output

#define GPIO_DIRSET_PIN7_Output (1UL)

Pin set as output.

Definition at line 2386 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN7_Pos

#define GPIO_DIRSET_PIN7_Pos (7UL)

Position of PIN7 field.

Definition at line 2383 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN7_Set

#define GPIO_DIRSET_PIN7_Set (1UL)

Set pin as output.

Definition at line 2387 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN8_Input

#define GPIO_DIRSET_PIN8_Input (0UL)

Pin set as input.

Definition at line 2378 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN8_Msk

#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos)

Bit mask of PIN8 field.

Definition at line 2377 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN8_Output

#define GPIO_DIRSET_PIN8_Output (1UL)

Pin set as output.

Definition at line 2379 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN8_Pos

#define GPIO_DIRSET_PIN8_Pos (8UL)

Position of PIN8 field.

Definition at line 2376 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN8_Set

#define GPIO_DIRSET_PIN8_Set (1UL)

Set pin as output.

Definition at line 2380 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN9_Input

#define GPIO_DIRSET_PIN9_Input (0UL)

Pin set as input.

Definition at line 2371 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN9_Msk

#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos)

Bit mask of PIN9 field.

Definition at line 2370 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN9_Output

#define GPIO_DIRSET_PIN9_Output (1UL)

Pin set as output.

Definition at line 2372 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN9_Pos

#define GPIO_DIRSET_PIN9_Pos (9UL)

Position of PIN9 field.

Definition at line 2369 of file nrf51_bitfields.h.

◆ GPIO_DIRSET_PIN9_Set

#define GPIO_DIRSET_PIN9_Set (1UL)

Set pin as output.

Definition at line 2373 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN0_High

#define GPIO_IN_PIN0_High (1UL)

Pin input is high.

Definition at line 2014 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN0_Low

#define GPIO_IN_PIN0_Low (0UL)

Pin input is low.

Definition at line 2013 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN0_Msk

#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos)

Bit mask of PIN0 field.

Definition at line 2012 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN0_Pos

#define GPIO_IN_PIN0_Pos (0UL)

Position of PIN0 field.

Definition at line 2011 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN10_High

#define GPIO_IN_PIN10_High (1UL)

Pin input is high.

Definition at line 1954 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN10_Low

#define GPIO_IN_PIN10_Low (0UL)

Pin input is low.

Definition at line 1953 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN10_Msk

#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos)

Bit mask of PIN10 field.

Definition at line 1952 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN10_Pos

#define GPIO_IN_PIN10_Pos (10UL)

Position of PIN10 field.

Definition at line 1951 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN11_High

#define GPIO_IN_PIN11_High (1UL)

Pin input is high.

Definition at line 1948 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN11_Low

#define GPIO_IN_PIN11_Low (0UL)

Pin input is low.

Definition at line 1947 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN11_Msk

#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos)

Bit mask of PIN11 field.

Definition at line 1946 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN11_Pos

#define GPIO_IN_PIN11_Pos (11UL)

Position of PIN11 field.

Definition at line 1945 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN12_High

#define GPIO_IN_PIN12_High (1UL)

Pin input is high.

Definition at line 1942 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN12_Low

#define GPIO_IN_PIN12_Low (0UL)

Pin input is low.

Definition at line 1941 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN12_Msk

#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos)

Bit mask of PIN12 field.

Definition at line 1940 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN12_Pos

#define GPIO_IN_PIN12_Pos (12UL)

Position of PIN12 field.

Definition at line 1939 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN13_High

#define GPIO_IN_PIN13_High (1UL)

Pin input is high.

Definition at line 1936 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN13_Low

#define GPIO_IN_PIN13_Low (0UL)

Pin input is low.

Definition at line 1935 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN13_Msk

#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos)

Bit mask of PIN13 field.

Definition at line 1934 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN13_Pos

#define GPIO_IN_PIN13_Pos (13UL)

Position of PIN13 field.

Definition at line 1933 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN14_High

#define GPIO_IN_PIN14_High (1UL)

Pin input is high.

Definition at line 1930 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN14_Low

#define GPIO_IN_PIN14_Low (0UL)

Pin input is low.

Definition at line 1929 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN14_Msk

#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos)

Bit mask of PIN14 field.

Definition at line 1928 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN14_Pos

#define GPIO_IN_PIN14_Pos (14UL)

Position of PIN14 field.

Definition at line 1927 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN15_High

#define GPIO_IN_PIN15_High (1UL)

Pin input is high.

Definition at line 1924 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN15_Low

#define GPIO_IN_PIN15_Low (0UL)

Pin input is low.

Definition at line 1923 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN15_Msk

#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos)

Bit mask of PIN15 field.

Definition at line 1922 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN15_Pos

#define GPIO_IN_PIN15_Pos (15UL)

Position of PIN15 field.

Definition at line 1921 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN16_High

#define GPIO_IN_PIN16_High (1UL)

Pin input is high.

Definition at line 1918 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN16_Low

#define GPIO_IN_PIN16_Low (0UL)

Pin input is low.

Definition at line 1917 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN16_Msk

#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos)

Bit mask of PIN16 field.

Definition at line 1916 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN16_Pos

#define GPIO_IN_PIN16_Pos (16UL)

Position of PIN16 field.

Definition at line 1915 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN17_High

#define GPIO_IN_PIN17_High (1UL)

Pin input is high.

Definition at line 1912 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN17_Low

#define GPIO_IN_PIN17_Low (0UL)

Pin input is low.

Definition at line 1911 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN17_Msk

#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos)

Bit mask of PIN17 field.

Definition at line 1910 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN17_Pos

#define GPIO_IN_PIN17_Pos (17UL)

Position of PIN17 field.

Definition at line 1909 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN18_High

#define GPIO_IN_PIN18_High (1UL)

Pin input is high.

Definition at line 1906 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN18_Low

#define GPIO_IN_PIN18_Low (0UL)

Pin input is low.

Definition at line 1905 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN18_Msk

#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos)

Bit mask of PIN18 field.

Definition at line 1904 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN18_Pos

#define GPIO_IN_PIN18_Pos (18UL)

Position of PIN18 field.

Definition at line 1903 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN19_High

#define GPIO_IN_PIN19_High (1UL)

Pin input is high.

Definition at line 1900 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN19_Low

#define GPIO_IN_PIN19_Low (0UL)

Pin input is low.

Definition at line 1899 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN19_Msk

#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos)

Bit mask of PIN19 field.

Definition at line 1898 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN19_Pos

#define GPIO_IN_PIN19_Pos (19UL)

Position of PIN19 field.

Definition at line 1897 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN1_High

#define GPIO_IN_PIN1_High (1UL)

Pin input is high.

Definition at line 2008 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN1_Low

#define GPIO_IN_PIN1_Low (0UL)

Pin input is low.

Definition at line 2007 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN1_Msk

#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos)

Bit mask of PIN1 field.

Definition at line 2006 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN1_Pos

#define GPIO_IN_PIN1_Pos (1UL)

Position of PIN1 field.

Definition at line 2005 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN20_High

#define GPIO_IN_PIN20_High (1UL)

Pin input is high.

Definition at line 1894 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN20_Low

#define GPIO_IN_PIN20_Low (0UL)

Pin input is low.

Definition at line 1893 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN20_Msk

#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos)

Bit mask of PIN20 field.

Definition at line 1892 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN20_Pos

#define GPIO_IN_PIN20_Pos (20UL)

Position of PIN20 field.

Definition at line 1891 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN21_High

#define GPIO_IN_PIN21_High (1UL)

Pin input is high.

Definition at line 1888 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN21_Low

#define GPIO_IN_PIN21_Low (0UL)

Pin input is low.

Definition at line 1887 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN21_Msk

#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos)

Bit mask of PIN21 field.

Definition at line 1886 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN21_Pos

#define GPIO_IN_PIN21_Pos (21UL)

Position of PIN21 field.

Definition at line 1885 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN22_High

#define GPIO_IN_PIN22_High (1UL)

Pin input is high.

Definition at line 1882 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN22_Low

#define GPIO_IN_PIN22_Low (0UL)

Pin input is low.

Definition at line 1881 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN22_Msk

#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos)

Bit mask of PIN22 field.

Definition at line 1880 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN22_Pos

#define GPIO_IN_PIN22_Pos (22UL)

Position of PIN22 field.

Definition at line 1879 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN23_High

#define GPIO_IN_PIN23_High (1UL)

Pin input is high.

Definition at line 1876 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN23_Low

#define GPIO_IN_PIN23_Low (0UL)

Pin input is low.

Definition at line 1875 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN23_Msk

#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos)

Bit mask of PIN23 field.

Definition at line 1874 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN23_Pos

#define GPIO_IN_PIN23_Pos (23UL)

Position of PIN23 field.

Definition at line 1873 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN24_High

#define GPIO_IN_PIN24_High (1UL)

Pin input is high.

Definition at line 1870 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN24_Low

#define GPIO_IN_PIN24_Low (0UL)

Pin input is low.

Definition at line 1869 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN24_Msk

#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos)

Bit mask of PIN24 field.

Definition at line 1868 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN24_Pos

#define GPIO_IN_PIN24_Pos (24UL)

Position of PIN24 field.

Definition at line 1867 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN25_High

#define GPIO_IN_PIN25_High (1UL)

Pin input is high.

Definition at line 1864 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN25_Low

#define GPIO_IN_PIN25_Low (0UL)

Pin input is low.

Definition at line 1863 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN25_Msk

#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos)

Bit mask of PIN25 field.

Definition at line 1862 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN25_Pos

#define GPIO_IN_PIN25_Pos (25UL)

Position of PIN25 field.

Definition at line 1861 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN26_High

#define GPIO_IN_PIN26_High (1UL)

Pin input is high.

Definition at line 1858 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN26_Low

#define GPIO_IN_PIN26_Low (0UL)

Pin input is low.

Definition at line 1857 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN26_Msk

#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos)

Bit mask of PIN26 field.

Definition at line 1856 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN26_Pos

#define GPIO_IN_PIN26_Pos (26UL)

Position of PIN26 field.

Definition at line 1855 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN27_High

#define GPIO_IN_PIN27_High (1UL)

Pin input is high.

Definition at line 1852 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN27_Low

#define GPIO_IN_PIN27_Low (0UL)

Pin input is low.

Definition at line 1851 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN27_Msk

#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos)

Bit mask of PIN27 field.

Definition at line 1850 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN27_Pos

#define GPIO_IN_PIN27_Pos (27UL)

Position of PIN27 field.

Definition at line 1849 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN28_High

#define GPIO_IN_PIN28_High (1UL)

Pin input is high.

Definition at line 1846 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN28_Low

#define GPIO_IN_PIN28_Low (0UL)

Pin input is low.

Definition at line 1845 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN28_Msk

#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos)

Bit mask of PIN28 field.

Definition at line 1844 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN28_Pos

#define GPIO_IN_PIN28_Pos (28UL)

Position of PIN28 field.

Definition at line 1843 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN29_High

#define GPIO_IN_PIN29_High (1UL)

Pin input is high.

Definition at line 1840 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN29_Low

#define GPIO_IN_PIN29_Low (0UL)

Pin input is low.

Definition at line 1839 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN29_Msk

#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos)

Bit mask of PIN29 field.

Definition at line 1838 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN29_Pos

#define GPIO_IN_PIN29_Pos (29UL)

Position of PIN29 field.

Definition at line 1837 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN2_High

#define GPIO_IN_PIN2_High (1UL)

Pin input is high.

Definition at line 2002 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN2_Low

#define GPIO_IN_PIN2_Low (0UL)

Pin input is low.

Definition at line 2001 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN2_Msk

#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos)

Bit mask of PIN2 field.

Definition at line 2000 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN2_Pos

#define GPIO_IN_PIN2_Pos (2UL)

Position of PIN2 field.

Definition at line 1999 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN30_High

#define GPIO_IN_PIN30_High (1UL)

Pin input is high.

Definition at line 1834 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN30_Low

#define GPIO_IN_PIN30_Low (0UL)

Pin input is low.

Definition at line 1833 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN30_Msk

#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos)

Bit mask of PIN30 field.

Definition at line 1832 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN30_Pos

#define GPIO_IN_PIN30_Pos (30UL)

Position of PIN30 field.

Definition at line 1831 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN31_High

#define GPIO_IN_PIN31_High (1UL)

Pin input is high.

Definition at line 1828 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN31_Low

#define GPIO_IN_PIN31_Low (0UL)

Pin input is low.

Definition at line 1827 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN31_Msk

#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos)

Bit mask of PIN31 field.

Definition at line 1826 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN31_Pos

#define GPIO_IN_PIN31_Pos (31UL)

Position of PIN31 field.

Definition at line 1825 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN3_High

#define GPIO_IN_PIN3_High (1UL)

Pin input is high.

Definition at line 1996 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN3_Low

#define GPIO_IN_PIN3_Low (0UL)

Pin input is low.

Definition at line 1995 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN3_Msk

#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos)

Bit mask of PIN3 field.

Definition at line 1994 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN3_Pos

#define GPIO_IN_PIN3_Pos (3UL)

Position of PIN3 field.

Definition at line 1993 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN4_High

#define GPIO_IN_PIN4_High (1UL)

Pin input is high.

Definition at line 1990 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN4_Low

#define GPIO_IN_PIN4_Low (0UL)

Pin input is low.

Definition at line 1989 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN4_Msk

#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos)

Bit mask of PIN4 field.

Definition at line 1988 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN4_Pos

#define GPIO_IN_PIN4_Pos (4UL)

Position of PIN4 field.

Definition at line 1987 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN5_High

#define GPIO_IN_PIN5_High (1UL)

Pin input is high.

Definition at line 1984 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN5_Low

#define GPIO_IN_PIN5_Low (0UL)

Pin input is low.

Definition at line 1983 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN5_Msk

#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos)

Bit mask of PIN5 field.

Definition at line 1982 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN5_Pos

#define GPIO_IN_PIN5_Pos (5UL)

Position of PIN5 field.

Definition at line 1981 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN6_High

#define GPIO_IN_PIN6_High (1UL)

Pin input is high.

Definition at line 1978 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN6_Low

#define GPIO_IN_PIN6_Low (0UL)

Pin input is low.

Definition at line 1977 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN6_Msk

#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos)

Bit mask of PIN6 field.

Definition at line 1976 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN6_Pos

#define GPIO_IN_PIN6_Pos (6UL)

Position of PIN6 field.

Definition at line 1975 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN7_High

#define GPIO_IN_PIN7_High (1UL)

Pin input is high.

Definition at line 1972 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN7_Low

#define GPIO_IN_PIN7_Low (0UL)

Pin input is low.

Definition at line 1971 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN7_Msk

#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos)

Bit mask of PIN7 field.

Definition at line 1970 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN7_Pos

#define GPIO_IN_PIN7_Pos (7UL)

Position of PIN7 field.

Definition at line 1969 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN8_High

#define GPIO_IN_PIN8_High (1UL)

Pin input is high.

Definition at line 1966 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN8_Low

#define GPIO_IN_PIN8_Low (0UL)

Pin input is low.

Definition at line 1965 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN8_Msk

#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos)

Bit mask of PIN8 field.

Definition at line 1964 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN8_Pos

#define GPIO_IN_PIN8_Pos (8UL)

Position of PIN8 field.

Definition at line 1963 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN9_High

#define GPIO_IN_PIN9_High (1UL)

Pin input is high.

Definition at line 1960 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN9_Low

#define GPIO_IN_PIN9_Low (0UL)

Pin input is low.

Definition at line 1959 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN9_Msk

#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos)

Bit mask of PIN9 field.

Definition at line 1958 of file nrf51_bitfields.h.

◆ GPIO_IN_PIN9_Pos

#define GPIO_IN_PIN9_Pos (9UL)

Position of PIN9 field.

Definition at line 1957 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN0_High

#define GPIO_OUT_PIN0_High (1UL)

Pin driver is high.

Definition at line 1365 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN0_Low

#define GPIO_OUT_PIN0_Low (0UL)

Pin driver is low.

Definition at line 1364 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN0_Msk

#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos)

Bit mask of PIN0 field.

Definition at line 1363 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN0_Pos

#define GPIO_OUT_PIN0_Pos (0UL)

Position of PIN0 field.

Definition at line 1362 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN10_High

#define GPIO_OUT_PIN10_High (1UL)

Pin driver is high.

Definition at line 1305 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN10_Low

#define GPIO_OUT_PIN10_Low (0UL)

Pin driver is low.

Definition at line 1304 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN10_Msk

#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos)

Bit mask of PIN10 field.

Definition at line 1303 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN10_Pos

#define GPIO_OUT_PIN10_Pos (10UL)

Position of PIN10 field.

Definition at line 1302 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN11_High

#define GPIO_OUT_PIN11_High (1UL)

Pin driver is high.

Definition at line 1299 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN11_Low

#define GPIO_OUT_PIN11_Low (0UL)

Pin driver is low.

Definition at line 1298 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN11_Msk

#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos)

Bit mask of PIN11 field.

Definition at line 1297 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN11_Pos

#define GPIO_OUT_PIN11_Pos (11UL)

Position of PIN11 field.

Definition at line 1296 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN12_High

#define GPIO_OUT_PIN12_High (1UL)

Pin driver is high.

Definition at line 1293 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN12_Low

#define GPIO_OUT_PIN12_Low (0UL)

Pin driver is low.

Definition at line 1292 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN12_Msk

#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos)

Bit mask of PIN12 field.

Definition at line 1291 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN12_Pos

#define GPIO_OUT_PIN12_Pos (12UL)

Position of PIN12 field.

Definition at line 1290 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN13_High

#define GPIO_OUT_PIN13_High (1UL)

Pin driver is high.

Definition at line 1287 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN13_Low

#define GPIO_OUT_PIN13_Low (0UL)

Pin driver is low.

Definition at line 1286 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN13_Msk

#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos)

Bit mask of PIN13 field.

Definition at line 1285 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN13_Pos

#define GPIO_OUT_PIN13_Pos (13UL)

Position of PIN13 field.

Definition at line 1284 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN14_High

#define GPIO_OUT_PIN14_High (1UL)

Pin driver is high.

Definition at line 1281 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN14_Low

#define GPIO_OUT_PIN14_Low (0UL)

Pin driver is low.

Definition at line 1280 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN14_Msk

#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos)

Bit mask of PIN14 field.

Definition at line 1279 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN14_Pos

#define GPIO_OUT_PIN14_Pos (14UL)

Position of PIN14 field.

Definition at line 1278 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN15_High

#define GPIO_OUT_PIN15_High (1UL)

Pin driver is high.

Definition at line 1275 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN15_Low

#define GPIO_OUT_PIN15_Low (0UL)

Pin driver is low.

Definition at line 1274 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN15_Msk

#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos)

Bit mask of PIN15 field.

Definition at line 1273 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN15_Pos

#define GPIO_OUT_PIN15_Pos (15UL)

Position of PIN15 field.

Definition at line 1272 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN16_High

#define GPIO_OUT_PIN16_High (1UL)

Pin driver is high.

Definition at line 1269 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN16_Low

#define GPIO_OUT_PIN16_Low (0UL)

Pin driver is low.

Definition at line 1268 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN16_Msk

#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos)

Bit mask of PIN16 field.

Definition at line 1267 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN16_Pos

#define GPIO_OUT_PIN16_Pos (16UL)

Position of PIN16 field.

Definition at line 1266 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN17_High

#define GPIO_OUT_PIN17_High (1UL)

Pin driver is high.

Definition at line 1263 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN17_Low

#define GPIO_OUT_PIN17_Low (0UL)

Pin driver is low.

Definition at line 1262 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN17_Msk

#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos)

Bit mask of PIN17 field.

Definition at line 1261 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN17_Pos

#define GPIO_OUT_PIN17_Pos (17UL)

Position of PIN17 field.

Definition at line 1260 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN18_High

#define GPIO_OUT_PIN18_High (1UL)

Pin driver is high.

Definition at line 1257 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN18_Low

#define GPIO_OUT_PIN18_Low (0UL)

Pin driver is low.

Definition at line 1256 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN18_Msk

#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos)

Bit mask of PIN18 field.

Definition at line 1255 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN18_Pos

#define GPIO_OUT_PIN18_Pos (18UL)

Position of PIN18 field.

Definition at line 1254 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN19_High

#define GPIO_OUT_PIN19_High (1UL)

Pin driver is high.

Definition at line 1251 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN19_Low

#define GPIO_OUT_PIN19_Low (0UL)

Pin driver is low.

Definition at line 1250 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN19_Msk

#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos)

Bit mask of PIN19 field.

Definition at line 1249 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN19_Pos

#define GPIO_OUT_PIN19_Pos (19UL)

Position of PIN19 field.

Definition at line 1248 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN1_High

#define GPIO_OUT_PIN1_High (1UL)

Pin driver is high.

Definition at line 1359 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN1_Low

#define GPIO_OUT_PIN1_Low (0UL)

Pin driver is low.

Definition at line 1358 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN1_Msk

#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos)

Bit mask of PIN1 field.

Definition at line 1357 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN1_Pos

#define GPIO_OUT_PIN1_Pos (1UL)

Position of PIN1 field.

Definition at line 1356 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN20_High

#define GPIO_OUT_PIN20_High (1UL)

Pin driver is high.

Definition at line 1245 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN20_Low

#define GPIO_OUT_PIN20_Low (0UL)

Pin driver is low.

Definition at line 1244 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN20_Msk

#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos)

Bit mask of PIN20 field.

Definition at line 1243 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN20_Pos

#define GPIO_OUT_PIN20_Pos (20UL)

Position of PIN20 field.

Definition at line 1242 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN21_High

#define GPIO_OUT_PIN21_High (1UL)

Pin driver is high.

Definition at line 1239 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN21_Low

#define GPIO_OUT_PIN21_Low (0UL)

Pin driver is low.

Definition at line 1238 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN21_Msk

#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos)

Bit mask of PIN21 field.

Definition at line 1237 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN21_Pos

#define GPIO_OUT_PIN21_Pos (21UL)

Position of PIN21 field.

Definition at line 1236 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN22_High

#define GPIO_OUT_PIN22_High (1UL)

Pin driver is high.

Definition at line 1233 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN22_Low

#define GPIO_OUT_PIN22_Low (0UL)

Pin driver is low.

Definition at line 1232 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN22_Msk

#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos)

Bit mask of PIN22 field.

Definition at line 1231 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN22_Pos

#define GPIO_OUT_PIN22_Pos (22UL)

Position of PIN22 field.

Definition at line 1230 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN23_High

#define GPIO_OUT_PIN23_High (1UL)

Pin driver is high.

Definition at line 1227 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN23_Low

#define GPIO_OUT_PIN23_Low (0UL)

Pin driver is low.

Definition at line 1226 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN23_Msk

#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos)

Bit mask of PIN23 field.

Definition at line 1225 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN23_Pos

#define GPIO_OUT_PIN23_Pos (23UL)

Position of PIN23 field.

Definition at line 1224 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN24_High

#define GPIO_OUT_PIN24_High (1UL)

Pin driver is high.

Definition at line 1221 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN24_Low

#define GPIO_OUT_PIN24_Low (0UL)

Pin driver is low.

Definition at line 1220 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN24_Msk

#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos)

Bit mask of PIN24 field.

Definition at line 1219 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN24_Pos

#define GPIO_OUT_PIN24_Pos (24UL)

Position of PIN24 field.

Definition at line 1218 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN25_High

#define GPIO_OUT_PIN25_High (1UL)

Pin driver is high.

Definition at line 1215 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN25_Low

#define GPIO_OUT_PIN25_Low (0UL)

Pin driver is low.

Definition at line 1214 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN25_Msk

#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos)

Bit mask of PIN25 field.

Definition at line 1213 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN25_Pos

#define GPIO_OUT_PIN25_Pos (25UL)

Position of PIN25 field.

Definition at line 1212 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN26_High

#define GPIO_OUT_PIN26_High (1UL)

Pin driver is high.

Definition at line 1209 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN26_Low

#define GPIO_OUT_PIN26_Low (0UL)

Pin driver is low.

Definition at line 1208 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN26_Msk

#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos)

Bit mask of PIN26 field.

Definition at line 1207 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN26_Pos

#define GPIO_OUT_PIN26_Pos (26UL)

Position of PIN26 field.

Definition at line 1206 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN27_High

#define GPIO_OUT_PIN27_High (1UL)

Pin driver is high.

Definition at line 1203 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN27_Low

#define GPIO_OUT_PIN27_Low (0UL)

Pin driver is low.

Definition at line 1202 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN27_Msk

#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos)

Bit mask of PIN27 field.

Definition at line 1201 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN27_Pos

#define GPIO_OUT_PIN27_Pos (27UL)

Position of PIN27 field.

Definition at line 1200 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN28_High

#define GPIO_OUT_PIN28_High (1UL)

Pin driver is high.

Definition at line 1197 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN28_Low

#define GPIO_OUT_PIN28_Low (0UL)

Pin driver is low.

Definition at line 1196 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN28_Msk

#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos)

Bit mask of PIN28 field.

Definition at line 1195 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN28_Pos

#define GPIO_OUT_PIN28_Pos (28UL)

Position of PIN28 field.

Definition at line 1194 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN29_High

#define GPIO_OUT_PIN29_High (1UL)

Pin driver is high.

Definition at line 1191 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN29_Low

#define GPIO_OUT_PIN29_Low (0UL)

Pin driver is low.

Definition at line 1190 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN29_Msk

#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos)

Bit mask of PIN29 field.

Definition at line 1189 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN29_Pos

#define GPIO_OUT_PIN29_Pos (29UL)

Position of PIN29 field.

Definition at line 1188 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN2_High

#define GPIO_OUT_PIN2_High (1UL)

Pin driver is high.

Definition at line 1353 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN2_Low

#define GPIO_OUT_PIN2_Low (0UL)

Pin driver is low.

Definition at line 1352 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN2_Msk

#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos)

Bit mask of PIN2 field.

Definition at line 1351 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN2_Pos

#define GPIO_OUT_PIN2_Pos (2UL)

Position of PIN2 field.

Definition at line 1350 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN30_High

#define GPIO_OUT_PIN30_High (1UL)

Pin driver is high.

Definition at line 1185 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN30_Low

#define GPIO_OUT_PIN30_Low (0UL)

Pin driver is low.

Definition at line 1184 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN30_Msk

#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos)

Bit mask of PIN30 field.

Definition at line 1183 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN30_Pos

#define GPIO_OUT_PIN30_Pos (30UL)

Position of PIN30 field.

Definition at line 1182 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN31_High

#define GPIO_OUT_PIN31_High (1UL)

Pin driver is high.

Definition at line 1179 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN31_Low

#define GPIO_OUT_PIN31_Low (0UL)

Pin driver is low.

Definition at line 1178 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN31_Msk

#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos)

Bit mask of PIN31 field.

Definition at line 1177 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN31_Pos

#define GPIO_OUT_PIN31_Pos (31UL)

Position of PIN31 field.

Definition at line 1176 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN3_High

#define GPIO_OUT_PIN3_High (1UL)

Pin driver is high.

Definition at line 1347 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN3_Low

#define GPIO_OUT_PIN3_Low (0UL)

Pin driver is low.

Definition at line 1346 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN3_Msk

#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos)

Bit mask of PIN3 field.

Definition at line 1345 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN3_Pos

#define GPIO_OUT_PIN3_Pos (3UL)

Position of PIN3 field.

Definition at line 1344 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN4_High

#define GPIO_OUT_PIN4_High (1UL)

Pin driver is high.

Definition at line 1341 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN4_Low

#define GPIO_OUT_PIN4_Low (0UL)

Pin driver is low.

Definition at line 1340 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN4_Msk

#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos)

Bit mask of PIN4 field.

Definition at line 1339 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN4_Pos

#define GPIO_OUT_PIN4_Pos (4UL)

Position of PIN4 field.

Definition at line 1338 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN5_High

#define GPIO_OUT_PIN5_High (1UL)

Pin driver is high.

Definition at line 1335 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN5_Low

#define GPIO_OUT_PIN5_Low (0UL)

Pin driver is low.

Definition at line 1334 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN5_Msk

#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos)

Bit mask of PIN5 field.

Definition at line 1333 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN5_Pos

#define GPIO_OUT_PIN5_Pos (5UL)

Position of PIN5 field.

Definition at line 1332 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN6_High

#define GPIO_OUT_PIN6_High (1UL)

Pin driver is high.

Definition at line 1329 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN6_Low

#define GPIO_OUT_PIN6_Low (0UL)

Pin driver is low.

Definition at line 1328 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN6_Msk

#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos)

Bit mask of PIN6 field.

Definition at line 1327 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN6_Pos

#define GPIO_OUT_PIN6_Pos (6UL)

Position of PIN6 field.

Definition at line 1326 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN7_High

#define GPIO_OUT_PIN7_High (1UL)

Pin driver is high.

Definition at line 1323 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN7_Low

#define GPIO_OUT_PIN7_Low (0UL)

Pin driver is low.

Definition at line 1322 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN7_Msk

#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos)

Bit mask of PIN7 field.

Definition at line 1321 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN7_Pos

#define GPIO_OUT_PIN7_Pos (7UL)

Position of PIN7 field.

Definition at line 1320 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN8_High

#define GPIO_OUT_PIN8_High (1UL)

Pin driver is high.

Definition at line 1317 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN8_Low

#define GPIO_OUT_PIN8_Low (0UL)

Pin driver is low.

Definition at line 1316 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN8_Msk

#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos)

Bit mask of PIN8 field.

Definition at line 1315 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN8_Pos

#define GPIO_OUT_PIN8_Pos (8UL)

Position of PIN8 field.

Definition at line 1314 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN9_High

#define GPIO_OUT_PIN9_High (1UL)

Pin driver is high.

Definition at line 1311 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN9_Low

#define GPIO_OUT_PIN9_Low (0UL)

Pin driver is low.

Definition at line 1310 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN9_Msk

#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos)

Bit mask of PIN9 field.

Definition at line 1309 of file nrf51_bitfields.h.

◆ GPIO_OUT_PIN9_Pos

#define GPIO_OUT_PIN9_Pos (9UL)

Position of PIN9 field.

Definition at line 1308 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN0_Clear

#define GPIO_OUTCLR_PIN0_Clear (1UL)

Set pin driver low.

Definition at line 1819 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN0_High

#define GPIO_OUTCLR_PIN0_High (1UL)

Pin driver is high.

Definition at line 1818 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN0_Low

#define GPIO_OUTCLR_PIN0_Low (0UL)

Pin driver is low.

Definition at line 1817 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN0_Msk

#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos)

Bit mask of PIN0 field.

Definition at line 1816 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN0_Pos

#define GPIO_OUTCLR_PIN0_Pos (0UL)

Position of PIN0 field.

Definition at line 1815 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN10_Clear

#define GPIO_OUTCLR_PIN10_Clear (1UL)

Set pin driver low.

Definition at line 1749 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN10_High

#define GPIO_OUTCLR_PIN10_High (1UL)

Pin driver is high.

Definition at line 1748 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN10_Low

#define GPIO_OUTCLR_PIN10_Low (0UL)

Pin driver is low.

Definition at line 1747 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN10_Msk

#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos)

Bit mask of PIN10 field.

Definition at line 1746 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN10_Pos

#define GPIO_OUTCLR_PIN10_Pos (10UL)

Position of PIN10 field.

Definition at line 1745 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN11_Clear

#define GPIO_OUTCLR_PIN11_Clear (1UL)

Set pin driver low.

Definition at line 1742 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN11_High

#define GPIO_OUTCLR_PIN11_High (1UL)

Pin driver is high.

Definition at line 1741 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN11_Low

#define GPIO_OUTCLR_PIN11_Low (0UL)

Pin driver is low.

Definition at line 1740 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN11_Msk

#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos)

Bit mask of PIN11 field.

Definition at line 1739 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN11_Pos

#define GPIO_OUTCLR_PIN11_Pos (11UL)

Position of PIN11 field.

Definition at line 1738 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN12_Clear

#define GPIO_OUTCLR_PIN12_Clear (1UL)

Set pin driver low.

Definition at line 1735 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN12_High

#define GPIO_OUTCLR_PIN12_High (1UL)

Pin driver is high.

Definition at line 1734 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN12_Low

#define GPIO_OUTCLR_PIN12_Low (0UL)

Pin driver is low.

Definition at line 1733 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN12_Msk

#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos)

Bit mask of PIN12 field.

Definition at line 1732 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN12_Pos

#define GPIO_OUTCLR_PIN12_Pos (12UL)

Position of PIN12 field.

Definition at line 1731 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN13_Clear

#define GPIO_OUTCLR_PIN13_Clear (1UL)

Set pin driver low.

Definition at line 1728 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN13_High

#define GPIO_OUTCLR_PIN13_High (1UL)

Pin driver is high.

Definition at line 1727 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN13_Low

#define GPIO_OUTCLR_PIN13_Low (0UL)

Pin driver is low.

Definition at line 1726 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN13_Msk

#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos)

Bit mask of PIN13 field.

Definition at line 1725 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN13_Pos

#define GPIO_OUTCLR_PIN13_Pos (13UL)

Position of PIN13 field.

Definition at line 1724 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN14_Clear

#define GPIO_OUTCLR_PIN14_Clear (1UL)

Set pin driver low.

Definition at line 1721 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN14_High

#define GPIO_OUTCLR_PIN14_High (1UL)

Pin driver is high.

Definition at line 1720 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN14_Low

#define GPIO_OUTCLR_PIN14_Low (0UL)

Pin driver is low.

Definition at line 1719 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN14_Msk

#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos)

Bit mask of PIN14 field.

Definition at line 1718 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN14_Pos

#define GPIO_OUTCLR_PIN14_Pos (14UL)

Position of PIN14 field.

Definition at line 1717 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN15_Clear

#define GPIO_OUTCLR_PIN15_Clear (1UL)

Set pin driver low.

Definition at line 1714 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN15_High

#define GPIO_OUTCLR_PIN15_High (1UL)

Pin driver is high.

Definition at line 1713 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN15_Low

#define GPIO_OUTCLR_PIN15_Low (0UL)

Pin driver is low.

Definition at line 1712 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN15_Msk

#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos)

Bit mask of PIN15 field.

Definition at line 1711 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN15_Pos

#define GPIO_OUTCLR_PIN15_Pos (15UL)

Position of PIN15 field.

Definition at line 1710 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN16_Clear

#define GPIO_OUTCLR_PIN16_Clear (1UL)

Set pin driver low.

Definition at line 1707 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN16_High

#define GPIO_OUTCLR_PIN16_High (1UL)

Pin driver is high.

Definition at line 1706 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN16_Low

#define GPIO_OUTCLR_PIN16_Low (0UL)

Pin driver is low.

Definition at line 1705 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN16_Msk

#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos)

Bit mask of PIN16 field.

Definition at line 1704 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN16_Pos

#define GPIO_OUTCLR_PIN16_Pos (16UL)

Position of PIN16 field.

Definition at line 1703 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN17_Clear

#define GPIO_OUTCLR_PIN17_Clear (1UL)

Set pin driver low.

Definition at line 1700 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN17_High

#define GPIO_OUTCLR_PIN17_High (1UL)

Pin driver is high.

Definition at line 1699 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN17_Low

#define GPIO_OUTCLR_PIN17_Low (0UL)

Pin driver is low.

Definition at line 1698 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN17_Msk

#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos)

Bit mask of PIN17 field.

Definition at line 1697 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN17_Pos

#define GPIO_OUTCLR_PIN17_Pos (17UL)

Position of PIN17 field.

Definition at line 1696 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN18_Clear

#define GPIO_OUTCLR_PIN18_Clear (1UL)

Set pin driver low.

Definition at line 1693 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN18_High

#define GPIO_OUTCLR_PIN18_High (1UL)

Pin driver is high.

Definition at line 1692 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN18_Low

#define GPIO_OUTCLR_PIN18_Low (0UL)

Pin driver is low.

Definition at line 1691 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN18_Msk

#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos)

Bit mask of PIN18 field.

Definition at line 1690 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN18_Pos

#define GPIO_OUTCLR_PIN18_Pos (18UL)

Position of PIN18 field.

Definition at line 1689 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN19_Clear

#define GPIO_OUTCLR_PIN19_Clear (1UL)

Set pin driver low.

Definition at line 1686 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN19_High

#define GPIO_OUTCLR_PIN19_High (1UL)

Pin driver is high.

Definition at line 1685 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN19_Low

#define GPIO_OUTCLR_PIN19_Low (0UL)

Pin driver is low.

Definition at line 1684 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN19_Msk

#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos)

Bit mask of PIN19 field.

Definition at line 1683 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN19_Pos

#define GPIO_OUTCLR_PIN19_Pos (19UL)

Position of PIN19 field.

Definition at line 1682 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN1_Clear

#define GPIO_OUTCLR_PIN1_Clear (1UL)

Set pin driver low.

Definition at line 1812 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN1_High

#define GPIO_OUTCLR_PIN1_High (1UL)

Pin driver is high.

Definition at line 1811 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN1_Low

#define GPIO_OUTCLR_PIN1_Low (0UL)

Pin driver is low.

Definition at line 1810 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN1_Msk

#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos)

Bit mask of PIN1 field.

Definition at line 1809 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN1_Pos

#define GPIO_OUTCLR_PIN1_Pos (1UL)

Position of PIN1 field.

Definition at line 1808 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN20_Clear

#define GPIO_OUTCLR_PIN20_Clear (1UL)

Set pin driver low.

Definition at line 1679 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN20_High

#define GPIO_OUTCLR_PIN20_High (1UL)

Pin driver is high.

Definition at line 1678 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN20_Low

#define GPIO_OUTCLR_PIN20_Low (0UL)

Pin driver is low.

Definition at line 1677 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN20_Msk

#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos)

Bit mask of PIN20 field.

Definition at line 1676 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN20_Pos

#define GPIO_OUTCLR_PIN20_Pos (20UL)

Position of PIN20 field.

Definition at line 1675 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN21_Clear

#define GPIO_OUTCLR_PIN21_Clear (1UL)

Set pin driver low.

Definition at line 1672 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN21_High

#define GPIO_OUTCLR_PIN21_High (1UL)

Pin driver is high.

Definition at line 1671 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN21_Low

#define GPIO_OUTCLR_PIN21_Low (0UL)

Pin driver is low.

Definition at line 1670 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN21_Msk

#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos)

Bit mask of PIN21 field.

Definition at line 1669 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN21_Pos

#define GPIO_OUTCLR_PIN21_Pos (21UL)

Position of PIN21 field.

Definition at line 1668 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN22_Clear

#define GPIO_OUTCLR_PIN22_Clear (1UL)

Set pin driver low.

Definition at line 1665 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN22_High

#define GPIO_OUTCLR_PIN22_High (1UL)

Pin driver is high.

Definition at line 1664 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN22_Low

#define GPIO_OUTCLR_PIN22_Low (0UL)

Pin driver is low.

Definition at line 1663 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN22_Msk

#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos)

Bit mask of PIN22 field.

Definition at line 1662 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN22_Pos

#define GPIO_OUTCLR_PIN22_Pos (22UL)

Position of PIN22 field.

Definition at line 1661 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN23_Clear

#define GPIO_OUTCLR_PIN23_Clear (1UL)

Set pin driver low.

Definition at line 1658 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN23_High

#define GPIO_OUTCLR_PIN23_High (1UL)

Pin driver is high.

Definition at line 1657 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN23_Low

#define GPIO_OUTCLR_PIN23_Low (0UL)

Pin driver is low.

Definition at line 1656 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN23_Msk

#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos)

Bit mask of PIN23 field.

Definition at line 1655 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN23_Pos

#define GPIO_OUTCLR_PIN23_Pos (23UL)

Position of PIN23 field.

Definition at line 1654 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN24_Clear

#define GPIO_OUTCLR_PIN24_Clear (1UL)

Set pin driver low.

Definition at line 1651 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN24_High

#define GPIO_OUTCLR_PIN24_High (1UL)

Pin driver is high.

Definition at line 1650 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN24_Low

#define GPIO_OUTCLR_PIN24_Low (0UL)

Pin driver is low.

Definition at line 1649 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN24_Msk

#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos)

Bit mask of PIN24 field.

Definition at line 1648 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN24_Pos

#define GPIO_OUTCLR_PIN24_Pos (24UL)

Position of PIN24 field.

Definition at line 1647 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN25_Clear

#define GPIO_OUTCLR_PIN25_Clear (1UL)

Set pin driver low.

Definition at line 1644 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN25_High

#define GPIO_OUTCLR_PIN25_High (1UL)

Pin driver is high.

Definition at line 1643 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN25_Low

#define GPIO_OUTCLR_PIN25_Low (0UL)

Pin driver is low.

Definition at line 1642 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN25_Msk

#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos)

Bit mask of PIN25 field.

Definition at line 1641 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN25_Pos

#define GPIO_OUTCLR_PIN25_Pos (25UL)

Position of PIN25 field.

Definition at line 1640 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN26_Clear

#define GPIO_OUTCLR_PIN26_Clear (1UL)

Set pin driver low.

Definition at line 1637 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN26_High

#define GPIO_OUTCLR_PIN26_High (1UL)

Pin driver is high.

Definition at line 1636 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN26_Low

#define GPIO_OUTCLR_PIN26_Low (0UL)

Pin driver is low.

Definition at line 1635 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN26_Msk

#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos)

Bit mask of PIN26 field.

Definition at line 1634 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN26_Pos

#define GPIO_OUTCLR_PIN26_Pos (26UL)

Position of PIN26 field.

Definition at line 1633 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN27_Clear

#define GPIO_OUTCLR_PIN27_Clear (1UL)

Set pin driver low.

Definition at line 1630 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN27_High

#define GPIO_OUTCLR_PIN27_High (1UL)

Pin driver is high.

Definition at line 1629 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN27_Low

#define GPIO_OUTCLR_PIN27_Low (0UL)

Pin driver is low.

Definition at line 1628 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN27_Msk

#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos)

Bit mask of PIN27 field.

Definition at line 1627 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN27_Pos

#define GPIO_OUTCLR_PIN27_Pos (27UL)

Position of PIN27 field.

Definition at line 1626 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN28_Clear

#define GPIO_OUTCLR_PIN28_Clear (1UL)

Set pin driver low.

Definition at line 1623 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN28_High

#define GPIO_OUTCLR_PIN28_High (1UL)

Pin driver is high.

Definition at line 1622 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN28_Low

#define GPIO_OUTCLR_PIN28_Low (0UL)

Pin driver is low.

Definition at line 1621 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN28_Msk

#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos)

Bit mask of PIN28 field.

Definition at line 1620 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN28_Pos

#define GPIO_OUTCLR_PIN28_Pos (28UL)

Position of PIN28 field.

Definition at line 1619 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN29_Clear

#define GPIO_OUTCLR_PIN29_Clear (1UL)

Set pin driver low.

Definition at line 1616 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN29_High

#define GPIO_OUTCLR_PIN29_High (1UL)

Pin driver is high.

Definition at line 1615 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN29_Low

#define GPIO_OUTCLR_PIN29_Low (0UL)

Pin driver is low.

Definition at line 1614 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN29_Msk

#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos)

Bit mask of PIN29 field.

Definition at line 1613 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN29_Pos

#define GPIO_OUTCLR_PIN29_Pos (29UL)

Position of PIN29 field.

Definition at line 1612 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN2_Clear

#define GPIO_OUTCLR_PIN2_Clear (1UL)

Set pin driver low.

Definition at line 1805 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN2_High

#define GPIO_OUTCLR_PIN2_High (1UL)

Pin driver is high.

Definition at line 1804 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN2_Low

#define GPIO_OUTCLR_PIN2_Low (0UL)

Pin driver is low.

Definition at line 1803 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN2_Msk

#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos)

Bit mask of PIN2 field.

Definition at line 1802 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN2_Pos

#define GPIO_OUTCLR_PIN2_Pos (2UL)

Position of PIN2 field.

Definition at line 1801 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN30_Clear

#define GPIO_OUTCLR_PIN30_Clear (1UL)

Set pin driver low.

Definition at line 1609 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN30_High

#define GPIO_OUTCLR_PIN30_High (1UL)

Pin driver is high.

Definition at line 1608 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN30_Low

#define GPIO_OUTCLR_PIN30_Low (0UL)

Pin driver is low.

Definition at line 1607 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN30_Msk

#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos)

Bit mask of PIN30 field.

Definition at line 1606 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN30_Pos

#define GPIO_OUTCLR_PIN30_Pos (30UL)

Position of PIN30 field.

Definition at line 1605 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN31_Clear

#define GPIO_OUTCLR_PIN31_Clear (1UL)

Set pin driver low.

Definition at line 1602 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN31_High

#define GPIO_OUTCLR_PIN31_High (1UL)

Pin driver is high.

Definition at line 1601 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN31_Low

#define GPIO_OUTCLR_PIN31_Low (0UL)

Pin driver is low.

Definition at line 1600 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN31_Msk

#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos)

Bit mask of PIN31 field.

Definition at line 1599 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN31_Pos

#define GPIO_OUTCLR_PIN31_Pos (31UL)

Position of PIN31 field.

Definition at line 1598 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN3_Clear

#define GPIO_OUTCLR_PIN3_Clear (1UL)

Set pin driver low.

Definition at line 1798 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN3_High

#define GPIO_OUTCLR_PIN3_High (1UL)

Pin driver is high.

Definition at line 1797 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN3_Low

#define GPIO_OUTCLR_PIN3_Low (0UL)

Pin driver is low.

Definition at line 1796 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN3_Msk

#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos)

Bit mask of PIN3 field.

Definition at line 1795 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN3_Pos

#define GPIO_OUTCLR_PIN3_Pos (3UL)

Position of PIN3 field.

Definition at line 1794 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN4_Clear

#define GPIO_OUTCLR_PIN4_Clear (1UL)

Set pin driver low.

Definition at line 1791 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN4_High

#define GPIO_OUTCLR_PIN4_High (1UL)

Pin driver is high.

Definition at line 1790 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN4_Low

#define GPIO_OUTCLR_PIN4_Low (0UL)

Pin driver is low.

Definition at line 1789 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN4_Msk

#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos)

Bit mask of PIN4 field.

Definition at line 1788 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN4_Pos

#define GPIO_OUTCLR_PIN4_Pos (4UL)

Position of PIN4 field.

Definition at line 1787 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN5_Clear

#define GPIO_OUTCLR_PIN5_Clear (1UL)

Set pin driver low.

Definition at line 1784 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN5_High

#define GPIO_OUTCLR_PIN5_High (1UL)

Pin driver is high.

Definition at line 1783 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN5_Low

#define GPIO_OUTCLR_PIN5_Low (0UL)

Pin driver is low.

Definition at line 1782 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN5_Msk

#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos)

Bit mask of PIN5 field.

Definition at line 1781 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN5_Pos

#define GPIO_OUTCLR_PIN5_Pos (5UL)

Position of PIN5 field.

Definition at line 1780 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN6_Clear

#define GPIO_OUTCLR_PIN6_Clear (1UL)

Set pin driver low.

Definition at line 1777 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN6_High

#define GPIO_OUTCLR_PIN6_High (1UL)

Pin driver is high.

Definition at line 1776 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN6_Low

#define GPIO_OUTCLR_PIN6_Low (0UL)

Pin driver is low.

Definition at line 1775 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN6_Msk

#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos)

Bit mask of PIN6 field.

Definition at line 1774 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN6_Pos

#define GPIO_OUTCLR_PIN6_Pos (6UL)

Position of PIN6 field.

Definition at line 1773 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN7_Clear

#define GPIO_OUTCLR_PIN7_Clear (1UL)

Set pin driver low.

Definition at line 1770 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN7_High

#define GPIO_OUTCLR_PIN7_High (1UL)

Pin driver is high.

Definition at line 1769 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN7_Low

#define GPIO_OUTCLR_PIN7_Low (0UL)

Pin driver is low.

Definition at line 1768 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN7_Msk

#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos)

Bit mask of PIN7 field.

Definition at line 1767 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN7_Pos

#define GPIO_OUTCLR_PIN7_Pos (7UL)

Position of PIN7 field.

Definition at line 1766 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN8_Clear

#define GPIO_OUTCLR_PIN8_Clear (1UL)

Set pin driver low.

Definition at line 1763 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN8_High

#define GPIO_OUTCLR_PIN8_High (1UL)

Pin driver is high.

Definition at line 1762 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN8_Low

#define GPIO_OUTCLR_PIN8_Low (0UL)

Pin driver is low.

Definition at line 1761 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN8_Msk

#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos)

Bit mask of PIN8 field.

Definition at line 1760 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN8_Pos

#define GPIO_OUTCLR_PIN8_Pos (8UL)

Position of PIN8 field.

Definition at line 1759 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN9_Clear

#define GPIO_OUTCLR_PIN9_Clear (1UL)

Set pin driver low.

Definition at line 1756 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN9_High

#define GPIO_OUTCLR_PIN9_High (1UL)

Pin driver is high.

Definition at line 1755 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN9_Low

#define GPIO_OUTCLR_PIN9_Low (0UL)

Pin driver is low.

Definition at line 1754 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN9_Msk

#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos)

Bit mask of PIN9 field.

Definition at line 1753 of file nrf51_bitfields.h.

◆ GPIO_OUTCLR_PIN9_Pos

#define GPIO_OUTCLR_PIN9_Pos (9UL)

Position of PIN9 field.

Definition at line 1752 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN0_High

#define GPIO_OUTSET_PIN0_High (1UL)

Pin driver is high.

Definition at line 1591 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN0_Low

#define GPIO_OUTSET_PIN0_Low (0UL)

Pin driver is low.

Definition at line 1590 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN0_Msk

#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos)

Bit mask of PIN0 field.

Definition at line 1589 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN0_Pos

#define GPIO_OUTSET_PIN0_Pos (0UL)

Position of PIN0 field.

Definition at line 1588 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN0_Set

#define GPIO_OUTSET_PIN0_Set (1UL)

Set pin driver high.

Definition at line 1592 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN10_High

#define GPIO_OUTSET_PIN10_High (1UL)

Pin driver is high.

Definition at line 1521 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN10_Low

#define GPIO_OUTSET_PIN10_Low (0UL)

Pin driver is low.

Definition at line 1520 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN10_Msk

#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos)

Bit mask of PIN10 field.

Definition at line 1519 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN10_Pos

#define GPIO_OUTSET_PIN10_Pos (10UL)

Position of PIN10 field.

Definition at line 1518 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN10_Set

#define GPIO_OUTSET_PIN10_Set (1UL)

Set pin driver high.

Definition at line 1522 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN11_High

#define GPIO_OUTSET_PIN11_High (1UL)

Pin driver is high.

Definition at line 1514 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN11_Low

#define GPIO_OUTSET_PIN11_Low (0UL)

Pin driver is low.

Definition at line 1513 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN11_Msk

#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos)

Bit mask of PIN11 field.

Definition at line 1512 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN11_Pos

#define GPIO_OUTSET_PIN11_Pos (11UL)

Position of PIN11 field.

Definition at line 1511 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN11_Set

#define GPIO_OUTSET_PIN11_Set (1UL)

Set pin driver high.

Definition at line 1515 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN12_High

#define GPIO_OUTSET_PIN12_High (1UL)

Pin driver is high.

Definition at line 1507 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN12_Low

#define GPIO_OUTSET_PIN12_Low (0UL)

Pin driver is low.

Definition at line 1506 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN12_Msk

#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos)

Bit mask of PIN12 field.

Definition at line 1505 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN12_Pos

#define GPIO_OUTSET_PIN12_Pos (12UL)

Position of PIN12 field.

Definition at line 1504 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN12_Set

#define GPIO_OUTSET_PIN12_Set (1UL)

Set pin driver high.

Definition at line 1508 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN13_High

#define GPIO_OUTSET_PIN13_High (1UL)

Pin driver is high.

Definition at line 1500 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN13_Low

#define GPIO_OUTSET_PIN13_Low (0UL)

Pin driver is low.

Definition at line 1499 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN13_Msk

#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos)

Bit mask of PIN13 field.

Definition at line 1498 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN13_Pos

#define GPIO_OUTSET_PIN13_Pos (13UL)

Position of PIN13 field.

Definition at line 1497 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN13_Set

#define GPIO_OUTSET_PIN13_Set (1UL)

Set pin driver high.

Definition at line 1501 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN14_High

#define GPIO_OUTSET_PIN14_High (1UL)

Pin driver is high.

Definition at line 1493 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN14_Low

#define GPIO_OUTSET_PIN14_Low (0UL)

Pin driver is low.

Definition at line 1492 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN14_Msk

#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos)

Bit mask of PIN14 field.

Definition at line 1491 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN14_Pos

#define GPIO_OUTSET_PIN14_Pos (14UL)

Position of PIN14 field.

Definition at line 1490 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN14_Set

#define GPIO_OUTSET_PIN14_Set (1UL)

Set pin driver high.

Definition at line 1494 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN15_High

#define GPIO_OUTSET_PIN15_High (1UL)

Pin driver is high.

Definition at line 1486 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN15_Low

#define GPIO_OUTSET_PIN15_Low (0UL)

Pin driver is low.

Definition at line 1485 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN15_Msk

#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos)

Bit mask of PIN15 field.

Definition at line 1484 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN15_Pos

#define GPIO_OUTSET_PIN15_Pos (15UL)

Position of PIN15 field.

Definition at line 1483 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN15_Set

#define GPIO_OUTSET_PIN15_Set (1UL)

Set pin driver high.

Definition at line 1487 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN16_High

#define GPIO_OUTSET_PIN16_High (1UL)

Pin driver is high.

Definition at line 1479 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN16_Low

#define GPIO_OUTSET_PIN16_Low (0UL)

Pin driver is low.

Definition at line 1478 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN16_Msk

#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos)

Bit mask of PIN16 field.

Definition at line 1477 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN16_Pos

#define GPIO_OUTSET_PIN16_Pos (16UL)

Position of PIN16 field.

Definition at line 1476 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN16_Set

#define GPIO_OUTSET_PIN16_Set (1UL)

Set pin driver high.

Definition at line 1480 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN17_High

#define GPIO_OUTSET_PIN17_High (1UL)

Pin driver is high.

Definition at line 1472 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN17_Low

#define GPIO_OUTSET_PIN17_Low (0UL)

Pin driver is low.

Definition at line 1471 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN17_Msk

#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos)

Bit mask of PIN17 field.

Definition at line 1470 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN17_Pos

#define GPIO_OUTSET_PIN17_Pos (17UL)

Position of PIN17 field.

Definition at line 1469 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN17_Set

#define GPIO_OUTSET_PIN17_Set (1UL)

Set pin driver high.

Definition at line 1473 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN18_High

#define GPIO_OUTSET_PIN18_High (1UL)

Pin driver is high.

Definition at line 1465 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN18_Low

#define GPIO_OUTSET_PIN18_Low (0UL)

Pin driver is low.

Definition at line 1464 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN18_Msk

#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos)

Bit mask of PIN18 field.

Definition at line 1463 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN18_Pos

#define GPIO_OUTSET_PIN18_Pos (18UL)

Position of PIN18 field.

Definition at line 1462 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN18_Set

#define GPIO_OUTSET_PIN18_Set (1UL)

Set pin driver high.

Definition at line 1466 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN19_High

#define GPIO_OUTSET_PIN19_High (1UL)

Pin driver is high.

Definition at line 1458 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN19_Low

#define GPIO_OUTSET_PIN19_Low (0UL)

Pin driver is low.

Definition at line 1457 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN19_Msk

#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos)

Bit mask of PIN19 field.

Definition at line 1456 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN19_Pos

#define GPIO_OUTSET_PIN19_Pos (19UL)

Position of PIN19 field.

Definition at line 1455 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN19_Set

#define GPIO_OUTSET_PIN19_Set (1UL)

Set pin driver high.

Definition at line 1459 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN1_High

#define GPIO_OUTSET_PIN1_High (1UL)

Pin driver is high.

Definition at line 1584 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN1_Low

#define GPIO_OUTSET_PIN1_Low (0UL)

Pin driver is low.

Definition at line 1583 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN1_Msk

#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos)

Bit mask of PIN1 field.

Definition at line 1582 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN1_Pos

#define GPIO_OUTSET_PIN1_Pos (1UL)

Position of PIN1 field.

Definition at line 1581 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN1_Set

#define GPIO_OUTSET_PIN1_Set (1UL)

Set pin driver high.

Definition at line 1585 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN20_High

#define GPIO_OUTSET_PIN20_High (1UL)

Pin driver is high.

Definition at line 1451 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN20_Low

#define GPIO_OUTSET_PIN20_Low (0UL)

Pin driver is low.

Definition at line 1450 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN20_Msk

#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos)

Bit mask of PIN20 field.

Definition at line 1449 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN20_Pos

#define GPIO_OUTSET_PIN20_Pos (20UL)

Position of PIN20 field.

Definition at line 1448 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN20_Set

#define GPIO_OUTSET_PIN20_Set (1UL)

Set pin driver high.

Definition at line 1452 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN21_High

#define GPIO_OUTSET_PIN21_High (1UL)

Pin driver is high.

Definition at line 1444 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN21_Low

#define GPIO_OUTSET_PIN21_Low (0UL)

Pin driver is low.

Definition at line 1443 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN21_Msk

#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos)

Bit mask of PIN21 field.

Definition at line 1442 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN21_Pos

#define GPIO_OUTSET_PIN21_Pos (21UL)

Position of PIN21 field.

Definition at line 1441 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN21_Set

#define GPIO_OUTSET_PIN21_Set (1UL)

Set pin driver high.

Definition at line 1445 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN22_High

#define GPIO_OUTSET_PIN22_High (1UL)

Pin driver is high.

Definition at line 1437 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN22_Low

#define GPIO_OUTSET_PIN22_Low (0UL)

Pin driver is low.

Definition at line 1436 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN22_Msk

#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos)

Bit mask of PIN22 field.

Definition at line 1435 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN22_Pos

#define GPIO_OUTSET_PIN22_Pos (22UL)

Position of PIN22 field.

Definition at line 1434 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN22_Set

#define GPIO_OUTSET_PIN22_Set (1UL)

Set pin driver high.

Definition at line 1438 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN23_High

#define GPIO_OUTSET_PIN23_High (1UL)

Pin driver is high.

Definition at line 1430 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN23_Low

#define GPIO_OUTSET_PIN23_Low (0UL)

Pin driver is low.

Definition at line 1429 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN23_Msk

#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos)

Bit mask of PIN23 field.

Definition at line 1428 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN23_Pos

#define GPIO_OUTSET_PIN23_Pos (23UL)

Position of PIN23 field.

Definition at line 1427 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN23_Set

#define GPIO_OUTSET_PIN23_Set (1UL)

Set pin driver high.

Definition at line 1431 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN24_High

#define GPIO_OUTSET_PIN24_High (1UL)

Pin driver is high.

Definition at line 1423 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN24_Low

#define GPIO_OUTSET_PIN24_Low (0UL)

Pin driver is low.

Definition at line 1422 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN24_Msk

#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos)

Bit mask of PIN24 field.

Definition at line 1421 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN24_Pos

#define GPIO_OUTSET_PIN24_Pos (24UL)

Position of PIN24 field.

Definition at line 1420 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN24_Set

#define GPIO_OUTSET_PIN24_Set (1UL)

Set pin driver high.

Definition at line 1424 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN25_High

#define GPIO_OUTSET_PIN25_High (1UL)

Pin driver is high.

Definition at line 1416 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN25_Low

#define GPIO_OUTSET_PIN25_Low (0UL)

Pin driver is low.

Definition at line 1415 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN25_Msk

#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos)

Bit mask of PIN25 field.

Definition at line 1414 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN25_Pos

#define GPIO_OUTSET_PIN25_Pos (25UL)

Position of PIN25 field.

Definition at line 1413 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN25_Set

#define GPIO_OUTSET_PIN25_Set (1UL)

Set pin driver high.

Definition at line 1417 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN26_High

#define GPIO_OUTSET_PIN26_High (1UL)

Pin driver is high.

Definition at line 1409 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN26_Low

#define GPIO_OUTSET_PIN26_Low (0UL)

Pin driver is low.

Definition at line 1408 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN26_Msk

#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos)

Bit mask of PIN26 field.

Definition at line 1407 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN26_Pos

#define GPIO_OUTSET_PIN26_Pos (26UL)

Position of PIN26 field.

Definition at line 1406 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN26_Set

#define GPIO_OUTSET_PIN26_Set (1UL)

Set pin driver high.

Definition at line 1410 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN27_High

#define GPIO_OUTSET_PIN27_High (1UL)

Pin driver is high.

Definition at line 1402 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN27_Low

#define GPIO_OUTSET_PIN27_Low (0UL)

Pin driver is low.

Definition at line 1401 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN27_Msk

#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos)

Bit mask of PIN27 field.

Definition at line 1400 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN27_Pos

#define GPIO_OUTSET_PIN27_Pos (27UL)

Position of PIN27 field.

Definition at line 1399 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN27_Set

#define GPIO_OUTSET_PIN27_Set (1UL)

Set pin driver high.

Definition at line 1403 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN28_High

#define GPIO_OUTSET_PIN28_High (1UL)

Pin driver is high.

Definition at line 1395 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN28_Low

#define GPIO_OUTSET_PIN28_Low (0UL)

Pin driver is low.

Definition at line 1394 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN28_Msk

#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos)

Bit mask of PIN28 field.

Definition at line 1393 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN28_Pos

#define GPIO_OUTSET_PIN28_Pos (28UL)

Position of PIN28 field.

Definition at line 1392 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN28_Set

#define GPIO_OUTSET_PIN28_Set (1UL)

Set pin driver high.

Definition at line 1396 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN29_High

#define GPIO_OUTSET_PIN29_High (1UL)

Pin driver is high.

Definition at line 1388 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN29_Low

#define GPIO_OUTSET_PIN29_Low (0UL)

Pin driver is low.

Definition at line 1387 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN29_Msk

#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos)

Bit mask of PIN29 field.

Definition at line 1386 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN29_Pos

#define GPIO_OUTSET_PIN29_Pos (29UL)

Position of PIN29 field.

Definition at line 1385 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN29_Set

#define GPIO_OUTSET_PIN29_Set (1UL)

Set pin driver high.

Definition at line 1389 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN2_High

#define GPIO_OUTSET_PIN2_High (1UL)

Pin driver is high.

Definition at line 1577 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN2_Low

#define GPIO_OUTSET_PIN2_Low (0UL)

Pin driver is low.

Definition at line 1576 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN2_Msk

#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos)

Bit mask of PIN2 field.

Definition at line 1575 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN2_Pos

#define GPIO_OUTSET_PIN2_Pos (2UL)

Position of PIN2 field.

Definition at line 1574 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN2_Set

#define GPIO_OUTSET_PIN2_Set (1UL)

Set pin driver high.

Definition at line 1578 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN30_High

#define GPIO_OUTSET_PIN30_High (1UL)

Pin driver is high.

Definition at line 1381 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN30_Low

#define GPIO_OUTSET_PIN30_Low (0UL)

Pin driver is low.

Definition at line 1380 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN30_Msk

#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos)

Bit mask of PIN30 field.

Definition at line 1379 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN30_Pos

#define GPIO_OUTSET_PIN30_Pos (30UL)

Position of PIN30 field.

Definition at line 1378 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN30_Set

#define GPIO_OUTSET_PIN30_Set (1UL)

Set pin driver high.

Definition at line 1382 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN31_High

#define GPIO_OUTSET_PIN31_High (1UL)

Pin driver is high.

Definition at line 1374 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN31_Low

#define GPIO_OUTSET_PIN31_Low (0UL)

Pin driver is low.

Definition at line 1373 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN31_Msk

#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos)

Bit mask of PIN31 field.

Definition at line 1372 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN31_Pos

#define GPIO_OUTSET_PIN31_Pos (31UL)

Position of PIN31 field.

Definition at line 1371 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN31_Set

#define GPIO_OUTSET_PIN31_Set (1UL)

Set pin driver high.

Definition at line 1375 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN3_High

#define GPIO_OUTSET_PIN3_High (1UL)

Pin driver is high.

Definition at line 1570 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN3_Low

#define GPIO_OUTSET_PIN3_Low (0UL)

Pin driver is low.

Definition at line 1569 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN3_Msk

#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos)

Bit mask of PIN3 field.

Definition at line 1568 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN3_Pos

#define GPIO_OUTSET_PIN3_Pos (3UL)

Position of PIN3 field.

Definition at line 1567 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN3_Set

#define GPIO_OUTSET_PIN3_Set (1UL)

Set pin driver high.

Definition at line 1571 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN4_High

#define GPIO_OUTSET_PIN4_High (1UL)

Pin driver is high.

Definition at line 1563 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN4_Low

#define GPIO_OUTSET_PIN4_Low (0UL)

Pin driver is low.

Definition at line 1562 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN4_Msk

#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos)

Bit mask of PIN4 field.

Definition at line 1561 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN4_Pos

#define GPIO_OUTSET_PIN4_Pos (4UL)

Position of PIN4 field.

Definition at line 1560 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN4_Set

#define GPIO_OUTSET_PIN4_Set (1UL)

Set pin driver high.

Definition at line 1564 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN5_High

#define GPIO_OUTSET_PIN5_High (1UL)

Pin driver is high.

Definition at line 1556 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN5_Low

#define GPIO_OUTSET_PIN5_Low (0UL)

Pin driver is low.

Definition at line 1555 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN5_Msk

#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos)

Bit mask of PIN5 field.

Definition at line 1554 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN5_Pos

#define GPIO_OUTSET_PIN5_Pos (5UL)

Position of PIN5 field.

Definition at line 1553 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN5_Set

#define GPIO_OUTSET_PIN5_Set (1UL)

Set pin driver high.

Definition at line 1557 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN6_High

#define GPIO_OUTSET_PIN6_High (1UL)

Pin driver is high.

Definition at line 1549 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN6_Low

#define GPIO_OUTSET_PIN6_Low (0UL)

Pin driver is low.

Definition at line 1548 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN6_Msk

#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos)

Bit mask of PIN6 field.

Definition at line 1547 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN6_Pos

#define GPIO_OUTSET_PIN6_Pos (6UL)

Position of PIN6 field.

Definition at line 1546 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN6_Set

#define GPIO_OUTSET_PIN6_Set (1UL)

Set pin driver high.

Definition at line 1550 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN7_High

#define GPIO_OUTSET_PIN7_High (1UL)

Pin driver is high.

Definition at line 1542 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN7_Low

#define GPIO_OUTSET_PIN7_Low (0UL)

Pin driver is low.

Definition at line 1541 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN7_Msk

#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos)

Bit mask of PIN7 field.

Definition at line 1540 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN7_Pos

#define GPIO_OUTSET_PIN7_Pos (7UL)

Position of PIN7 field.

Definition at line 1539 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN7_Set

#define GPIO_OUTSET_PIN7_Set (1UL)

Set pin driver high.

Definition at line 1543 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN8_High

#define GPIO_OUTSET_PIN8_High (1UL)

Pin driver is high.

Definition at line 1535 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN8_Low

#define GPIO_OUTSET_PIN8_Low (0UL)

Pin driver is low.

Definition at line 1534 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN8_Msk

#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos)

Bit mask of PIN8 field.

Definition at line 1533 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN8_Pos

#define GPIO_OUTSET_PIN8_Pos (8UL)

Position of PIN8 field.

Definition at line 1532 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN8_Set

#define GPIO_OUTSET_PIN8_Set (1UL)

Set pin driver high.

Definition at line 1536 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN9_High

#define GPIO_OUTSET_PIN9_High (1UL)

Pin driver is high.

Definition at line 1528 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN9_Low

#define GPIO_OUTSET_PIN9_Low (0UL)

Pin driver is low.

Definition at line 1527 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN9_Msk

#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos)

Bit mask of PIN9 field.

Definition at line 1526 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN9_Pos

#define GPIO_OUTSET_PIN9_Pos (9UL)

Position of PIN9 field.

Definition at line 1525 of file nrf51_bitfields.h.

◆ GPIO_OUTSET_PIN9_Set

#define GPIO_OUTSET_PIN9_Set (1UL)

Set pin driver high.

Definition at line 1529 of file nrf51_bitfields.h.

◆ GPIO_PIN_CNF_DIR_Input

#define GPIO_PIN_CNF_DIR_Input (0UL)

Configure pin as an input pin.

Definition at line 2703 of file nrf51_bitfields.h.

◆ GPIO_PIN_CNF_DIR_Msk

#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos)

Bit mask of DIR field.

Definition at line 2702 of file nrf51_bitfields.h.

◆ GPIO_PIN_CNF_DIR_Output

#define GPIO_PIN_CNF_DIR_Output (1UL)

Configure pin as an output pin.

Definition at line 2704 of file nrf51_bitfields.h.

◆ GPIO_PIN_CNF_DIR_Pos

#define GPIO_PIN_CNF_DIR_Pos (0UL)

Position of DIR field.

Definition at line 2701 of file nrf51_bitfields.h.

◆ GPIO_PIN_CNF_DRIVE_D0H1

#define GPIO_PIN_CNF_DRIVE_D0H1 (0x05UL)

Disconnected '0', High '1'.

Definition at line 2683 of file nrf51_bitfields.h.

◆ GPIO_PIN_CNF_DRIVE_D0S1

#define GPIO_PIN_CNF_DRIVE_D0S1 (0x04UL)

Disconnected '0', Standard '1'.

Definition at line 2682 of file nrf51_bitfields.h.

◆ GPIO_PIN_CNF_DRIVE_H0D1

#define GPIO_PIN_CNF_DRIVE_H0D1 (0x07UL)

High '0', Disconnected '1'.

Definition at line 2685 of file nrf51_bitfields.h.

◆ GPIO_PIN_CNF_DRIVE_H0H1

#define GPIO_PIN_CNF_DRIVE_H0H1 (0x03UL)

High '0', High '1'.

Definition at line 2681 of file nrf51_bitfields.h.

◆ GPIO_PIN_CNF_DRIVE_H0S1

#define GPIO_PIN_CNF_DRIVE_H0S1 (0x01UL)

High '0', Standard '1'.

Definition at line 2679 of file nrf51_bitfields.h.

◆ GPIO_PIN_CNF_DRIVE_Msk

#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos)

Bit mask of DRIVE field.

Definition at line 2677 of file nrf51_bitfields.h.

◆ GPIO_PIN_CNF_DRIVE_Pos

#define GPIO_PIN_CNF_DRIVE_Pos (8UL)

Position of DRIVE field.

Definition at line 2676 of file nrf51_bitfields.h.

◆ GPIO_PIN_CNF_DRIVE_S0D1

#define GPIO_PIN_CNF_DRIVE_S0D1 (0x06UL)

Standard '0', Disconnected '1'.

Definition at line 2684 of file nrf51_bitfields.h.

◆ GPIO_PIN_CNF_DRIVE_S0H1

#define GPIO_PIN_CNF_DRIVE_S0H1 (0x02UL)

Standard '0', High '1'.

Definition at line 2680 of file nrf51_bitfields.h.

◆ GPIO_PIN_CNF_DRIVE_S0S1

#define GPIO_PIN_CNF_DRIVE_S0S1 (0x00UL)

Standard '0', Standard '1'.

Definition at line 2678 of file nrf51_bitfields.h.

◆ GPIO_PIN_CNF_INPUT_Connect

#define GPIO_PIN_CNF_INPUT_Connect (0UL)

Connect input pin.

Definition at line 2697 of file nrf51_bitfields.h.

◆ GPIO_PIN_CNF_INPUT_Disconnect

#define GPIO_PIN_CNF_INPUT_Disconnect (1UL)

Disconnect input pin.

Definition at line 2698 of file nrf51_bitfields.h.

◆ GPIO_PIN_CNF_INPUT_Msk

#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos)

Bit mask of INPUT field.

Definition at line 2696 of file nrf51_bitfields.h.

◆ GPIO_PIN_CNF_INPUT_Pos

#define GPIO_PIN_CNF_INPUT_Pos (1UL)

Position of INPUT field.

Definition at line 2695 of file nrf51_bitfields.h.

◆ GPIO_PIN_CNF_PULL_Disabled

#define GPIO_PIN_CNF_PULL_Disabled (0x00UL)

No pull.

Definition at line 2690 of file nrf51_bitfields.h.

◆ GPIO_PIN_CNF_PULL_Msk

#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos)

Bit mask of PULL field.

Definition at line 2689 of file nrf51_bitfields.h.

◆ GPIO_PIN_CNF_PULL_Pos

#define GPIO_PIN_CNF_PULL_Pos (2UL)

Position of PULL field.

Definition at line 2688 of file nrf51_bitfields.h.

◆ GPIO_PIN_CNF_PULL_Pulldown

#define GPIO_PIN_CNF_PULL_Pulldown (0x01UL)

Pulldown on pin.

Definition at line 2691 of file nrf51_bitfields.h.

◆ GPIO_PIN_CNF_PULL_Pullup

#define GPIO_PIN_CNF_PULL_Pullup (0x03UL)

Pullup on pin.

Definition at line 2692 of file nrf51_bitfields.h.

◆ GPIO_PIN_CNF_SENSE_Disabled

#define GPIO_PIN_CNF_SENSE_Disabled (0x00UL)

Disabled.

Definition at line 2671 of file nrf51_bitfields.h.

◆ GPIO_PIN_CNF_SENSE_High

#define GPIO_PIN_CNF_SENSE_High (0x02UL)

Wakeup on high level.

Definition at line 2672 of file nrf51_bitfields.h.

◆ GPIO_PIN_CNF_SENSE_Low

#define GPIO_PIN_CNF_SENSE_Low (0x03UL)

Wakeup on low level.

Definition at line 2673 of file nrf51_bitfields.h.

◆ GPIO_PIN_CNF_SENSE_Msk

#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos)

Bit mask of SENSE field.

Definition at line 2670 of file nrf51_bitfields.h.

◆ GPIO_PIN_CNF_SENSE_Pos

#define GPIO_PIN_CNF_SENSE_Pos (16UL)

Position of SENSE field.

Definition at line 2669 of file nrf51_bitfields.h.

◆ GPIOTE_CONFIG_MODE_Disabled

#define GPIOTE_CONFIG_MODE_Disabled (0x00UL)

Disabled.

Definition at line 2810 of file nrf51_bitfields.h.

◆ GPIOTE_CONFIG_MODE_Event

#define GPIOTE_CONFIG_MODE_Event (0x01UL)

Channel configure in event mode.

Definition at line 2811 of file nrf51_bitfields.h.

◆ GPIOTE_CONFIG_MODE_Msk

#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos)

Bit mask of MODE field.

Definition at line 2809 of file nrf51_bitfields.h.

◆ GPIOTE_CONFIG_MODE_Pos

#define GPIOTE_CONFIG_MODE_Pos (0UL)

Position of MODE field.

Definition at line 2808 of file nrf51_bitfields.h.

◆ GPIOTE_CONFIG_MODE_Task

#define GPIOTE_CONFIG_MODE_Task (0x03UL)

Channel configure in task mode.

Definition at line 2812 of file nrf51_bitfields.h.

◆ GPIOTE_CONFIG_OUTINIT_High

#define GPIOTE_CONFIG_OUTINIT_High (1UL)

Initial high output when in task mode.

Definition at line 2793 of file nrf51_bitfields.h.

◆ GPIOTE_CONFIG_OUTINIT_Low

#define GPIOTE_CONFIG_OUTINIT_Low (0UL)

Initial low output when in task mode.

Definition at line 2792 of file nrf51_bitfields.h.

◆ GPIOTE_CONFIG_OUTINIT_Msk

#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos)

Bit mask of OUTINIT field.

Definition at line 2791 of file nrf51_bitfields.h.

◆ GPIOTE_CONFIG_OUTINIT_Pos

#define GPIOTE_CONFIG_OUTINIT_Pos (20UL)

Position of OUTINIT field.

Definition at line 2790 of file nrf51_bitfields.h.

◆ GPIOTE_CONFIG_POLARITY_HiToLo

#define GPIOTE_CONFIG_POLARITY_HiToLo (0x02UL)

High to low.

Definition at line 2800 of file nrf51_bitfields.h.

◆ GPIOTE_CONFIG_POLARITY_LoToHi

#define GPIOTE_CONFIG_POLARITY_LoToHi (0x01UL)

Low to high.

Definition at line 2799 of file nrf51_bitfields.h.

◆ GPIOTE_CONFIG_POLARITY_Msk

#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos)

Bit mask of POLARITY field.

Definition at line 2797 of file nrf51_bitfields.h.

◆ GPIOTE_CONFIG_POLARITY_None

#define GPIOTE_CONFIG_POLARITY_None (0x00UL)

No task or event.

Definition at line 2798 of file nrf51_bitfields.h.

◆ GPIOTE_CONFIG_POLARITY_Pos

#define GPIOTE_CONFIG_POLARITY_Pos (16UL)

Position of POLARITY field.

Definition at line 2796 of file nrf51_bitfields.h.

◆ GPIOTE_CONFIG_POLARITY_Toggle

#define GPIOTE_CONFIG_POLARITY_Toggle (0x03UL)

Toggle.

Definition at line 2801 of file nrf51_bitfields.h.

◆ GPIOTE_CONFIG_PSEL_Msk

#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos)

Bit mask of PSEL field.

Definition at line 2805 of file nrf51_bitfields.h.

◆ GPIOTE_CONFIG_PSEL_Pos

#define GPIOTE_CONFIG_PSEL_Pos (8UL)

Position of PSEL field.

Definition at line 2804 of file nrf51_bitfields.h.

◆ GPIOTE_INTENCLR_IN0_Clear

#define GPIOTE_INTENCLR_IN0_Clear (1UL)

Disable interrupt on write.

Definition at line 2784 of file nrf51_bitfields.h.

◆ GPIOTE_INTENCLR_IN0_Disabled

#define GPIOTE_INTENCLR_IN0_Disabled (0UL)

Interrupt disabled.

Definition at line 2782 of file nrf51_bitfields.h.

◆ GPIOTE_INTENCLR_IN0_Enabled

#define GPIOTE_INTENCLR_IN0_Enabled (1UL)

Interrupt enabled.

Definition at line 2783 of file nrf51_bitfields.h.

◆ GPIOTE_INTENCLR_IN0_Msk

#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos)

Bit mask of IN0 field.

Definition at line 2781 of file nrf51_bitfields.h.

◆ GPIOTE_INTENCLR_IN0_Pos

#define GPIOTE_INTENCLR_IN0_Pos (0UL)

Position of IN0 field.

Definition at line 2780 of file nrf51_bitfields.h.

◆ GPIOTE_INTENCLR_IN1_Clear

#define GPIOTE_INTENCLR_IN1_Clear (1UL)

Disable interrupt on write.

Definition at line 2777 of file nrf51_bitfields.h.

◆ GPIOTE_INTENCLR_IN1_Disabled

#define GPIOTE_INTENCLR_IN1_Disabled (0UL)

Interrupt disabled.

Definition at line 2775 of file nrf51_bitfields.h.

◆ GPIOTE_INTENCLR_IN1_Enabled

#define GPIOTE_INTENCLR_IN1_Enabled (1UL)

Interrupt enabled.

Definition at line 2776 of file nrf51_bitfields.h.

◆ GPIOTE_INTENCLR_IN1_Msk

#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos)

Bit mask of IN1 field.

Definition at line 2774 of file nrf51_bitfields.h.

◆ GPIOTE_INTENCLR_IN1_Pos

#define GPIOTE_INTENCLR_IN1_Pos (1UL)

Position of IN1 field.

Definition at line 2773 of file nrf51_bitfields.h.

◆ GPIOTE_INTENCLR_IN2_Clear

#define GPIOTE_INTENCLR_IN2_Clear (1UL)

Disable interrupt on write.

Definition at line 2770 of file nrf51_bitfields.h.

◆ GPIOTE_INTENCLR_IN2_Disabled

#define GPIOTE_INTENCLR_IN2_Disabled (0UL)

Interrupt disabled.

Definition at line 2768 of file nrf51_bitfields.h.

◆ GPIOTE_INTENCLR_IN2_Enabled

#define GPIOTE_INTENCLR_IN2_Enabled (1UL)

Interrupt enabled.

Definition at line 2769 of file nrf51_bitfields.h.

◆ GPIOTE_INTENCLR_IN2_Msk

#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos)

Bit mask of IN2 field.

Definition at line 2767 of file nrf51_bitfields.h.

◆ GPIOTE_INTENCLR_IN2_Pos

#define GPIOTE_INTENCLR_IN2_Pos (2UL)

Position of IN2 field.

Definition at line 2766 of file nrf51_bitfields.h.

◆ GPIOTE_INTENCLR_IN3_Clear

#define GPIOTE_INTENCLR_IN3_Clear (1UL)

Disable interrupt on write.

Definition at line 2763 of file nrf51_bitfields.h.

◆ GPIOTE_INTENCLR_IN3_Disabled

#define GPIOTE_INTENCLR_IN3_Disabled (0UL)

Interrupt disabled.

Definition at line 2761 of file nrf51_bitfields.h.

◆ GPIOTE_INTENCLR_IN3_Enabled

#define GPIOTE_INTENCLR_IN3_Enabled (1UL)

Interrupt enabled.

Definition at line 2762 of file nrf51_bitfields.h.

◆ GPIOTE_INTENCLR_IN3_Msk

#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos)

Bit mask of IN3 field.

Definition at line 2760 of file nrf51_bitfields.h.

◆ GPIOTE_INTENCLR_IN3_Pos

#define GPIOTE_INTENCLR_IN3_Pos (3UL)

Position of IN3 field.

Definition at line 2759 of file nrf51_bitfields.h.

◆ GPIOTE_INTENCLR_PORT_Clear

#define GPIOTE_INTENCLR_PORT_Clear (1UL)

Disable interrupt on write.

Definition at line 2756 of file nrf51_bitfields.h.

◆ GPIOTE_INTENCLR_PORT_Disabled

#define GPIOTE_INTENCLR_PORT_Disabled (0UL)

Interrupt disabled.

Definition at line 2754 of file nrf51_bitfields.h.

◆ GPIOTE_INTENCLR_PORT_Enabled

#define GPIOTE_INTENCLR_PORT_Enabled (1UL)

Interrupt enabled.

Definition at line 2755 of file nrf51_bitfields.h.

◆ GPIOTE_INTENCLR_PORT_Msk

#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos)

Bit mask of PORT field.

Definition at line 2753 of file nrf51_bitfields.h.

◆ GPIOTE_INTENCLR_PORT_Pos

#define GPIOTE_INTENCLR_PORT_Pos (31UL)

Position of PORT field.

Definition at line 2752 of file nrf51_bitfields.h.

◆ GPIOTE_INTENSET_IN0_Disabled

#define GPIOTE_INTENSET_IN0_Disabled (0UL)

Interrupt disabled.

Definition at line 2744 of file nrf51_bitfields.h.

◆ GPIOTE_INTENSET_IN0_Enabled

#define GPIOTE_INTENSET_IN0_Enabled (1UL)

Interrupt enabled.

Definition at line 2745 of file nrf51_bitfields.h.

◆ GPIOTE_INTENSET_IN0_Msk

#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos)

Bit mask of IN0 field.

Definition at line 2743 of file nrf51_bitfields.h.

◆ GPIOTE_INTENSET_IN0_Pos

#define GPIOTE_INTENSET_IN0_Pos (0UL)

Position of IN0 field.

Definition at line 2742 of file nrf51_bitfields.h.

◆ GPIOTE_INTENSET_IN0_Set

#define GPIOTE_INTENSET_IN0_Set (1UL)

Enable interrupt on write.

Definition at line 2746 of file nrf51_bitfields.h.

◆ GPIOTE_INTENSET_IN1_Disabled

#define GPIOTE_INTENSET_IN1_Disabled (0UL)

Interrupt disabled.

Definition at line 2737 of file nrf51_bitfields.h.

◆ GPIOTE_INTENSET_IN1_Enabled

#define GPIOTE_INTENSET_IN1_Enabled (1UL)

Interrupt enabled.

Definition at line 2738 of file nrf51_bitfields.h.

◆ GPIOTE_INTENSET_IN1_Msk

#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos)

Bit mask of IN1 field.

Definition at line 2736 of file nrf51_bitfields.h.

◆ GPIOTE_INTENSET_IN1_Pos

#define GPIOTE_INTENSET_IN1_Pos (1UL)

Position of IN1 field.

Definition at line 2735 of file nrf51_bitfields.h.

◆ GPIOTE_INTENSET_IN1_Set

#define GPIOTE_INTENSET_IN1_Set (1UL)

Enable interrupt on write.

Definition at line 2739 of file nrf51_bitfields.h.

◆ GPIOTE_INTENSET_IN2_Disabled

#define GPIOTE_INTENSET_IN2_Disabled (0UL)

Interrupt disabled.

Definition at line 2730 of file nrf51_bitfields.h.

◆ GPIOTE_INTENSET_IN2_Enabled

#define GPIOTE_INTENSET_IN2_Enabled (1UL)

Interrupt enabled.

Definition at line 2731 of file nrf51_bitfields.h.

◆ GPIOTE_INTENSET_IN2_Msk

#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos)

Bit mask of IN2 field.

Definition at line 2729 of file nrf51_bitfields.h.

◆ GPIOTE_INTENSET_IN2_Pos

#define GPIOTE_INTENSET_IN2_Pos (2UL)

Position of IN2 field.

Definition at line 2728 of file nrf51_bitfields.h.

◆ GPIOTE_INTENSET_IN2_Set

#define GPIOTE_INTENSET_IN2_Set (1UL)

Enable interrupt on write.

Definition at line 2732 of file nrf51_bitfields.h.

◆ GPIOTE_INTENSET_IN3_Disabled

#define GPIOTE_INTENSET_IN3_Disabled (0UL)

Interrupt disabled.

Definition at line 2723 of file nrf51_bitfields.h.

◆ GPIOTE_INTENSET_IN3_Enabled

#define GPIOTE_INTENSET_IN3_Enabled (1UL)

Interrupt enabled.

Definition at line 2724 of file nrf51_bitfields.h.

◆ GPIOTE_INTENSET_IN3_Msk

#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos)

Bit mask of IN3 field.

Definition at line 2722 of file nrf51_bitfields.h.

◆ GPIOTE_INTENSET_IN3_Pos

#define GPIOTE_INTENSET_IN3_Pos (3UL)

Position of IN3 field.

Definition at line 2721 of file nrf51_bitfields.h.

◆ GPIOTE_INTENSET_IN3_Set

#define GPIOTE_INTENSET_IN3_Set (1UL)

Enable interrupt on write.

Definition at line 2725 of file nrf51_bitfields.h.

◆ GPIOTE_INTENSET_PORT_Disabled

#define GPIOTE_INTENSET_PORT_Disabled (0UL)

Interrupt disabled.

Definition at line 2716 of file nrf51_bitfields.h.

◆ GPIOTE_INTENSET_PORT_Enabled

#define GPIOTE_INTENSET_PORT_Enabled (1UL)

Interrupt enabled.

Definition at line 2717 of file nrf51_bitfields.h.

◆ GPIOTE_INTENSET_PORT_Msk

#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos)

Bit mask of PORT field.

Definition at line 2715 of file nrf51_bitfields.h.

◆ GPIOTE_INTENSET_PORT_Pos

#define GPIOTE_INTENSET_PORT_Pos (31UL)

Position of PORT field.

Definition at line 2714 of file nrf51_bitfields.h.

◆ GPIOTE_INTENSET_PORT_Set

#define GPIOTE_INTENSET_PORT_Set (1UL)

Enable interrupt on write.

Definition at line 2718 of file nrf51_bitfields.h.

◆ GPIOTE_POWER_POWER_Disabled

#define GPIOTE_POWER_POWER_Disabled (0UL)

Module power disabled.

Definition at line 2820 of file nrf51_bitfields.h.

◆ GPIOTE_POWER_POWER_Enabled

#define GPIOTE_POWER_POWER_Enabled (1UL)

Module power enabled.

Definition at line 2821 of file nrf51_bitfields.h.

◆ GPIOTE_POWER_POWER_Msk

#define GPIOTE_POWER_POWER_Msk (0x1UL << GPIOTE_POWER_POWER_Pos)

Bit mask of POWER field.

Definition at line 2819 of file nrf51_bitfields.h.

◆ GPIOTE_POWER_POWER_Pos

#define GPIOTE_POWER_POWER_Pos (0UL)

Position of POWER field.

Definition at line 2818 of file nrf51_bitfields.h.

◆ LPCOMP_ANADETECT_ANADETECT_Cross

#define LPCOMP_ANADETECT_ANADETECT_Cross (0UL)

Generate ANADETEC on crossing, both upwards and downwards crossing.

Definition at line 2985 of file nrf51_bitfields.h.

◆ LPCOMP_ANADETECT_ANADETECT_Down

#define LPCOMP_ANADETECT_ANADETECT_Down (2UL)

Generate ANADETEC on downwards crossing only.

Definition at line 2987 of file nrf51_bitfields.h.

◆ LPCOMP_ANADETECT_ANADETECT_Msk

#define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos)

Bit mask of ANADETECT field.

Definition at line 2984 of file nrf51_bitfields.h.

◆ LPCOMP_ANADETECT_ANADETECT_Pos

#define LPCOMP_ANADETECT_ANADETECT_Pos (0UL)

Position of ANADETECT field.

Definition at line 2983 of file nrf51_bitfields.h.

◆ LPCOMP_ANADETECT_ANADETECT_Up

#define LPCOMP_ANADETECT_ANADETECT_Up (1UL)

Generate ANADETEC on upwards crossing only.

Definition at line 2986 of file nrf51_bitfields.h.

◆ LPCOMP_ENABLE_ENABLE_Disabled

#define LPCOMP_ENABLE_ENABLE_Disabled (0x00UL)

Disabled LPCOMP.

Definition at line 2937 of file nrf51_bitfields.h.

◆ LPCOMP_ENABLE_ENABLE_Enabled

#define LPCOMP_ENABLE_ENABLE_Enabled (0x01UL)

Enable LPCOMP.

Definition at line 2938 of file nrf51_bitfields.h.

◆ LPCOMP_ENABLE_ENABLE_Msk

#define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos)

Bit mask of ENABLE field.

Definition at line 2936 of file nrf51_bitfields.h.

◆ LPCOMP_ENABLE_ENABLE_Pos

#define LPCOMP_ENABLE_ENABLE_Pos (0UL)

Position of ENABLE field.

Definition at line 2935 of file nrf51_bitfields.h.

◆ LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0

#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL)

Use analog reference 0 as reference.

Definition at line 2976 of file nrf51_bitfields.h.

◆ LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1

#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL)

Use analog reference 1 as reference.

Definition at line 2977 of file nrf51_bitfields.h.

◆ LPCOMP_EXTREFSEL_EXTREFSEL_Msk

#define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos)

Bit mask of EXTREFSEL field.

Definition at line 2975 of file nrf51_bitfields.h.

◆ LPCOMP_EXTREFSEL_EXTREFSEL_Pos

#define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL)

Position of EXTREFSEL field.

Definition at line 2974 of file nrf51_bitfields.h.

◆ LPCOMP_INTENCLR_CROSS_Clear

#define LPCOMP_INTENCLR_CROSS_Clear (1UL)

Disable interrupt on write.

Definition at line 2899 of file nrf51_bitfields.h.

◆ LPCOMP_INTENCLR_CROSS_Disabled

#define LPCOMP_INTENCLR_CROSS_Disabled (0UL)

Interrupt disabled.

Definition at line 2897 of file nrf51_bitfields.h.

◆ LPCOMP_INTENCLR_CROSS_Enabled

#define LPCOMP_INTENCLR_CROSS_Enabled (1UL)

Interrupt enabled.

Definition at line 2898 of file nrf51_bitfields.h.

◆ LPCOMP_INTENCLR_CROSS_Msk

#define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos)

Bit mask of CROSS field.

Definition at line 2896 of file nrf51_bitfields.h.

◆ LPCOMP_INTENCLR_CROSS_Pos

#define LPCOMP_INTENCLR_CROSS_Pos (3UL)

Position of CROSS field.

Definition at line 2895 of file nrf51_bitfields.h.

◆ LPCOMP_INTENCLR_DOWN_Clear

#define LPCOMP_INTENCLR_DOWN_Clear (1UL)

Disable interrupt on write.

Definition at line 2913 of file nrf51_bitfields.h.

◆ LPCOMP_INTENCLR_DOWN_Disabled

#define LPCOMP_INTENCLR_DOWN_Disabled (0UL)

Interrupt disabled.

Definition at line 2911 of file nrf51_bitfields.h.

◆ LPCOMP_INTENCLR_DOWN_Enabled

#define LPCOMP_INTENCLR_DOWN_Enabled (1UL)

Interrupt enabled.

Definition at line 2912 of file nrf51_bitfields.h.

◆ LPCOMP_INTENCLR_DOWN_Msk

#define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos)

Bit mask of DOWN field.

Definition at line 2910 of file nrf51_bitfields.h.

◆ LPCOMP_INTENCLR_DOWN_Pos

#define LPCOMP_INTENCLR_DOWN_Pos (1UL)

Position of DOWN field.

Definition at line 2909 of file nrf51_bitfields.h.

◆ LPCOMP_INTENCLR_READY_Clear

#define LPCOMP_INTENCLR_READY_Clear (1UL)

Disable interrupt on write.

Definition at line 2920 of file nrf51_bitfields.h.

◆ LPCOMP_INTENCLR_READY_Disabled

#define LPCOMP_INTENCLR_READY_Disabled (0UL)

Interrupt disabled.

Definition at line 2918 of file nrf51_bitfields.h.

◆ LPCOMP_INTENCLR_READY_Enabled

#define LPCOMP_INTENCLR_READY_Enabled (1UL)

Interrupt enabled.

Definition at line 2919 of file nrf51_bitfields.h.

◆ LPCOMP_INTENCLR_READY_Msk

#define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos)

Bit mask of READY field.

Definition at line 2917 of file nrf51_bitfields.h.

◆ LPCOMP_INTENCLR_READY_Pos

#define LPCOMP_INTENCLR_READY_Pos (0UL)

Position of READY field.

Definition at line 2916 of file nrf51_bitfields.h.

◆ LPCOMP_INTENCLR_UP_Clear

#define LPCOMP_INTENCLR_UP_Clear (1UL)

Disable interrupt on write.

Definition at line 2906 of file nrf51_bitfields.h.

◆ LPCOMP_INTENCLR_UP_Disabled

#define LPCOMP_INTENCLR_UP_Disabled (0UL)

Interrupt disabled.

Definition at line 2904 of file nrf51_bitfields.h.

◆ LPCOMP_INTENCLR_UP_Enabled

#define LPCOMP_INTENCLR_UP_Enabled (1UL)

Interrupt enabled.

Definition at line 2905 of file nrf51_bitfields.h.

◆ LPCOMP_INTENCLR_UP_Msk

#define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos)

Bit mask of UP field.

Definition at line 2903 of file nrf51_bitfields.h.

◆ LPCOMP_INTENCLR_UP_Pos

#define LPCOMP_INTENCLR_UP_Pos (2UL)

Position of UP field.

Definition at line 2902 of file nrf51_bitfields.h.

◆ LPCOMP_INTENSET_CROSS_Disabled

#define LPCOMP_INTENSET_CROSS_Disabled (0UL)

Interrupt disabled.

Definition at line 2866 of file nrf51_bitfields.h.

◆ LPCOMP_INTENSET_CROSS_Enabled

#define LPCOMP_INTENSET_CROSS_Enabled (1UL)

Interrupt enabled.

Definition at line 2867 of file nrf51_bitfields.h.

◆ LPCOMP_INTENSET_CROSS_Msk

#define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos)

Bit mask of CROSS field.

Definition at line 2865 of file nrf51_bitfields.h.

◆ LPCOMP_INTENSET_CROSS_Pos

#define LPCOMP_INTENSET_CROSS_Pos (3UL)

Position of CROSS field.

Definition at line 2864 of file nrf51_bitfields.h.

◆ LPCOMP_INTENSET_CROSS_Set

#define LPCOMP_INTENSET_CROSS_Set (1UL)

Enable interrupt on write.

Definition at line 2868 of file nrf51_bitfields.h.

◆ LPCOMP_INTENSET_DOWN_Disabled

#define LPCOMP_INTENSET_DOWN_Disabled (0UL)

Interrupt disabled.

Definition at line 2880 of file nrf51_bitfields.h.

◆ LPCOMP_INTENSET_DOWN_Enabled

#define LPCOMP_INTENSET_DOWN_Enabled (1UL)

Interrupt enabled.

Definition at line 2881 of file nrf51_bitfields.h.

◆ LPCOMP_INTENSET_DOWN_Msk

#define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos)

Bit mask of DOWN field.

Definition at line 2879 of file nrf51_bitfields.h.

◆ LPCOMP_INTENSET_DOWN_Pos

#define LPCOMP_INTENSET_DOWN_Pos (1UL)

Position of DOWN field.

Definition at line 2878 of file nrf51_bitfields.h.

◆ LPCOMP_INTENSET_DOWN_Set

#define LPCOMP_INTENSET_DOWN_Set (1UL)

Enable interrupt on write.

Definition at line 2882 of file nrf51_bitfields.h.

◆ LPCOMP_INTENSET_READY_Disabled

#define LPCOMP_INTENSET_READY_Disabled (0UL)

Interrupt disabled.

Definition at line 2887 of file nrf51_bitfields.h.

◆ LPCOMP_INTENSET_READY_Enabled

#define LPCOMP_INTENSET_READY_Enabled (1UL)

Interrupt enabled.

Definition at line 2888 of file nrf51_bitfields.h.

◆ LPCOMP_INTENSET_READY_Msk

#define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos)

Bit mask of READY field.

Definition at line 2886 of file nrf51_bitfields.h.

◆ LPCOMP_INTENSET_READY_Pos

#define LPCOMP_INTENSET_READY_Pos (0UL)

Position of READY field.

Definition at line 2885 of file nrf51_bitfields.h.

◆ LPCOMP_INTENSET_READY_Set

#define LPCOMP_INTENSET_READY_Set (1UL)

Enable interrupt on write.

Definition at line 2889 of file nrf51_bitfields.h.

◆ LPCOMP_INTENSET_UP_Disabled

#define LPCOMP_INTENSET_UP_Disabled (0UL)

Interrupt disabled.

Definition at line 2873 of file nrf51_bitfields.h.

◆ LPCOMP_INTENSET_UP_Enabled

#define LPCOMP_INTENSET_UP_Enabled (1UL)

Interrupt enabled.

Definition at line 2874 of file nrf51_bitfields.h.

◆ LPCOMP_INTENSET_UP_Msk

#define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos)

Bit mask of UP field.

Definition at line 2872 of file nrf51_bitfields.h.

◆ LPCOMP_INTENSET_UP_Pos

#define LPCOMP_INTENSET_UP_Pos (2UL)

Position of UP field.

Definition at line 2871 of file nrf51_bitfields.h.

◆ LPCOMP_INTENSET_UP_Set

#define LPCOMP_INTENSET_UP_Set (1UL)

Enable interrupt on write.

Definition at line 2875 of file nrf51_bitfields.h.

◆ LPCOMP_POWER_POWER_Disabled

#define LPCOMP_POWER_POWER_Disabled (0UL)

Module power disabled.

Definition at line 2995 of file nrf51_bitfields.h.

◆ LPCOMP_POWER_POWER_Enabled

#define LPCOMP_POWER_POWER_Enabled (1UL)

Module power enabled.

Definition at line 2996 of file nrf51_bitfields.h.

◆ LPCOMP_POWER_POWER_Msk

#define LPCOMP_POWER_POWER_Msk (0x1UL << LPCOMP_POWER_POWER_Pos)

Bit mask of POWER field.

Definition at line 2994 of file nrf51_bitfields.h.

◆ LPCOMP_POWER_POWER_Pos

#define LPCOMP_POWER_POWER_Pos (0UL)

Position of POWER field.

Definition at line 2993 of file nrf51_bitfields.h.

◆ LPCOMP_PSEL_PSEL_AnalogInput0

#define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL)

Use analog input 0 as analog input.

Definition at line 2946 of file nrf51_bitfields.h.

◆ LPCOMP_PSEL_PSEL_AnalogInput1

#define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL)

Use analog input 1 as analog input.

Definition at line 2947 of file nrf51_bitfields.h.

◆ LPCOMP_PSEL_PSEL_AnalogInput2

#define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL)

Use analog input 2 as analog input.

Definition at line 2948 of file nrf51_bitfields.h.

◆ LPCOMP_PSEL_PSEL_AnalogInput3

#define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL)

Use analog input 3 as analog input.

Definition at line 2949 of file nrf51_bitfields.h.

◆ LPCOMP_PSEL_PSEL_AnalogInput4

#define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL)

Use analog input 4 as analog input.

Definition at line 2950 of file nrf51_bitfields.h.

◆ LPCOMP_PSEL_PSEL_AnalogInput5

#define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL)

Use analog input 5 as analog input.

Definition at line 2951 of file nrf51_bitfields.h.

◆ LPCOMP_PSEL_PSEL_AnalogInput6

#define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL)

Use analog input 6 as analog input.

Definition at line 2952 of file nrf51_bitfields.h.

◆ LPCOMP_PSEL_PSEL_AnalogInput7

#define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL)

Use analog input 7 as analog input.

Definition at line 2953 of file nrf51_bitfields.h.

◆ LPCOMP_PSEL_PSEL_Msk

#define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos)

Bit mask of PSEL field.

Definition at line 2945 of file nrf51_bitfields.h.

◆ LPCOMP_PSEL_PSEL_Pos

#define LPCOMP_PSEL_PSEL_Pos (0UL)

Position of PSEL field.

Definition at line 2944 of file nrf51_bitfields.h.

◆ LPCOMP_REFSEL_REFSEL_ARef

#define LPCOMP_REFSEL_REFSEL_ARef (7UL)

Use external analog reference as reference.

Definition at line 2968 of file nrf51_bitfields.h.

◆ LPCOMP_REFSEL_REFSEL_Msk

#define LPCOMP_REFSEL_REFSEL_Msk (0x7UL << LPCOMP_REFSEL_REFSEL_Pos)

Bit mask of REFSEL field.

Definition at line 2960 of file nrf51_bitfields.h.

◆ LPCOMP_REFSEL_REFSEL_Pos

#define LPCOMP_REFSEL_REFSEL_Pos (0UL)

Position of REFSEL field.

Definition at line 2959 of file nrf51_bitfields.h.

◆ LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling

#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling (4UL)

Use supply with a 5/8 prescaler as reference.

Definition at line 2965 of file nrf51_bitfields.h.

◆ LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling

#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling (3UL)

Use supply with a 4/8 prescaler as reference.

Definition at line 2964 of file nrf51_bitfields.h.

◆ LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling

#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling (0UL)

Use supply with a 1/8 prescaler as reference.

Definition at line 2961 of file nrf51_bitfields.h.

◆ LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling

#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling (6UL)

Use supply with a 7/8 prescaler as reference.

Definition at line 2967 of file nrf51_bitfields.h.

◆ LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling

#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling (5UL)

Use supply with a 6/8 prescaler as reference.

Definition at line 2966 of file nrf51_bitfields.h.

◆ LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling

#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling (2UL)

Use supply with a 3/8 prescaler as reference.

Definition at line 2963 of file nrf51_bitfields.h.

◆ LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling

#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling (1UL)

Use supply with a 2/8 prescaler as reference.

Definition at line 2962 of file nrf51_bitfields.h.

◆ LPCOMP_RESULT_RESULT_Above

#define LPCOMP_RESULT_RESULT_Above (1UL)

Input voltage is above the reference threshold.

Definition at line 2929 of file nrf51_bitfields.h.

◆ LPCOMP_RESULT_RESULT_Bellow

#define LPCOMP_RESULT_RESULT_Bellow (0UL)

Input voltage is bellow the reference threshold.

Definition at line 2928 of file nrf51_bitfields.h.

◆ LPCOMP_RESULT_RESULT_Msk

#define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos)

Bit mask of RESULT field.

Definition at line 2927 of file nrf51_bitfields.h.

◆ LPCOMP_RESULT_RESULT_Pos

#define LPCOMP_RESULT_RESULT_Pos (0UL)

Position of RESULT field.

Definition at line 2926 of file nrf51_bitfields.h.

◆ LPCOMP_SHORTS_CROSS_STOP_Disabled

#define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL)

Shortcut disabled.

Definition at line 2833 of file nrf51_bitfields.h.

◆ LPCOMP_SHORTS_CROSS_STOP_Enabled

#define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL)

Shortcut enabled.

Definition at line 2834 of file nrf51_bitfields.h.

◆ LPCOMP_SHORTS_CROSS_STOP_Msk

#define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos)

Bit mask of CROSS_STOP field.

Definition at line 2832 of file nrf51_bitfields.h.

◆ LPCOMP_SHORTS_CROSS_STOP_Pos

#define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL)

Position of CROSS_STOP field.

Definition at line 2831 of file nrf51_bitfields.h.

◆ LPCOMP_SHORTS_DOWN_STOP_Disabled

#define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL)

Shortcut disabled.

Definition at line 2845 of file nrf51_bitfields.h.

◆ LPCOMP_SHORTS_DOWN_STOP_Enabled

#define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL)

Shortcut enabled.

Definition at line 2846 of file nrf51_bitfields.h.

◆ LPCOMP_SHORTS_DOWN_STOP_Msk

#define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos)

Bit mask of DOWN_STOP field.

Definition at line 2844 of file nrf51_bitfields.h.

◆ LPCOMP_SHORTS_DOWN_STOP_Pos

#define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL)

Position of DOWN_STOP field.

Definition at line 2843 of file nrf51_bitfields.h.

◆ LPCOMP_SHORTS_READY_SAMPLE_Disabled

#define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL)

Shortcut disabled.

Definition at line 2857 of file nrf51_bitfields.h.

◆ LPCOMP_SHORTS_READY_SAMPLE_Enabled

#define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL)

Shortcut enabled.

Definition at line 2858 of file nrf51_bitfields.h.

◆ LPCOMP_SHORTS_READY_SAMPLE_Msk

#define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos)

Bit mask of READY_SAMPLE field.

Definition at line 2856 of file nrf51_bitfields.h.

◆ LPCOMP_SHORTS_READY_SAMPLE_Pos

#define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL)

Position of READY_SAMPLE field.

Definition at line 2855 of file nrf51_bitfields.h.

◆ LPCOMP_SHORTS_READY_STOP_Disabled

#define LPCOMP_SHORTS_READY_STOP_Disabled (0UL)

Shortcut disabled.

Definition at line 2851 of file nrf51_bitfields.h.

◆ LPCOMP_SHORTS_READY_STOP_Enabled

#define LPCOMP_SHORTS_READY_STOP_Enabled (1UL)

Shortcut enabled.

Definition at line 2852 of file nrf51_bitfields.h.

◆ LPCOMP_SHORTS_READY_STOP_Msk

#define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos)

Bit mask of READY_STOP field.

Definition at line 2850 of file nrf51_bitfields.h.

◆ LPCOMP_SHORTS_READY_STOP_Pos

#define LPCOMP_SHORTS_READY_STOP_Pos (1UL)

Position of READY_STOP field.

Definition at line 2849 of file nrf51_bitfields.h.

◆ LPCOMP_SHORTS_UP_STOP_Disabled

#define LPCOMP_SHORTS_UP_STOP_Disabled (0UL)

Shortcut disabled.

Definition at line 2839 of file nrf51_bitfields.h.

◆ LPCOMP_SHORTS_UP_STOP_Enabled

#define LPCOMP_SHORTS_UP_STOP_Enabled (1UL)

Shortcut enabled.

Definition at line 2840 of file nrf51_bitfields.h.

◆ LPCOMP_SHORTS_UP_STOP_Msk

#define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos)

Bit mask of UP_STOP field.

Definition at line 2838 of file nrf51_bitfields.h.

◆ LPCOMP_SHORTS_UP_STOP_Pos

#define LPCOMP_SHORTS_UP_STOP_Pos (3UL)

Position of UP_STOP field.

Definition at line 2837 of file nrf51_bitfields.h.

◆ MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled

#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL)

Protection disabled.

Definition at line 3592 of file nrf51_bitfields.h.

◆ MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled

#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL)

Protection enabled.

Definition at line 3591 of file nrf51_bitfields.h.

◆ MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk

#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos)

Bit mask of DISABLEINDEBUG field.

Definition at line 3590 of file nrf51_bitfields.h.

◆ MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos

#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL)

Position of DISABLEINDEBUG field.

Definition at line 3589 of file nrf51_bitfields.h.

◆ MPU_PERR0_ADC_InRegion0

#define MPU_PERR0_ADC_InRegion0 (1UL)

Peripheral configured in region 0.

Definition at line 3093 of file nrf51_bitfields.h.

◆ MPU_PERR0_ADC_InRegion1

#define MPU_PERR0_ADC_InRegion1 (0UL)

Peripheral configured in region 1.

Definition at line 3092 of file nrf51_bitfields.h.

◆ MPU_PERR0_ADC_Msk

#define MPU_PERR0_ADC_Msk (0x1UL << MPU_PERR0_ADC_Pos)

Bit mask of ADC field.

Definition at line 3091 of file nrf51_bitfields.h.

◆ MPU_PERR0_ADC_Pos

#define MPU_PERR0_ADC_Pos (7UL)

Position of ADC field.

Definition at line 3090 of file nrf51_bitfields.h.

◆ MPU_PERR0_CCM_AAR_InRegion0

#define MPU_PERR0_CCM_AAR_InRegion0 (1UL)

Peripheral configured in region 0.

Definition at line 3045 of file nrf51_bitfields.h.

◆ MPU_PERR0_CCM_AAR_InRegion1

#define MPU_PERR0_CCM_AAR_InRegion1 (0UL)

Peripheral configured in region 1.

Definition at line 3044 of file nrf51_bitfields.h.

◆ MPU_PERR0_CCM_AAR_Msk

#define MPU_PERR0_CCM_AAR_Msk (0x1UL << MPU_PERR0_CCM_AAR_Pos)

Bit mask of CCM_AAR field.

Definition at line 3043 of file nrf51_bitfields.h.

◆ MPU_PERR0_CCM_AAR_Pos

#define MPU_PERR0_CCM_AAR_Pos (15UL)

Position of CCM_AAR field.

Definition at line 3042 of file nrf51_bitfields.h.

◆ MPU_PERR0_ECB_InRegion0

#define MPU_PERR0_ECB_InRegion0 (1UL)

Peripheral configured in region 0.

Definition at line 3051 of file nrf51_bitfields.h.

◆ MPU_PERR0_ECB_InRegion1

#define MPU_PERR0_ECB_InRegion1 (0UL)

Peripheral configured in region 1.

Definition at line 3050 of file nrf51_bitfields.h.

◆ MPU_PERR0_ECB_Msk

#define MPU_PERR0_ECB_Msk (0x1UL << MPU_PERR0_ECB_Pos)

Bit mask of ECB field.

Definition at line 3049 of file nrf51_bitfields.h.

◆ MPU_PERR0_ECB_Pos

#define MPU_PERR0_ECB_Pos (14UL)

Position of ECB field.

Definition at line 3048 of file nrf51_bitfields.h.

◆ MPU_PERR0_GPIOTE_InRegion0

#define MPU_PERR0_GPIOTE_InRegion0 (1UL)

Peripheral configured in region 0.

Definition at line 3099 of file nrf51_bitfields.h.

◆ MPU_PERR0_GPIOTE_InRegion1

#define MPU_PERR0_GPIOTE_InRegion1 (0UL)

Peripheral configured in region 1.

Definition at line 3098 of file nrf51_bitfields.h.

◆ MPU_PERR0_GPIOTE_Msk

#define MPU_PERR0_GPIOTE_Msk (0x1UL << MPU_PERR0_GPIOTE_Pos)

Bit mask of GPIOTE field.

Definition at line 3097 of file nrf51_bitfields.h.

◆ MPU_PERR0_GPIOTE_Pos

#define MPU_PERR0_GPIOTE_Pos (6UL)

Position of GPIOTE field.

Definition at line 3096 of file nrf51_bitfields.h.

◆ MPU_PERR0_LPCOMP_InRegion0

#define MPU_PERR0_LPCOMP_InRegion0 (1UL)

Peripheral configured in region 0.

Definition at line 3021 of file nrf51_bitfields.h.

◆ MPU_PERR0_LPCOMP_InRegion1

#define MPU_PERR0_LPCOMP_InRegion1 (0UL)

Peripheral configured in region 1.

Definition at line 3020 of file nrf51_bitfields.h.

◆ MPU_PERR0_LPCOMP_Msk

#define MPU_PERR0_LPCOMP_Msk (0x1UL << MPU_PERR0_LPCOMP_Pos)

Bit mask of LPCOMP field.

Definition at line 3019 of file nrf51_bitfields.h.

◆ MPU_PERR0_LPCOMP_Pos

#define MPU_PERR0_LPCOMP_Pos (19UL)

Position of LPCOMP field.

Definition at line 3018 of file nrf51_bitfields.h.

◆ MPU_PERR0_NVMC_InRegion0

#define MPU_PERR0_NVMC_InRegion0 (1UL)

Peripheral configured in region 0.

Definition at line 3015 of file nrf51_bitfields.h.

◆ MPU_PERR0_NVMC_InRegion1

#define MPU_PERR0_NVMC_InRegion1 (0UL)

Peripheral configured in region 1.

Definition at line 3014 of file nrf51_bitfields.h.

◆ MPU_PERR0_NVMC_Msk

#define MPU_PERR0_NVMC_Msk (0x1UL << MPU_PERR0_NVMC_Pos)

Bit mask of NVMC field.

Definition at line 3013 of file nrf51_bitfields.h.

◆ MPU_PERR0_NVMC_Pos

#define MPU_PERR0_NVMC_Pos (30UL)

Position of NVMC field.

Definition at line 3012 of file nrf51_bitfields.h.

◆ MPU_PERR0_POWER_CLOCK_InRegion0

#define MPU_PERR0_POWER_CLOCK_InRegion0 (1UL)

Peripheral configured in region 0.

Definition at line 3129 of file nrf51_bitfields.h.

◆ MPU_PERR0_POWER_CLOCK_InRegion1

#define MPU_PERR0_POWER_CLOCK_InRegion1 (0UL)

Peripheral configured in region 1.

Definition at line 3128 of file nrf51_bitfields.h.

◆ MPU_PERR0_POWER_CLOCK_Msk

#define MPU_PERR0_POWER_CLOCK_Msk (0x1UL << MPU_PERR0_POWER_CLOCK_Pos)

Bit mask of POWER_CLOCK field.

Definition at line 3127 of file nrf51_bitfields.h.

◆ MPU_PERR0_POWER_CLOCK_Pos

#define MPU_PERR0_POWER_CLOCK_Pos (0UL)

Position of POWER_CLOCK field.

Definition at line 3126 of file nrf51_bitfields.h.

◆ MPU_PERR0_PPI_InRegion0

#define MPU_PERR0_PPI_InRegion0 (1UL)

Peripheral configured in region 0.

Definition at line 3009 of file nrf51_bitfields.h.

◆ MPU_PERR0_PPI_InRegion1

#define MPU_PERR0_PPI_InRegion1 (0UL)

Peripheral configured in region 1.

Definition at line 3008 of file nrf51_bitfields.h.

◆ MPU_PERR0_PPI_Msk

#define MPU_PERR0_PPI_Msk (0x1UL << MPU_PERR0_PPI_Pos)

Bit mask of PPI field.

Definition at line 3007 of file nrf51_bitfields.h.

◆ MPU_PERR0_PPI_Pos

#define MPU_PERR0_PPI_Pos (31UL)

Position of PPI field.

Definition at line 3006 of file nrf51_bitfields.h.

◆ MPU_PERR0_QDEC_InRegion0

#define MPU_PERR0_QDEC_InRegion0 (1UL)

Peripheral configured in region 0.

Definition at line 3027 of file nrf51_bitfields.h.

◆ MPU_PERR0_QDEC_InRegion1

#define MPU_PERR0_QDEC_InRegion1 (0UL)

Peripheral configured in region 1.

Definition at line 3026 of file nrf51_bitfields.h.

◆ MPU_PERR0_QDEC_Msk

#define MPU_PERR0_QDEC_Msk (0x1UL << MPU_PERR0_QDEC_Pos)

Bit mask of QDEC field.

Definition at line 3025 of file nrf51_bitfields.h.

◆ MPU_PERR0_QDEC_Pos

#define MPU_PERR0_QDEC_Pos (18UL)

Position of QDEC field.

Definition at line 3024 of file nrf51_bitfields.h.

◆ MPU_PERR0_RADIO_InRegion0

#define MPU_PERR0_RADIO_InRegion0 (1UL)

Peripheral configured in region 0.

Definition at line 3123 of file nrf51_bitfields.h.

◆ MPU_PERR0_RADIO_InRegion1

#define MPU_PERR0_RADIO_InRegion1 (0UL)

Peripheral configured in region 1.

Definition at line 3122 of file nrf51_bitfields.h.

◆ MPU_PERR0_RADIO_Msk

#define MPU_PERR0_RADIO_Msk (0x1UL << MPU_PERR0_RADIO_Pos)

Bit mask of RADIO field.

Definition at line 3121 of file nrf51_bitfields.h.

◆ MPU_PERR0_RADIO_Pos

#define MPU_PERR0_RADIO_Pos (1UL)

Position of RADIO field.

Definition at line 3120 of file nrf51_bitfields.h.

◆ MPU_PERR0_RNG_InRegion0

#define MPU_PERR0_RNG_InRegion0 (1UL)

Peripheral configured in region 0.

Definition at line 3057 of file nrf51_bitfields.h.

◆ MPU_PERR0_RNG_InRegion1

#define MPU_PERR0_RNG_InRegion1 (0UL)

Peripheral configured in region 1.

Definition at line 3056 of file nrf51_bitfields.h.

◆ MPU_PERR0_RNG_Msk

#define MPU_PERR0_RNG_Msk (0x1UL << MPU_PERR0_RNG_Pos)

Bit mask of RNG field.

Definition at line 3055 of file nrf51_bitfields.h.

◆ MPU_PERR0_RNG_Pos

#define MPU_PERR0_RNG_Pos (13UL)

Position of RNG field.

Definition at line 3054 of file nrf51_bitfields.h.

◆ MPU_PERR0_RTC0_InRegion0

#define MPU_PERR0_RTC0_InRegion0 (1UL)

Peripheral configured in region 0.

Definition at line 3069 of file nrf51_bitfields.h.

◆ MPU_PERR0_RTC0_InRegion1

#define MPU_PERR0_RTC0_InRegion1 (0UL)

Peripheral configured in region 1.

Definition at line 3068 of file nrf51_bitfields.h.

◆ MPU_PERR0_RTC0_Msk

#define MPU_PERR0_RTC0_Msk (0x1UL << MPU_PERR0_RTC0_Pos)

Bit mask of RTC0 field.

Definition at line 3067 of file nrf51_bitfields.h.

◆ MPU_PERR0_RTC0_Pos

#define MPU_PERR0_RTC0_Pos (11UL)

Position of RTC0 field.

Definition at line 3066 of file nrf51_bitfields.h.

◆ MPU_PERR0_RTC1_InRegion0

#define MPU_PERR0_RTC1_InRegion0 (1UL)

Peripheral configured in region 0.

Definition at line 3033 of file nrf51_bitfields.h.

◆ MPU_PERR0_RTC1_InRegion1

#define MPU_PERR0_RTC1_InRegion1 (0UL)

Peripheral configured in region 1.

Definition at line 3032 of file nrf51_bitfields.h.

◆ MPU_PERR0_RTC1_Msk

#define MPU_PERR0_RTC1_Msk (0x1UL << MPU_PERR0_RTC1_Pos)

Bit mask of RTC1 field.

Definition at line 3031 of file nrf51_bitfields.h.

◆ MPU_PERR0_RTC1_Pos

#define MPU_PERR0_RTC1_Pos (17UL)

Position of RTC1 field.

Definition at line 3030 of file nrf51_bitfields.h.

◆ MPU_PERR0_SPI0_TWI0_InRegion0

#define MPU_PERR0_SPI0_TWI0_InRegion0 (1UL)

Peripheral configured in region 0.

Definition at line 3111 of file nrf51_bitfields.h.

◆ MPU_PERR0_SPI0_TWI0_InRegion1

#define MPU_PERR0_SPI0_TWI0_InRegion1 (0UL)

Peripheral configured in region 1.

Definition at line 3110 of file nrf51_bitfields.h.

◆ MPU_PERR0_SPI0_TWI0_Msk

#define MPU_PERR0_SPI0_TWI0_Msk (0x1UL << MPU_PERR0_SPI0_TWI0_Pos)

Bit mask of SPI0_TWI0 field.

Definition at line 3109 of file nrf51_bitfields.h.

◆ MPU_PERR0_SPI0_TWI0_Pos

#define MPU_PERR0_SPI0_TWI0_Pos (3UL)

Position of SPI0_TWI0 field.

Definition at line 3108 of file nrf51_bitfields.h.

◆ MPU_PERR0_SPI1_TWI1_InRegion0

#define MPU_PERR0_SPI1_TWI1_InRegion0 (1UL)

Peripheral configured in region 0.

Definition at line 3105 of file nrf51_bitfields.h.

◆ MPU_PERR0_SPI1_TWI1_InRegion1

#define MPU_PERR0_SPI1_TWI1_InRegion1 (0UL)

Peripheral configured in region 1.

Definition at line 3104 of file nrf51_bitfields.h.

◆ MPU_PERR0_SPI1_TWI1_Msk

#define MPU_PERR0_SPI1_TWI1_Msk (0x1UL << MPU_PERR0_SPI1_TWI1_Pos)

Bit mask of SPI1_TWI1 field.

Definition at line 3103 of file nrf51_bitfields.h.

◆ MPU_PERR0_SPI1_TWI1_Pos

#define MPU_PERR0_SPI1_TWI1_Pos (4UL)

Position of SPI1_TWI1 field.

Definition at line 3102 of file nrf51_bitfields.h.

◆ MPU_PERR0_TEMP_InRegion0

#define MPU_PERR0_TEMP_InRegion0 (1UL)

Peripheral configured in region 0.

Definition at line 3063 of file nrf51_bitfields.h.

◆ MPU_PERR0_TEMP_InRegion1

#define MPU_PERR0_TEMP_InRegion1 (0UL)

Peripheral configured in region 1.

Definition at line 3062 of file nrf51_bitfields.h.

◆ MPU_PERR0_TEMP_Msk

#define MPU_PERR0_TEMP_Msk (0x1UL << MPU_PERR0_TEMP_Pos)

Bit mask of TEMP field.

Definition at line 3061 of file nrf51_bitfields.h.

◆ MPU_PERR0_TEMP_Pos

#define MPU_PERR0_TEMP_Pos (12UL)

Position of TEMP field.

Definition at line 3060 of file nrf51_bitfields.h.

◆ MPU_PERR0_TIMER0_InRegion0

#define MPU_PERR0_TIMER0_InRegion0 (1UL)

Peripheral configured in region 0.

Definition at line 3087 of file nrf51_bitfields.h.

◆ MPU_PERR0_TIMER0_InRegion1

#define MPU_PERR0_TIMER0_InRegion1 (0UL)

Peripheral configured in region 1.

Definition at line 3086 of file nrf51_bitfields.h.

◆ MPU_PERR0_TIMER0_Msk

#define MPU_PERR0_TIMER0_Msk (0x1UL << MPU_PERR0_TIMER0_Pos)

Bit mask of TIMER0 field.

Definition at line 3085 of file nrf51_bitfields.h.

◆ MPU_PERR0_TIMER0_Pos

#define MPU_PERR0_TIMER0_Pos (8UL)

Position of TIMER0 field.

Definition at line 3084 of file nrf51_bitfields.h.

◆ MPU_PERR0_TIMER1_InRegion0

#define MPU_PERR0_TIMER1_InRegion0 (1UL)

Peripheral configured in region 0.

Definition at line 3081 of file nrf51_bitfields.h.

◆ MPU_PERR0_TIMER1_InRegion1

#define MPU_PERR0_TIMER1_InRegion1 (0UL)

Peripheral configured in region 1.

Definition at line 3080 of file nrf51_bitfields.h.

◆ MPU_PERR0_TIMER1_Msk

#define MPU_PERR0_TIMER1_Msk (0x1UL << MPU_PERR0_TIMER1_Pos)

Bit mask of TIMER1 field.

Definition at line 3079 of file nrf51_bitfields.h.

◆ MPU_PERR0_TIMER1_Pos

#define MPU_PERR0_TIMER1_Pos (9UL)

Position of TIMER1 field.

Definition at line 3078 of file nrf51_bitfields.h.

◆ MPU_PERR0_TIMER2_InRegion0

#define MPU_PERR0_TIMER2_InRegion0 (1UL)

Peripheral configured in region 0.

Definition at line 3075 of file nrf51_bitfields.h.

◆ MPU_PERR0_TIMER2_InRegion1

#define MPU_PERR0_TIMER2_InRegion1 (0UL)

Peripheral configured in region 1.

Definition at line 3074 of file nrf51_bitfields.h.

◆ MPU_PERR0_TIMER2_Msk

#define MPU_PERR0_TIMER2_Msk (0x1UL << MPU_PERR0_TIMER2_Pos)

Bit mask of TIMER2 field.

Definition at line 3073 of file nrf51_bitfields.h.

◆ MPU_PERR0_TIMER2_Pos

#define MPU_PERR0_TIMER2_Pos (10UL)

Position of TIMER2 field.

Definition at line 3072 of file nrf51_bitfields.h.

◆ MPU_PERR0_UART0_InRegion0

#define MPU_PERR0_UART0_InRegion0 (1UL)

Peripheral configured in region 0.

Definition at line 3117 of file nrf51_bitfields.h.

◆ MPU_PERR0_UART0_InRegion1

#define MPU_PERR0_UART0_InRegion1 (0UL)

Peripheral configured in region 1.

Definition at line 3116 of file nrf51_bitfields.h.

◆ MPU_PERR0_UART0_Msk

#define MPU_PERR0_UART0_Msk (0x1UL << MPU_PERR0_UART0_Pos)

Bit mask of UART0 field.

Definition at line 3115 of file nrf51_bitfields.h.

◆ MPU_PERR0_UART0_Pos

#define MPU_PERR0_UART0_Pos (2UL)

Position of UART0 field.

Definition at line 3114 of file nrf51_bitfields.h.

◆ MPU_PERR0_WDT_InRegion0

#define MPU_PERR0_WDT_InRegion0 (1UL)

Peripheral configured in region 0.

Definition at line 3039 of file nrf51_bitfields.h.

◆ MPU_PERR0_WDT_InRegion1

#define MPU_PERR0_WDT_InRegion1 (0UL)

Peripheral configured in region 1.

Definition at line 3038 of file nrf51_bitfields.h.

◆ MPU_PERR0_WDT_Msk

#define MPU_PERR0_WDT_Msk (0x1UL << MPU_PERR0_WDT_Pos)

Bit mask of WDT field.

Definition at line 3037 of file nrf51_bitfields.h.

◆ MPU_PERR0_WDT_Pos

#define MPU_PERR0_WDT_Pos (16UL)

Position of WDT field.

Definition at line 3036 of file nrf51_bitfields.h.

◆ MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_4k

#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_4k (0UL)

Erase and write protection block size is 4k.

Definition at line 3600 of file nrf51_bitfields.h.

◆ MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Msk

#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Msk (0x3UL << MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos)

Bit mask of PROTBLOCKSIZE field.

Definition at line 3599 of file nrf51_bitfields.h.

◆ MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos

#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos (0UL)

Position of PROTBLOCKSIZE field.

Definition at line 3598 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG0_Disabled

#define MPU_PROTENSET0_PROTREG0_Disabled (0UL)

Protection disabled.

Definition at line 3354 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG0_Enabled

#define MPU_PROTENSET0_PROTREG0_Enabled (1UL)

Protection enabled.

Definition at line 3355 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG0_Msk

#define MPU_PROTENSET0_PROTREG0_Msk (0x1UL << MPU_PROTENSET0_PROTREG0_Pos)

Bit mask of PROTREG0 field.

Definition at line 3353 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG0_Pos

#define MPU_PROTENSET0_PROTREG0_Pos (0UL)

Position of PROTREG0 field.

Definition at line 3352 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG0_Set

#define MPU_PROTENSET0_PROTREG0_Set (1UL)

Enable protection on write.

Definition at line 3356 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG10_Disabled

#define MPU_PROTENSET0_PROTREG10_Disabled (0UL)

Protection disabled.

Definition at line 3284 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG10_Enabled

#define MPU_PROTENSET0_PROTREG10_Enabled (1UL)

Protection enabled.

Definition at line 3285 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG10_Msk

#define MPU_PROTENSET0_PROTREG10_Msk (0x1UL << MPU_PROTENSET0_PROTREG10_Pos)

Bit mask of PROTREG10 field.

Definition at line 3283 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG10_Pos

#define MPU_PROTENSET0_PROTREG10_Pos (10UL)

Position of PROTREG10 field.

Definition at line 3282 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG10_Set

#define MPU_PROTENSET0_PROTREG10_Set (1UL)

Enable protection on write.

Definition at line 3286 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG11_Disabled

#define MPU_PROTENSET0_PROTREG11_Disabled (0UL)

Protection disabled.

Definition at line 3277 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG11_Enabled

#define MPU_PROTENSET0_PROTREG11_Enabled (1UL)

Protection enabled.

Definition at line 3278 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG11_Msk

#define MPU_PROTENSET0_PROTREG11_Msk (0x1UL << MPU_PROTENSET0_PROTREG11_Pos)

Bit mask of PROTREG11 field.

Definition at line 3276 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG11_Pos

#define MPU_PROTENSET0_PROTREG11_Pos (11UL)

Position of PROTREG11 field.

Definition at line 3275 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG11_Set

#define MPU_PROTENSET0_PROTREG11_Set (1UL)

Enable protection on write.

Definition at line 3279 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG12_Disabled

#define MPU_PROTENSET0_PROTREG12_Disabled (0UL)

Protection disabled.

Definition at line 3270 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG12_Enabled

#define MPU_PROTENSET0_PROTREG12_Enabled (1UL)

Protection enabled.

Definition at line 3271 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG12_Msk

#define MPU_PROTENSET0_PROTREG12_Msk (0x1UL << MPU_PROTENSET0_PROTREG12_Pos)

Bit mask of PROTREG12 field.

Definition at line 3269 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG12_Pos

#define MPU_PROTENSET0_PROTREG12_Pos (12UL)

Position of PROTREG12 field.

Definition at line 3268 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG12_Set

#define MPU_PROTENSET0_PROTREG12_Set (1UL)

Enable protection on write.

Definition at line 3272 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG13_Disabled

#define MPU_PROTENSET0_PROTREG13_Disabled (0UL)

Protection disabled.

Definition at line 3263 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG13_Enabled

#define MPU_PROTENSET0_PROTREG13_Enabled (1UL)

Protection enabled.

Definition at line 3264 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG13_Msk

#define MPU_PROTENSET0_PROTREG13_Msk (0x1UL << MPU_PROTENSET0_PROTREG13_Pos)

Bit mask of PROTREG13 field.

Definition at line 3262 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG13_Pos

#define MPU_PROTENSET0_PROTREG13_Pos (13UL)

Position of PROTREG13 field.

Definition at line 3261 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG13_Set

#define MPU_PROTENSET0_PROTREG13_Set (1UL)

Enable protection on write.

Definition at line 3265 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG14_Disabled

#define MPU_PROTENSET0_PROTREG14_Disabled (0UL)

Protection disabled.

Definition at line 3256 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG14_Enabled

#define MPU_PROTENSET0_PROTREG14_Enabled (1UL)

Protection enabled.

Definition at line 3257 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG14_Msk

#define MPU_PROTENSET0_PROTREG14_Msk (0x1UL << MPU_PROTENSET0_PROTREG14_Pos)

Bit mask of PROTREG14 field.

Definition at line 3255 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG14_Pos

#define MPU_PROTENSET0_PROTREG14_Pos (14UL)

Position of PROTREG14 field.

Definition at line 3254 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG14_Set

#define MPU_PROTENSET0_PROTREG14_Set (1UL)

Enable protection on write.

Definition at line 3258 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG15_Disabled

#define MPU_PROTENSET0_PROTREG15_Disabled (0UL)

Protection disabled.

Definition at line 3249 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG15_Enabled

#define MPU_PROTENSET0_PROTREG15_Enabled (1UL)

Protection enabled.

Definition at line 3250 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG15_Msk

#define MPU_PROTENSET0_PROTREG15_Msk (0x1UL << MPU_PROTENSET0_PROTREG15_Pos)

Bit mask of PROTREG15 field.

Definition at line 3248 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG15_Pos

#define MPU_PROTENSET0_PROTREG15_Pos (15UL)

Position of PROTREG15 field.

Definition at line 3247 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG15_Set

#define MPU_PROTENSET0_PROTREG15_Set (1UL)

Enable protection on write.

Definition at line 3251 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG16_Disabled

#define MPU_PROTENSET0_PROTREG16_Disabled (0UL)

Protection disabled.

Definition at line 3242 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG16_Enabled

#define MPU_PROTENSET0_PROTREG16_Enabled (1UL)

Protection enabled.

Definition at line 3243 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG16_Msk

#define MPU_PROTENSET0_PROTREG16_Msk (0x1UL << MPU_PROTENSET0_PROTREG16_Pos)

Bit mask of PROTREG16 field.

Definition at line 3241 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG16_Pos

#define MPU_PROTENSET0_PROTREG16_Pos (16UL)

Position of PROTREG16 field.

Definition at line 3240 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG16_Set

#define MPU_PROTENSET0_PROTREG16_Set (1UL)

Enable protection on write.

Definition at line 3244 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG17_Disabled

#define MPU_PROTENSET0_PROTREG17_Disabled (0UL)

Protection disabled.

Definition at line 3235 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG17_Enabled

#define MPU_PROTENSET0_PROTREG17_Enabled (1UL)

Protection enabled.

Definition at line 3236 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG17_Msk

#define MPU_PROTENSET0_PROTREG17_Msk (0x1UL << MPU_PROTENSET0_PROTREG17_Pos)

Bit mask of PROTREG17 field.

Definition at line 3234 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG17_Pos

#define MPU_PROTENSET0_PROTREG17_Pos (17UL)

Position of PROTREG17 field.

Definition at line 3233 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG17_Set

#define MPU_PROTENSET0_PROTREG17_Set (1UL)

Enable protection on write.

Definition at line 3237 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG18_Disabled

#define MPU_PROTENSET0_PROTREG18_Disabled (0UL)

Protection disabled.

Definition at line 3228 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG18_Enabled

#define MPU_PROTENSET0_PROTREG18_Enabled (1UL)

Protection enabled.

Definition at line 3229 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG18_Msk

#define MPU_PROTENSET0_PROTREG18_Msk (0x1UL << MPU_PROTENSET0_PROTREG18_Pos)

Bit mask of PROTREG18 field.

Definition at line 3227 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG18_Pos

#define MPU_PROTENSET0_PROTREG18_Pos (18UL)

Position of PROTREG18 field.

Definition at line 3226 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG18_Set

#define MPU_PROTENSET0_PROTREG18_Set (1UL)

Enable protection on write.

Definition at line 3230 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG19_Disabled

#define MPU_PROTENSET0_PROTREG19_Disabled (0UL)

Protection disabled.

Definition at line 3221 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG19_Enabled

#define MPU_PROTENSET0_PROTREG19_Enabled (1UL)

Protection enabled.

Definition at line 3222 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG19_Msk

#define MPU_PROTENSET0_PROTREG19_Msk (0x1UL << MPU_PROTENSET0_PROTREG19_Pos)

Bit mask of PROTREG19 field.

Definition at line 3220 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG19_Pos

#define MPU_PROTENSET0_PROTREG19_Pos (19UL)

Position of PROTREG19 field.

Definition at line 3219 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG19_Set

#define MPU_PROTENSET0_PROTREG19_Set (1UL)

Enable protection on write.

Definition at line 3223 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG1_Disabled

#define MPU_PROTENSET0_PROTREG1_Disabled (0UL)

Protection disabled.

Definition at line 3347 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG1_Enabled

#define MPU_PROTENSET0_PROTREG1_Enabled (1UL)

Protection enabled.

Definition at line 3348 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG1_Msk

#define MPU_PROTENSET0_PROTREG1_Msk (0x1UL << MPU_PROTENSET0_PROTREG1_Pos)

Bit mask of PROTREG1 field.

Definition at line 3346 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG1_Pos

#define MPU_PROTENSET0_PROTREG1_Pos (1UL)

Position of PROTREG1 field.

Definition at line 3345 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG1_Set

#define MPU_PROTENSET0_PROTREG1_Set (1UL)

Enable protection on write.

Definition at line 3349 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG20_Disabled

#define MPU_PROTENSET0_PROTREG20_Disabled (0UL)

Protection disabled.

Definition at line 3214 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG20_Enabled

#define MPU_PROTENSET0_PROTREG20_Enabled (1UL)

Protection enabled.

Definition at line 3215 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG20_Msk

#define MPU_PROTENSET0_PROTREG20_Msk (0x1UL << MPU_PROTENSET0_PROTREG20_Pos)

Bit mask of PROTREG20 field.

Definition at line 3213 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG20_Pos

#define MPU_PROTENSET0_PROTREG20_Pos (20UL)

Position of PROTREG20 field.

Definition at line 3212 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG20_Set

#define MPU_PROTENSET0_PROTREG20_Set (1UL)

Enable protection on write.

Definition at line 3216 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG21_Disabled

#define MPU_PROTENSET0_PROTREG21_Disabled (0UL)

Protection disabled.

Definition at line 3207 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG21_Enabled

#define MPU_PROTENSET0_PROTREG21_Enabled (1UL)

Protection enabled.

Definition at line 3208 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG21_Msk

#define MPU_PROTENSET0_PROTREG21_Msk (0x1UL << MPU_PROTENSET0_PROTREG21_Pos)

Bit mask of PROTREG21 field.

Definition at line 3206 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG21_Pos

#define MPU_PROTENSET0_PROTREG21_Pos (21UL)

Position of PROTREG21 field.

Definition at line 3205 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG21_Set

#define MPU_PROTENSET0_PROTREG21_Set (1UL)

Enable protection on write.

Definition at line 3209 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG22_Disabled

#define MPU_PROTENSET0_PROTREG22_Disabled (0UL)

Protection disabled.

Definition at line 3200 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG22_Enabled

#define MPU_PROTENSET0_PROTREG22_Enabled (1UL)

Protection enabled.

Definition at line 3201 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG22_Msk

#define MPU_PROTENSET0_PROTREG22_Msk (0x1UL << MPU_PROTENSET0_PROTREG22_Pos)

Bit mask of PROTREG22 field.

Definition at line 3199 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG22_Pos

#define MPU_PROTENSET0_PROTREG22_Pos (22UL)

Position of PROTREG22 field.

Definition at line 3198 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG22_Set

#define MPU_PROTENSET0_PROTREG22_Set (1UL)

Enable protection on write.

Definition at line 3202 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG23_Disabled

#define MPU_PROTENSET0_PROTREG23_Disabled (0UL)

Protection disabled.

Definition at line 3193 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG23_Enabled

#define MPU_PROTENSET0_PROTREG23_Enabled (1UL)

Protection enabled.

Definition at line 3194 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG23_Msk

#define MPU_PROTENSET0_PROTREG23_Msk (0x1UL << MPU_PROTENSET0_PROTREG23_Pos)

Bit mask of PROTREG23 field.

Definition at line 3192 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG23_Pos

#define MPU_PROTENSET0_PROTREG23_Pos (23UL)

Position of PROTREG23 field.

Definition at line 3191 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG23_Set

#define MPU_PROTENSET0_PROTREG23_Set (1UL)

Enable protection on write.

Definition at line 3195 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG24_Disabled

#define MPU_PROTENSET0_PROTREG24_Disabled (0UL)

Protection disabled.

Definition at line 3186 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG24_Enabled

#define MPU_PROTENSET0_PROTREG24_Enabled (1UL)

Protection enabled.

Definition at line 3187 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG24_Msk

#define MPU_PROTENSET0_PROTREG24_Msk (0x1UL << MPU_PROTENSET0_PROTREG24_Pos)

Bit mask of PROTREG24 field.

Definition at line 3185 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG24_Pos

#define MPU_PROTENSET0_PROTREG24_Pos (24UL)

Position of PROTREG24 field.

Definition at line 3184 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG24_Set

#define MPU_PROTENSET0_PROTREG24_Set (1UL)

Enable protection on write.

Definition at line 3188 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG25_Disabled

#define MPU_PROTENSET0_PROTREG25_Disabled (0UL)

Protection disabled.

Definition at line 3179 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG25_Enabled

#define MPU_PROTENSET0_PROTREG25_Enabled (1UL)

Protection enabled.

Definition at line 3180 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG25_Msk

#define MPU_PROTENSET0_PROTREG25_Msk (0x1UL << MPU_PROTENSET0_PROTREG25_Pos)

Bit mask of PROTREG25 field.

Definition at line 3178 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG25_Pos

#define MPU_PROTENSET0_PROTREG25_Pos (25UL)

Position of PROTREG25 field.

Definition at line 3177 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG25_Set

#define MPU_PROTENSET0_PROTREG25_Set (1UL)

Enable protection on write.

Definition at line 3181 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG26_Disabled

#define MPU_PROTENSET0_PROTREG26_Disabled (0UL)

Protection disabled.

Definition at line 3172 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG26_Enabled

#define MPU_PROTENSET0_PROTREG26_Enabled (1UL)

Protection enabled.

Definition at line 3173 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG26_Msk

#define MPU_PROTENSET0_PROTREG26_Msk (0x1UL << MPU_PROTENSET0_PROTREG26_Pos)

Bit mask of PROTREG26 field.

Definition at line 3171 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG26_Pos

#define MPU_PROTENSET0_PROTREG26_Pos (26UL)

Position of PROTREG26 field.

Definition at line 3170 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG26_Set

#define MPU_PROTENSET0_PROTREG26_Set (1UL)

Enable protection on write.

Definition at line 3174 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG27_Disabled

#define MPU_PROTENSET0_PROTREG27_Disabled (0UL)

Protection disabled.

Definition at line 3165 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG27_Enabled

#define MPU_PROTENSET0_PROTREG27_Enabled (1UL)

Protection enabled.

Definition at line 3166 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG27_Msk

#define MPU_PROTENSET0_PROTREG27_Msk (0x1UL << MPU_PROTENSET0_PROTREG27_Pos)

Bit mask of PROTREG27 field.

Definition at line 3164 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG27_Pos

#define MPU_PROTENSET0_PROTREG27_Pos (27UL)

Position of PROTREG27 field.

Definition at line 3163 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG27_Set

#define MPU_PROTENSET0_PROTREG27_Set (1UL)

Enable protection on write.

Definition at line 3167 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG28_Disabled

#define MPU_PROTENSET0_PROTREG28_Disabled (0UL)

Protection disabled.

Definition at line 3158 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG28_Enabled

#define MPU_PROTENSET0_PROTREG28_Enabled (1UL)

Protection enabled.

Definition at line 3159 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG28_Msk

#define MPU_PROTENSET0_PROTREG28_Msk (0x1UL << MPU_PROTENSET0_PROTREG28_Pos)

Bit mask of PROTREG28 field.

Definition at line 3157 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG28_Pos

#define MPU_PROTENSET0_PROTREG28_Pos (28UL)

Position of PROTREG28 field.

Definition at line 3156 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG28_Set

#define MPU_PROTENSET0_PROTREG28_Set (1UL)

Enable protection on write.

Definition at line 3160 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG29_Disabled

#define MPU_PROTENSET0_PROTREG29_Disabled (0UL)

Protection disabled.

Definition at line 3151 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG29_Enabled

#define MPU_PROTENSET0_PROTREG29_Enabled (1UL)

Protection enabled.

Definition at line 3152 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG29_Msk

#define MPU_PROTENSET0_PROTREG29_Msk (0x1UL << MPU_PROTENSET0_PROTREG29_Pos)

Bit mask of PROTREG29 field.

Definition at line 3150 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG29_Pos

#define MPU_PROTENSET0_PROTREG29_Pos (29UL)

Position of PROTREG29 field.

Definition at line 3149 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG29_Set

#define MPU_PROTENSET0_PROTREG29_Set (1UL)

Enable protection on write.

Definition at line 3153 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG2_Disabled

#define MPU_PROTENSET0_PROTREG2_Disabled (0UL)

Protection disabled.

Definition at line 3340 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG2_Enabled

#define MPU_PROTENSET0_PROTREG2_Enabled (1UL)

Protection enabled.

Definition at line 3341 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG2_Msk

#define MPU_PROTENSET0_PROTREG2_Msk (0x1UL << MPU_PROTENSET0_PROTREG2_Pos)

Bit mask of PROTREG2 field.

Definition at line 3339 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG2_Pos

#define MPU_PROTENSET0_PROTREG2_Pos (2UL)

Position of PROTREG2 field.

Definition at line 3338 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG2_Set

#define MPU_PROTENSET0_PROTREG2_Set (1UL)

Enable protection on write.

Definition at line 3342 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG30_Disabled

#define MPU_PROTENSET0_PROTREG30_Disabled (0UL)

Protection disabled.

Definition at line 3144 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG30_Enabled

#define MPU_PROTENSET0_PROTREG30_Enabled (1UL)

Protection enabled.

Definition at line 3145 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG30_Msk

#define MPU_PROTENSET0_PROTREG30_Msk (0x1UL << MPU_PROTENSET0_PROTREG30_Pos)

Bit mask of PROTREG30 field.

Definition at line 3143 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG30_Pos

#define MPU_PROTENSET0_PROTREG30_Pos (30UL)

Position of PROTREG30 field.

Definition at line 3142 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG30_Set

#define MPU_PROTENSET0_PROTREG30_Set (1UL)

Enable protection on write.

Definition at line 3146 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG31_Disabled

#define MPU_PROTENSET0_PROTREG31_Disabled (0UL)

Protection disabled.

Definition at line 3137 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG31_Enabled

#define MPU_PROTENSET0_PROTREG31_Enabled (1UL)

Protection enabled.

Definition at line 3138 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG31_Msk

#define MPU_PROTENSET0_PROTREG31_Msk (0x1UL << MPU_PROTENSET0_PROTREG31_Pos)

Bit mask of PROTREG31 field.

Definition at line 3136 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG31_Pos

#define MPU_PROTENSET0_PROTREG31_Pos (31UL)

Position of PROTREG31 field.

Definition at line 3135 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG31_Set

#define MPU_PROTENSET0_PROTREG31_Set (1UL)

Enable protection on write.

Definition at line 3139 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG3_Disabled

#define MPU_PROTENSET0_PROTREG3_Disabled (0UL)

Protection disabled.

Definition at line 3333 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG3_Enabled

#define MPU_PROTENSET0_PROTREG3_Enabled (1UL)

Protection enabled.

Definition at line 3334 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG3_Msk

#define MPU_PROTENSET0_PROTREG3_Msk (0x1UL << MPU_PROTENSET0_PROTREG3_Pos)

Bit mask of PROTREG3 field.

Definition at line 3332 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG3_Pos

#define MPU_PROTENSET0_PROTREG3_Pos (3UL)

Position of PROTREG3 field.

Definition at line 3331 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG3_Set

#define MPU_PROTENSET0_PROTREG3_Set (1UL)

Enable protection on write.

Definition at line 3335 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG4_Disabled

#define MPU_PROTENSET0_PROTREG4_Disabled (0UL)

Protection disabled.

Definition at line 3326 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG4_Enabled

#define MPU_PROTENSET0_PROTREG4_Enabled (1UL)

Protection enabled.

Definition at line 3327 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG4_Msk

#define MPU_PROTENSET0_PROTREG4_Msk (0x1UL << MPU_PROTENSET0_PROTREG4_Pos)

Bit mask of PROTREG4 field.

Definition at line 3325 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG4_Pos

#define MPU_PROTENSET0_PROTREG4_Pos (4UL)

Position of PROTREG4 field.

Definition at line 3324 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG4_Set

#define MPU_PROTENSET0_PROTREG4_Set (1UL)

Enable protection on write.

Definition at line 3328 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG5_Disabled

#define MPU_PROTENSET0_PROTREG5_Disabled (0UL)

Protection disabled.

Definition at line 3319 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG5_Enabled

#define MPU_PROTENSET0_PROTREG5_Enabled (1UL)

Protection enabled.

Definition at line 3320 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG5_Msk

#define MPU_PROTENSET0_PROTREG5_Msk (0x1UL << MPU_PROTENSET0_PROTREG5_Pos)

Bit mask of PROTREG5 field.

Definition at line 3318 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG5_Pos

#define MPU_PROTENSET0_PROTREG5_Pos (5UL)

Position of PROTREG5 field.

Definition at line 3317 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG5_Set

#define MPU_PROTENSET0_PROTREG5_Set (1UL)

Enable protection on write.

Definition at line 3321 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG6_Disabled

#define MPU_PROTENSET0_PROTREG6_Disabled (0UL)

Protection disabled.

Definition at line 3312 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG6_Enabled

#define MPU_PROTENSET0_PROTREG6_Enabled (1UL)

Protection enabled.

Definition at line 3313 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG6_Msk

#define MPU_PROTENSET0_PROTREG6_Msk (0x1UL << MPU_PROTENSET0_PROTREG6_Pos)

Bit mask of PROTREG6 field.

Definition at line 3311 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG6_Pos

#define MPU_PROTENSET0_PROTREG6_Pos (6UL)

Position of PROTREG6 field.

Definition at line 3310 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG6_Set

#define MPU_PROTENSET0_PROTREG6_Set (1UL)

Enable protection on write.

Definition at line 3314 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG7_Disabled

#define MPU_PROTENSET0_PROTREG7_Disabled (0UL)

Protection disabled.

Definition at line 3305 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG7_Enabled

#define MPU_PROTENSET0_PROTREG7_Enabled (1UL)

Protection enabled.

Definition at line 3306 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG7_Msk

#define MPU_PROTENSET0_PROTREG7_Msk (0x1UL << MPU_PROTENSET0_PROTREG7_Pos)

Bit mask of PROTREG7 field.

Definition at line 3304 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG7_Pos

#define MPU_PROTENSET0_PROTREG7_Pos (7UL)

Position of PROTREG7 field.

Definition at line 3303 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG7_Set

#define MPU_PROTENSET0_PROTREG7_Set (1UL)

Enable protection on write.

Definition at line 3307 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG8_Disabled

#define MPU_PROTENSET0_PROTREG8_Disabled (0UL)

Protection disabled.

Definition at line 3298 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG8_Enabled

#define MPU_PROTENSET0_PROTREG8_Enabled (1UL)

Protection enabled.

Definition at line 3299 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG8_Msk

#define MPU_PROTENSET0_PROTREG8_Msk (0x1UL << MPU_PROTENSET0_PROTREG8_Pos)

Bit mask of PROTREG8 field.

Definition at line 3297 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG8_Pos

#define MPU_PROTENSET0_PROTREG8_Pos (8UL)

Position of PROTREG8 field.

Definition at line 3296 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG8_Set

#define MPU_PROTENSET0_PROTREG8_Set (1UL)

Enable protection on write.

Definition at line 3300 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG9_Disabled

#define MPU_PROTENSET0_PROTREG9_Disabled (0UL)

Protection disabled.

Definition at line 3291 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG9_Enabled

#define MPU_PROTENSET0_PROTREG9_Enabled (1UL)

Protection enabled.

Definition at line 3292 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG9_Msk

#define MPU_PROTENSET0_PROTREG9_Msk (0x1UL << MPU_PROTENSET0_PROTREG9_Pos)

Bit mask of PROTREG9 field.

Definition at line 3290 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG9_Pos

#define MPU_PROTENSET0_PROTREG9_Pos (9UL)

Position of PROTREG9 field.

Definition at line 3289 of file nrf51_bitfields.h.

◆ MPU_PROTENSET0_PROTREG9_Set

#define MPU_PROTENSET0_PROTREG9_Set (1UL)

Enable protection on write.

Definition at line 3293 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG32_Disabled

#define MPU_PROTENSET1_PROTREG32_Disabled (0UL)

Protection disabled.

Definition at line 3581 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG32_Enabled

#define MPU_PROTENSET1_PROTREG32_Enabled (1UL)

Protection enabled.

Definition at line 3582 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG32_Msk

#define MPU_PROTENSET1_PROTREG32_Msk (0x1UL << MPU_PROTENSET1_PROTREG32_Pos)

Bit mask of PROTREG32 field.

Definition at line 3580 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG32_Pos

#define MPU_PROTENSET1_PROTREG32_Pos (0UL)

Position of PROTREG32 field.

Definition at line 3579 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG32_Set

#define MPU_PROTENSET1_PROTREG32_Set (1UL)

Enable protection on write.

Definition at line 3583 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG33_Disabled

#define MPU_PROTENSET1_PROTREG33_Disabled (0UL)

Protection disabled.

Definition at line 3574 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG33_Enabled

#define MPU_PROTENSET1_PROTREG33_Enabled (1UL)

Protection enabled.

Definition at line 3575 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG33_Msk

#define MPU_PROTENSET1_PROTREG33_Msk (0x1UL << MPU_PROTENSET1_PROTREG33_Pos)

Bit mask of PROTREG33 field.

Definition at line 3573 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG33_Pos

#define MPU_PROTENSET1_PROTREG33_Pos (1UL)

Position of PROTREG33 field.

Definition at line 3572 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG33_Set

#define MPU_PROTENSET1_PROTREG33_Set (1UL)

Enable protection on write.

Definition at line 3576 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG34_Disabled

#define MPU_PROTENSET1_PROTREG34_Disabled (0UL)

Protection disabled.

Definition at line 3567 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG34_Enabled

#define MPU_PROTENSET1_PROTREG34_Enabled (1UL)

Protection enabled.

Definition at line 3568 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG34_Msk

#define MPU_PROTENSET1_PROTREG34_Msk (0x1UL << MPU_PROTENSET1_PROTREG34_Pos)

Bit mask of PROTREG34 field.

Definition at line 3566 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG34_Pos

#define MPU_PROTENSET1_PROTREG34_Pos (2UL)

Position of PROTREG34 field.

Definition at line 3565 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG34_Set

#define MPU_PROTENSET1_PROTREG34_Set (1UL)

Enable protection on write.

Definition at line 3569 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG35_Disabled

#define MPU_PROTENSET1_PROTREG35_Disabled (0UL)

Protection disabled.

Definition at line 3560 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG35_Enabled

#define MPU_PROTENSET1_PROTREG35_Enabled (1UL)

Protection enabled.

Definition at line 3561 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG35_Msk

#define MPU_PROTENSET1_PROTREG35_Msk (0x1UL << MPU_PROTENSET1_PROTREG35_Pos)

Bit mask of PROTREG35 field.

Definition at line 3559 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG35_Pos

#define MPU_PROTENSET1_PROTREG35_Pos (3UL)

Position of PROTREG35 field.

Definition at line 3558 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG35_Set

#define MPU_PROTENSET1_PROTREG35_Set (1UL)

Enable protection on write.

Definition at line 3562 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG36_Disabled

#define MPU_PROTENSET1_PROTREG36_Disabled (0UL)

Protection disabled.

Definition at line 3553 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG36_Enabled

#define MPU_PROTENSET1_PROTREG36_Enabled (1UL)

Protection enabled.

Definition at line 3554 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG36_Msk

#define MPU_PROTENSET1_PROTREG36_Msk (0x1UL << MPU_PROTENSET1_PROTREG36_Pos)

Bit mask of PROTREG36 field.

Definition at line 3552 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG36_Pos

#define MPU_PROTENSET1_PROTREG36_Pos (4UL)

Position of PROTREG36 field.

Definition at line 3551 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG36_Set

#define MPU_PROTENSET1_PROTREG36_Set (1UL)

Enable protection on write.

Definition at line 3555 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG37_Disabled

#define MPU_PROTENSET1_PROTREG37_Disabled (0UL)

Protection disabled.

Definition at line 3546 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG37_Enabled

#define MPU_PROTENSET1_PROTREG37_Enabled (1UL)

Protection enabled.

Definition at line 3547 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG37_Msk

#define MPU_PROTENSET1_PROTREG37_Msk (0x1UL << MPU_PROTENSET1_PROTREG37_Pos)

Bit mask of PROTREG37 field.

Definition at line 3545 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG37_Pos

#define MPU_PROTENSET1_PROTREG37_Pos (5UL)

Position of PROTREG37 field.

Definition at line 3544 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG37_Set

#define MPU_PROTENSET1_PROTREG37_Set (1UL)

Enable protection on write.

Definition at line 3548 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG38_Disabled

#define MPU_PROTENSET1_PROTREG38_Disabled (0UL)

Protection disabled.

Definition at line 3539 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG38_Enabled

#define MPU_PROTENSET1_PROTREG38_Enabled (1UL)

Protection enabled.

Definition at line 3540 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG38_Msk

#define MPU_PROTENSET1_PROTREG38_Msk (0x1UL << MPU_PROTENSET1_PROTREG38_Pos)

Bit mask of PROTREG38 field.

Definition at line 3538 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG38_Pos

#define MPU_PROTENSET1_PROTREG38_Pos (6UL)

Position of PROTREG38 field.

Definition at line 3537 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG38_Set

#define MPU_PROTENSET1_PROTREG38_Set (1UL)

Enable protection on write.

Definition at line 3541 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG39_Disabled

#define MPU_PROTENSET1_PROTREG39_Disabled (0UL)

Protection disabled.

Definition at line 3532 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG39_Enabled

#define MPU_PROTENSET1_PROTREG39_Enabled (1UL)

Protection enabled.

Definition at line 3533 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG39_Msk

#define MPU_PROTENSET1_PROTREG39_Msk (0x1UL << MPU_PROTENSET1_PROTREG39_Pos)

Bit mask of PROTREG39 field.

Definition at line 3531 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG39_Pos

#define MPU_PROTENSET1_PROTREG39_Pos (7UL)

Position of PROTREG39 field.

Definition at line 3530 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG39_Set

#define MPU_PROTENSET1_PROTREG39_Set (1UL)

Enable protection on write.

Definition at line 3534 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG40_Disabled

#define MPU_PROTENSET1_PROTREG40_Disabled (0UL)

Protection disabled.

Definition at line 3525 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG40_Enabled

#define MPU_PROTENSET1_PROTREG40_Enabled (1UL)

Protection enabled.

Definition at line 3526 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG40_Msk

#define MPU_PROTENSET1_PROTREG40_Msk (0x1UL << MPU_PROTENSET1_PROTREG40_Pos)

Bit mask of PROTREG40 field.

Definition at line 3524 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG40_Pos

#define MPU_PROTENSET1_PROTREG40_Pos (8UL)

Position of PROTREG40 field.

Definition at line 3523 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG40_Set

#define MPU_PROTENSET1_PROTREG40_Set (1UL)

Enable protection on write.

Definition at line 3527 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG41_Disabled

#define MPU_PROTENSET1_PROTREG41_Disabled (0UL)

Protection disabled.

Definition at line 3518 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG41_Enabled

#define MPU_PROTENSET1_PROTREG41_Enabled (1UL)

Protection enabled.

Definition at line 3519 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG41_Msk

#define MPU_PROTENSET1_PROTREG41_Msk (0x1UL << MPU_PROTENSET1_PROTREG41_Pos)

Bit mask of PROTREG41 field.

Definition at line 3517 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG41_Pos

#define MPU_PROTENSET1_PROTREG41_Pos (9UL)

Position of PROTREG41 field.

Definition at line 3516 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG41_Set

#define MPU_PROTENSET1_PROTREG41_Set (1UL)

Enable protection on write.

Definition at line 3520 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG42_Disabled

#define MPU_PROTENSET1_PROTREG42_Disabled (0UL)

Protection disabled.

Definition at line 3511 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG42_Enabled

#define MPU_PROTENSET1_PROTREG42_Enabled (1UL)

Protection enabled.

Definition at line 3512 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG42_Msk

#define MPU_PROTENSET1_PROTREG42_Msk (0x1UL << MPU_PROTENSET1_PROTREG42_Pos)

Bit mask of PROTREG42 field.

Definition at line 3510 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG42_Pos

#define MPU_PROTENSET1_PROTREG42_Pos (10UL)

Position of PROTREG42 field.

Definition at line 3509 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG42_Set

#define MPU_PROTENSET1_PROTREG42_Set (1UL)

Enable protection on write.

Definition at line 3513 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG43_Disabled

#define MPU_PROTENSET1_PROTREG43_Disabled (0UL)

Protection disabled.

Definition at line 3504 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG43_Enabled

#define MPU_PROTENSET1_PROTREG43_Enabled (1UL)

Protection enabled.

Definition at line 3505 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG43_Msk

#define MPU_PROTENSET1_PROTREG43_Msk (0x1UL << MPU_PROTENSET1_PROTREG43_Pos)

Bit mask of PROTREG43 field.

Definition at line 3503 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG43_Pos

#define MPU_PROTENSET1_PROTREG43_Pos (11UL)

Position of PROTREG43 field.

Definition at line 3502 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG43_Set

#define MPU_PROTENSET1_PROTREG43_Set (1UL)

Enable protection on write.

Definition at line 3506 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG44_Disabled

#define MPU_PROTENSET1_PROTREG44_Disabled (0UL)

Protection disabled.

Definition at line 3497 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG44_Enabled

#define MPU_PROTENSET1_PROTREG44_Enabled (1UL)

Protection enabled.

Definition at line 3498 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG44_Msk

#define MPU_PROTENSET1_PROTREG44_Msk (0x1UL << MPU_PROTENSET1_PROTREG44_Pos)

Bit mask of PROTREG44 field.

Definition at line 3496 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG44_Pos

#define MPU_PROTENSET1_PROTREG44_Pos (12UL)

Position of PROTREG44 field.

Definition at line 3495 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG44_Set

#define MPU_PROTENSET1_PROTREG44_Set (1UL)

Enable protection on write.

Definition at line 3499 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG45_Disabled

#define MPU_PROTENSET1_PROTREG45_Disabled (0UL)

Protection disabled.

Definition at line 3490 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG45_Enabled

#define MPU_PROTENSET1_PROTREG45_Enabled (1UL)

Protection enabled.

Definition at line 3491 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG45_Msk

#define MPU_PROTENSET1_PROTREG45_Msk (0x1UL << MPU_PROTENSET1_PROTREG45_Pos)

Bit mask of PROTREG45 field.

Definition at line 3489 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG45_Pos

#define MPU_PROTENSET1_PROTREG45_Pos (13UL)

Position of PROTREG45 field.

Definition at line 3488 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG45_Set

#define MPU_PROTENSET1_PROTREG45_Set (1UL)

Enable protection on write.

Definition at line 3492 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG46_Disabled

#define MPU_PROTENSET1_PROTREG46_Disabled (0UL)

Protection disabled.

Definition at line 3483 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG46_Enabled

#define MPU_PROTENSET1_PROTREG46_Enabled (1UL)

Protection enabled.

Definition at line 3484 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG46_Msk

#define MPU_PROTENSET1_PROTREG46_Msk (0x1UL << MPU_PROTENSET1_PROTREG46_Pos)

Bit mask of PROTREG46 field.

Definition at line 3482 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG46_Pos

#define MPU_PROTENSET1_PROTREG46_Pos (14UL)

Position of PROTREG46 field.

Definition at line 3481 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG46_Set

#define MPU_PROTENSET1_PROTREG46_Set (1UL)

Enable protection on write.

Definition at line 3485 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG47_Disabled

#define MPU_PROTENSET1_PROTREG47_Disabled (0UL)

Protection disabled.

Definition at line 3476 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG47_Enabled

#define MPU_PROTENSET1_PROTREG47_Enabled (1UL)

Protection enabled.

Definition at line 3477 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG47_Msk

#define MPU_PROTENSET1_PROTREG47_Msk (0x1UL << MPU_PROTENSET1_PROTREG47_Pos)

Bit mask of PROTREG47 field.

Definition at line 3475 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG47_Pos

#define MPU_PROTENSET1_PROTREG47_Pos (15UL)

Position of PROTREG47 field.

Definition at line 3474 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG47_Set

#define MPU_PROTENSET1_PROTREG47_Set (1UL)

Enable protection on write.

Definition at line 3478 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG48_Disabled

#define MPU_PROTENSET1_PROTREG48_Disabled (0UL)

Protection disabled.

Definition at line 3469 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG48_Enabled

#define MPU_PROTENSET1_PROTREG48_Enabled (1UL)

Protection enabled.

Definition at line 3470 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG48_Msk

#define MPU_PROTENSET1_PROTREG48_Msk (0x1UL << MPU_PROTENSET1_PROTREG48_Pos)

Bit mask of PROTREG48 field.

Definition at line 3468 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG48_Pos

#define MPU_PROTENSET1_PROTREG48_Pos (16UL)

Position of PROTREG48 field.

Definition at line 3467 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG48_Set

#define MPU_PROTENSET1_PROTREG48_Set (1UL)

Enable protection on write.

Definition at line 3471 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG49_Disabled

#define MPU_PROTENSET1_PROTREG49_Disabled (0UL)

Protection disabled.

Definition at line 3462 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG49_Enabled

#define MPU_PROTENSET1_PROTREG49_Enabled (1UL)

Protection enabled.

Definition at line 3463 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG49_Msk

#define MPU_PROTENSET1_PROTREG49_Msk (0x1UL << MPU_PROTENSET1_PROTREG49_Pos)

Bit mask of PROTREG49 field.

Definition at line 3461 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG49_Pos

#define MPU_PROTENSET1_PROTREG49_Pos (17UL)

Position of PROTREG49 field.

Definition at line 3460 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG49_Set

#define MPU_PROTENSET1_PROTREG49_Set (1UL)

Enable protection on write.

Definition at line 3464 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG50_Disabled

#define MPU_PROTENSET1_PROTREG50_Disabled (0UL)

Protection disabled.

Definition at line 3455 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG50_Enabled

#define MPU_PROTENSET1_PROTREG50_Enabled (1UL)

Protection enabled.

Definition at line 3456 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG50_Msk

#define MPU_PROTENSET1_PROTREG50_Msk (0x1UL << MPU_PROTENSET1_PROTREG50_Pos)

Bit mask of PROTREG50 field.

Definition at line 3454 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG50_Pos

#define MPU_PROTENSET1_PROTREG50_Pos (18UL)

Position of PROTREG50 field.

Definition at line 3453 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG50_Set

#define MPU_PROTENSET1_PROTREG50_Set (1UL)

Enable protection on write.

Definition at line 3457 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG51_Disabled

#define MPU_PROTENSET1_PROTREG51_Disabled (0UL)

Protection disabled.

Definition at line 3448 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG51_Enabled

#define MPU_PROTENSET1_PROTREG51_Enabled (1UL)

Protection enabled.

Definition at line 3449 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG51_Msk

#define MPU_PROTENSET1_PROTREG51_Msk (0x1UL << MPU_PROTENSET1_PROTREG51_Pos)

Bit mask of PROTREG51 field.

Definition at line 3447 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG51_Pos

#define MPU_PROTENSET1_PROTREG51_Pos (19UL)

Position of PROTREG51 field.

Definition at line 3446 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG51_Set

#define MPU_PROTENSET1_PROTREG51_Set (1UL)

Enable protection on write.

Definition at line 3450 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG52_Disabled

#define MPU_PROTENSET1_PROTREG52_Disabled (0UL)

Protection disabled.

Definition at line 3441 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG52_Enabled

#define MPU_PROTENSET1_PROTREG52_Enabled (1UL)

Protection enabled.

Definition at line 3442 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG52_Msk

#define MPU_PROTENSET1_PROTREG52_Msk (0x1UL << MPU_PROTENSET1_PROTREG52_Pos)

Bit mask of PROTREG52 field.

Definition at line 3440 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG52_Pos

#define MPU_PROTENSET1_PROTREG52_Pos (20UL)

Position of PROTREG52 field.

Definition at line 3439 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG52_Set

#define MPU_PROTENSET1_PROTREG52_Set (1UL)

Enable protection on write.

Definition at line 3443 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG53_Disabled

#define MPU_PROTENSET1_PROTREG53_Disabled (0UL)

Protection disabled.

Definition at line 3434 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG53_Enabled

#define MPU_PROTENSET1_PROTREG53_Enabled (1UL)

Protection enabled.

Definition at line 3435 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG53_Msk

#define MPU_PROTENSET1_PROTREG53_Msk (0x1UL << MPU_PROTENSET1_PROTREG53_Pos)

Bit mask of PROTREG53 field.

Definition at line 3433 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG53_Pos

#define MPU_PROTENSET1_PROTREG53_Pos (21UL)

Position of PROTREG53 field.

Definition at line 3432 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG53_Set

#define MPU_PROTENSET1_PROTREG53_Set (1UL)

Enable protection on write.

Definition at line 3436 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG54_Disabled

#define MPU_PROTENSET1_PROTREG54_Disabled (0UL)

Protection disabled.

Definition at line 3427 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG54_Enabled

#define MPU_PROTENSET1_PROTREG54_Enabled (1UL)

Protection enabled.

Definition at line 3428 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG54_Msk

#define MPU_PROTENSET1_PROTREG54_Msk (0x1UL << MPU_PROTENSET1_PROTREG54_Pos)

Bit mask of PROTREG54 field.

Definition at line 3426 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG54_Pos

#define MPU_PROTENSET1_PROTREG54_Pos (22UL)

Position of PROTREG54 field.

Definition at line 3425 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG54_Set

#define MPU_PROTENSET1_PROTREG54_Set (1UL)

Enable protection on write.

Definition at line 3429 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG55_Disabled

#define MPU_PROTENSET1_PROTREG55_Disabled (0UL)

Protection disabled.

Definition at line 3420 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG55_Enabled

#define MPU_PROTENSET1_PROTREG55_Enabled (1UL)

Protection enabled.

Definition at line 3421 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG55_Msk

#define MPU_PROTENSET1_PROTREG55_Msk (0x1UL << MPU_PROTENSET1_PROTREG55_Pos)

Bit mask of PROTREG55 field.

Definition at line 3419 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG55_Pos

#define MPU_PROTENSET1_PROTREG55_Pos (23UL)

Position of PROTREG55 field.

Definition at line 3418 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG55_Set

#define MPU_PROTENSET1_PROTREG55_Set (1UL)

Enable protection on write.

Definition at line 3422 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG56_Disabled

#define MPU_PROTENSET1_PROTREG56_Disabled (0UL)

Protection disabled.

Definition at line 3413 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG56_Enabled

#define MPU_PROTENSET1_PROTREG56_Enabled (1UL)

Protection enabled.

Definition at line 3414 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG56_Msk

#define MPU_PROTENSET1_PROTREG56_Msk (0x1UL << MPU_PROTENSET1_PROTREG56_Pos)

Bit mask of PROTREG56 field.

Definition at line 3412 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG56_Pos

#define MPU_PROTENSET1_PROTREG56_Pos (24UL)

Position of PROTREG56 field.

Definition at line 3411 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG56_Set

#define MPU_PROTENSET1_PROTREG56_Set (1UL)

Enable protection on write.

Definition at line 3415 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG57_Disabled

#define MPU_PROTENSET1_PROTREG57_Disabled (0UL)

Protection disabled.

Definition at line 3406 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG57_Enabled

#define MPU_PROTENSET1_PROTREG57_Enabled (1UL)

Protection enabled.

Definition at line 3407 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG57_Msk

#define MPU_PROTENSET1_PROTREG57_Msk (0x1UL << MPU_PROTENSET1_PROTREG57_Pos)

Bit mask of PROTREG57 field.

Definition at line 3405 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG57_Pos

#define MPU_PROTENSET1_PROTREG57_Pos (25UL)

Position of PROTREG57 field.

Definition at line 3404 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG57_Set

#define MPU_PROTENSET1_PROTREG57_Set (1UL)

Enable protection on write.

Definition at line 3408 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG58_Disabled

#define MPU_PROTENSET1_PROTREG58_Disabled (0UL)

Protection disabled.

Definition at line 3399 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG58_Enabled

#define MPU_PROTENSET1_PROTREG58_Enabled (1UL)

Protection enabled.

Definition at line 3400 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG58_Msk

#define MPU_PROTENSET1_PROTREG58_Msk (0x1UL << MPU_PROTENSET1_PROTREG58_Pos)

Bit mask of PROTREG58 field.

Definition at line 3398 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG58_Pos

#define MPU_PROTENSET1_PROTREG58_Pos (26UL)

Position of PROTREG58 field.

Definition at line 3397 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG58_Set

#define MPU_PROTENSET1_PROTREG58_Set (1UL)

Enable protection on write.

Definition at line 3401 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG59_Disabled

#define MPU_PROTENSET1_PROTREG59_Disabled (0UL)

Protection disabled.

Definition at line 3392 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG59_Enabled

#define MPU_PROTENSET1_PROTREG59_Enabled (1UL)

Protection enabled.

Definition at line 3393 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG59_Msk

#define MPU_PROTENSET1_PROTREG59_Msk (0x1UL << MPU_PROTENSET1_PROTREG59_Pos)

Bit mask of PROTREG59 field.

Definition at line 3391 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG59_Pos

#define MPU_PROTENSET1_PROTREG59_Pos (27UL)

Position of PROTREG59 field.

Definition at line 3390 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG59_Set

#define MPU_PROTENSET1_PROTREG59_Set (1UL)

Enable protection on write.

Definition at line 3394 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG60_Disabled

#define MPU_PROTENSET1_PROTREG60_Disabled (0UL)

Protection disabled.

Definition at line 3385 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG60_Enabled

#define MPU_PROTENSET1_PROTREG60_Enabled (1UL)

Protection enabled.

Definition at line 3386 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG60_Msk

#define MPU_PROTENSET1_PROTREG60_Msk (0x1UL << MPU_PROTENSET1_PROTREG60_Pos)

Bit mask of PROTREG60 field.

Definition at line 3384 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG60_Pos

#define MPU_PROTENSET1_PROTREG60_Pos (28UL)

Position of PROTREG60 field.

Definition at line 3383 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG60_Set

#define MPU_PROTENSET1_PROTREG60_Set (1UL)

Enable protection on write.

Definition at line 3387 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG61_Disabled

#define MPU_PROTENSET1_PROTREG61_Disabled (0UL)

Protection disabled.

Definition at line 3378 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG61_Enabled

#define MPU_PROTENSET1_PROTREG61_Enabled (1UL)

Protection enabled.

Definition at line 3379 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG61_Msk

#define MPU_PROTENSET1_PROTREG61_Msk (0x1UL << MPU_PROTENSET1_PROTREG61_Pos)

Bit mask of PROTREG61 field.

Definition at line 3377 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG61_Pos

#define MPU_PROTENSET1_PROTREG61_Pos (29UL)

Position of PROTREG61 field.

Definition at line 3376 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG61_Set

#define MPU_PROTENSET1_PROTREG61_Set (1UL)

Enable protection on write.

Definition at line 3380 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG62_Disabled

#define MPU_PROTENSET1_PROTREG62_Disabled (0UL)

Protection disabled.

Definition at line 3371 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG62_Enabled

#define MPU_PROTENSET1_PROTREG62_Enabled (1UL)

Protection enabled.

Definition at line 3372 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG62_Msk

#define MPU_PROTENSET1_PROTREG62_Msk (0x1UL << MPU_PROTENSET1_PROTREG62_Pos)

Bit mask of PROTREG62 field.

Definition at line 3370 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG62_Pos

#define MPU_PROTENSET1_PROTREG62_Pos (30UL)

Position of PROTREG62 field.

Definition at line 3369 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG62_Set

#define MPU_PROTENSET1_PROTREG62_Set (1UL)

Enable protection on write.

Definition at line 3373 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG63_Disabled

#define MPU_PROTENSET1_PROTREG63_Disabled (0UL)

Protection disabled.

Definition at line 3364 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG63_Enabled

#define MPU_PROTENSET1_PROTREG63_Enabled (1UL)

Protection enabled.

Definition at line 3365 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG63_Msk

#define MPU_PROTENSET1_PROTREG63_Msk (0x1UL << MPU_PROTENSET1_PROTREG63_Pos)

Bit mask of PROTREG63 field.

Definition at line 3363 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG63_Pos

#define MPU_PROTENSET1_PROTREG63_Pos (31UL)

Position of PROTREG63 field.

Definition at line 3362 of file nrf51_bitfields.h.

◆ MPU_PROTENSET1_PROTREG63_Set

#define MPU_PROTENSET1_PROTREG63_Set (1UL)

Enable protection on write.

Definition at line 3366 of file nrf51_bitfields.h.

◆ NVMC_CONFIG_WEN_Een

#define NVMC_CONFIG_WEN_Een (0x02UL)

Erase enabled.

Definition at line 3623 of file nrf51_bitfields.h.

◆ NVMC_CONFIG_WEN_Msk

#define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos)

Bit mask of WEN field.

Definition at line 3620 of file nrf51_bitfields.h.

◆ NVMC_CONFIG_WEN_Pos

#define NVMC_CONFIG_WEN_Pos (0UL)

Position of WEN field.

Definition at line 3619 of file nrf51_bitfields.h.

◆ NVMC_CONFIG_WEN_Ren

#define NVMC_CONFIG_WEN_Ren (0x00UL)

Read only access.

Definition at line 3621 of file nrf51_bitfields.h.

◆ NVMC_CONFIG_WEN_Wen

#define NVMC_CONFIG_WEN_Wen (0x01UL)

Write enabled.

Definition at line 3622 of file nrf51_bitfields.h.

◆ NVMC_ERASEALL_ERASEALL_Erase

#define NVMC_ERASEALL_ERASEALL_Erase (1UL)

Start chip erase.

Definition at line 3632 of file nrf51_bitfields.h.

◆ NVMC_ERASEALL_ERASEALL_Msk

#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos)

Bit mask of ERASEALL field.

Definition at line 3630 of file nrf51_bitfields.h.

◆ NVMC_ERASEALL_ERASEALL_NoOperation

#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL)

No operation.

Definition at line 3631 of file nrf51_bitfields.h.

◆ NVMC_ERASEALL_ERASEALL_Pos

#define NVMC_ERASEALL_ERASEALL_Pos (0UL)

Position of ERASEALL field.

Definition at line 3629 of file nrf51_bitfields.h.

◆ NVMC_ERASEUICR_ERASEUICR_Erase

#define NVMC_ERASEUICR_ERASEUICR_Erase (1UL)

Start UICR erase.

Definition at line 3641 of file nrf51_bitfields.h.

◆ NVMC_ERASEUICR_ERASEUICR_Msk

#define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos)

Bit mask of ERASEUICR field.

Definition at line 3639 of file nrf51_bitfields.h.

◆ NVMC_ERASEUICR_ERASEUICR_NoOperation

#define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL)

No operation.

Definition at line 3640 of file nrf51_bitfields.h.

◆ NVMC_ERASEUICR_ERASEUICR_Pos

#define NVMC_ERASEUICR_ERASEUICR_Pos (0UL)

Position of ERASEUICR field.

Definition at line 3638 of file nrf51_bitfields.h.

◆ NVMC_READY_READY_Busy

#define NVMC_READY_READY_Busy (0UL)

NVMC is busy (on-going write or erase operation).

Definition at line 3612 of file nrf51_bitfields.h.

◆ NVMC_READY_READY_Msk

#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos)

Bit mask of READY field.

Definition at line 3611 of file nrf51_bitfields.h.

◆ NVMC_READY_READY_Pos

#define NVMC_READY_READY_Pos (0UL)

Position of READY field.

Definition at line 3610 of file nrf51_bitfields.h.

◆ NVMC_READY_READY_Ready

#define NVMC_READY_READY_Ready (1UL)

NVMC is ready.

Definition at line 3613 of file nrf51_bitfields.h.

◆ POWER_DCDCEN_DCDCEN_Disabled

#define POWER_DCDCEN_DCDCEN_Disabled (0UL)

DCDC converter disabled.

Definition at line 3840 of file nrf51_bitfields.h.

◆ POWER_DCDCEN_DCDCEN_Enabled

#define POWER_DCDCEN_DCDCEN_Enabled (1UL)

DCDC converter enabled.

Definition at line 3841 of file nrf51_bitfields.h.

◆ POWER_DCDCEN_DCDCEN_Msk

#define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos)

Bit mask of DCDCEN field.

Definition at line 3839 of file nrf51_bitfields.h.

◆ POWER_DCDCEN_DCDCEN_Pos

#define POWER_DCDCEN_DCDCEN_Pos (0UL)

Position of DCDCEN field.

Definition at line 3838 of file nrf51_bitfields.h.

◆ POWER_DCDCFORCE_FORCEOFF_Force

#define POWER_DCDCFORCE_FORCEOFF_Force (1UL)

Force.

Definition at line 3856 of file nrf51_bitfields.h.

◆ POWER_DCDCFORCE_FORCEOFF_Msk

#define POWER_DCDCFORCE_FORCEOFF_Msk (0x1UL << POWER_DCDCFORCE_FORCEOFF_Pos)

Bit mask of FORCEOFF field.

Definition at line 3854 of file nrf51_bitfields.h.

◆ POWER_DCDCFORCE_FORCEOFF_NoForce

#define POWER_DCDCFORCE_FORCEOFF_NoForce (0UL)

No force.

Definition at line 3855 of file nrf51_bitfields.h.

◆ POWER_DCDCFORCE_FORCEOFF_Pos

#define POWER_DCDCFORCE_FORCEOFF_Pos (0UL)

Position of FORCEOFF field.

Definition at line 3853 of file nrf51_bitfields.h.

◆ POWER_DCDCFORCE_FORCEON_Force

#define POWER_DCDCFORCE_FORCEON_Force (1UL)

Force.

Definition at line 3850 of file nrf51_bitfields.h.

◆ POWER_DCDCFORCE_FORCEON_Msk

#define POWER_DCDCFORCE_FORCEON_Msk (0x1UL << POWER_DCDCFORCE_FORCEON_Pos)

Bit mask of FORCEON field.

Definition at line 3848 of file nrf51_bitfields.h.

◆ POWER_DCDCFORCE_FORCEON_NoForce

#define POWER_DCDCFORCE_FORCEON_NoForce (0UL)

No force.

Definition at line 3849 of file nrf51_bitfields.h.

◆ POWER_DCDCFORCE_FORCEON_Pos

#define POWER_DCDCFORCE_FORCEON_Pos (1UL)

Position of FORCEON field.

Definition at line 3847 of file nrf51_bitfields.h.

◆ POWER_GPREGRET_GPREGRET_Msk

#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos)

Bit mask of GPREGRET field.

Definition at line 3769 of file nrf51_bitfields.h.

◆ POWER_GPREGRET_GPREGRET_Pos

#define POWER_GPREGRET_GPREGRET_Pos (0UL)

Position of GPREGRET field.

Definition at line 3768 of file nrf51_bitfields.h.

◆ POWER_INTENCLR_POFWARN_Clear

#define POWER_INTENCLR_POFWARN_Clear (1UL)

Disable interrupt on write.

Definition at line 3665 of file nrf51_bitfields.h.

◆ POWER_INTENCLR_POFWARN_Disabled

#define POWER_INTENCLR_POFWARN_Disabled (0UL)

Interrupt disabled.

Definition at line 3663 of file nrf51_bitfields.h.

◆ POWER_INTENCLR_POFWARN_Enabled

#define POWER_INTENCLR_POFWARN_Enabled (1UL)

Interrupt enabled.

Definition at line 3664 of file nrf51_bitfields.h.

◆ POWER_INTENCLR_POFWARN_Msk

#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos)

Bit mask of POFWARN field.

Definition at line 3662 of file nrf51_bitfields.h.

◆ POWER_INTENCLR_POFWARN_Pos

#define POWER_INTENCLR_POFWARN_Pos (2UL)

Position of POFWARN field.

Definition at line 3661 of file nrf51_bitfields.h.

◆ POWER_INTENSET_POFWARN_Disabled

#define POWER_INTENSET_POFWARN_Disabled (0UL)

Interrupt disabled.

Definition at line 3653 of file nrf51_bitfields.h.

◆ POWER_INTENSET_POFWARN_Enabled

#define POWER_INTENSET_POFWARN_Enabled (1UL)

Interrupt enabled.

Definition at line 3654 of file nrf51_bitfields.h.

◆ POWER_INTENSET_POFWARN_Msk

#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos)

Bit mask of POFWARN field.

Definition at line 3652 of file nrf51_bitfields.h.

◆ POWER_INTENSET_POFWARN_Pos

#define POWER_INTENSET_POFWARN_Pos (2UL)

Position of POFWARN field.

Definition at line 3651 of file nrf51_bitfields.h.

◆ POWER_INTENSET_POFWARN_Set

#define POWER_INTENSET_POFWARN_Set (1UL)

Enable interrupt on write.

Definition at line 3655 of file nrf51_bitfields.h.

◆ POWER_POFCON_POF_Disabled

#define POWER_POFCON_POF_Disabled (0UL)

Disabled.

Definition at line 3761 of file nrf51_bitfields.h.

◆ POWER_POFCON_POF_Enabled

#define POWER_POFCON_POF_Enabled (1UL)

Enabled.

Definition at line 3762 of file nrf51_bitfields.h.

◆ POWER_POFCON_POF_Msk

#define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos)

Bit mask of POF field.

Definition at line 3760 of file nrf51_bitfields.h.

◆ POWER_POFCON_POF_Pos

#define POWER_POFCON_POF_Pos (0UL)

Position of POF field.

Definition at line 3759 of file nrf51_bitfields.h.

◆ POWER_POFCON_THRESHOLD_Msk

#define POWER_POFCON_THRESHOLD_Msk (0x3UL << POWER_POFCON_THRESHOLD_Pos)

Bit mask of THRESHOLD field.

Definition at line 3752 of file nrf51_bitfields.h.

◆ POWER_POFCON_THRESHOLD_Pos

#define POWER_POFCON_THRESHOLD_Pos (1UL)

Position of THRESHOLD field.

Definition at line 3751 of file nrf51_bitfields.h.

◆ POWER_POFCON_THRESHOLD_V21

#define POWER_POFCON_THRESHOLD_V21 (0x00UL)

Set threshold to 2.1Volts.

Definition at line 3753 of file nrf51_bitfields.h.

◆ POWER_POFCON_THRESHOLD_V23

#define POWER_POFCON_THRESHOLD_V23 (0x01UL)

Set threshold to 2.3Volts.

Definition at line 3754 of file nrf51_bitfields.h.

◆ POWER_POFCON_THRESHOLD_V25

#define POWER_POFCON_THRESHOLD_V25 (0x02UL)

Set threshold to 2.5Volts.

Definition at line 3755 of file nrf51_bitfields.h.

◆ POWER_POFCON_THRESHOLD_V27

#define POWER_POFCON_THRESHOLD_V27 (0x03UL)

Set threshold to 2.7Volts.

Definition at line 3756 of file nrf51_bitfields.h.

◆ POWER_RAMON_OFFRAM0_Msk

#define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos)

Bit mask of OFFRAM0 field.

Definition at line 3782 of file nrf51_bitfields.h.

◆ POWER_RAMON_OFFRAM0_Pos

#define POWER_RAMON_OFFRAM0_Pos (16UL)

Position of OFFRAM0 field.

Definition at line 3781 of file nrf51_bitfields.h.

◆ POWER_RAMON_OFFRAM0_RAM0Off

#define POWER_RAMON_OFFRAM0_RAM0Off (0UL)

RAM block 0 OFF in OFF mode.

Definition at line 3783 of file nrf51_bitfields.h.

◆ POWER_RAMON_OFFRAM0_RAM0On

#define POWER_RAMON_OFFRAM0_RAM0On (1UL)

RAM block 0 ON in OFF mode.

Definition at line 3784 of file nrf51_bitfields.h.

◆ POWER_RAMON_OFFRAM1_Msk

#define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos)

Bit mask of OFFRAM1 field.

Definition at line 3776 of file nrf51_bitfields.h.

◆ POWER_RAMON_OFFRAM1_Pos

#define POWER_RAMON_OFFRAM1_Pos (17UL)

Position of OFFRAM1 field.

Definition at line 3775 of file nrf51_bitfields.h.

◆ POWER_RAMON_OFFRAM1_RAM1Off

#define POWER_RAMON_OFFRAM1_RAM1Off (0UL)

RAM block 1 OFF in OFF mode.

Definition at line 3777 of file nrf51_bitfields.h.

◆ POWER_RAMON_OFFRAM1_RAM1On

#define POWER_RAMON_OFFRAM1_RAM1On (1UL)

RAM block 1 ON in OFF mode.

Definition at line 3778 of file nrf51_bitfields.h.

◆ POWER_RAMON_ONRAM0_Msk

#define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos)

Bit mask of ONRAM0 field.

Definition at line 3794 of file nrf51_bitfields.h.

◆ POWER_RAMON_ONRAM0_Pos

#define POWER_RAMON_ONRAM0_Pos (0UL)

Position of ONRAM0 field.

Definition at line 3793 of file nrf51_bitfields.h.

◆ POWER_RAMON_ONRAM0_RAM0Off

#define POWER_RAMON_ONRAM0_RAM0Off (0UL)

RAM block 0 OFF in ON mode.

Definition at line 3795 of file nrf51_bitfields.h.

◆ POWER_RAMON_ONRAM0_RAM0On

#define POWER_RAMON_ONRAM0_RAM0On (1UL)

RAM block 0 ON in ON mode.

Definition at line 3796 of file nrf51_bitfields.h.

◆ POWER_RAMON_ONRAM1_Msk

#define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos)

Bit mask of ONRAM1 field.

Definition at line 3788 of file nrf51_bitfields.h.

◆ POWER_RAMON_ONRAM1_Pos

#define POWER_RAMON_ONRAM1_Pos (1UL)

Position of ONRAM1 field.

Definition at line 3787 of file nrf51_bitfields.h.

◆ POWER_RAMON_ONRAM1_RAM1Off

#define POWER_RAMON_ONRAM1_RAM1Off (0UL)

RAM block 1 OFF in ON mode.

Definition at line 3789 of file nrf51_bitfields.h.

◆ POWER_RAMON_ONRAM1_RAM1On

#define POWER_RAMON_ONRAM1_RAM1On (1UL)

RAM block 1 ON in ON mode.

Definition at line 3790 of file nrf51_bitfields.h.

◆ POWER_RAMONB_OFFRAM2_Msk

#define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos)

Bit mask of OFFRAM2 field.

Definition at line 3818 of file nrf51_bitfields.h.

◆ POWER_RAMONB_OFFRAM2_Pos

#define POWER_RAMONB_OFFRAM2_Pos (16UL)

Position of OFFRAM2 field.

Definition at line 3817 of file nrf51_bitfields.h.

◆ POWER_RAMONB_OFFRAM2_RAM2Off

#define POWER_RAMONB_OFFRAM2_RAM2Off (0UL)

RAM block 2 OFF in OFF mode.

Definition at line 3819 of file nrf51_bitfields.h.

◆ POWER_RAMONB_OFFRAM2_RAM2On

#define POWER_RAMONB_OFFRAM2_RAM2On (1UL)

RAM block 2 ON in OFF mode.

Definition at line 3820 of file nrf51_bitfields.h.

◆ POWER_RAMONB_OFFRAM3_Msk

#define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos)

Bit mask of OFFRAM3 field.

Definition at line 3812 of file nrf51_bitfields.h.

◆ POWER_RAMONB_OFFRAM3_Pos

#define POWER_RAMONB_OFFRAM3_Pos (17UL)

Position of OFFRAM3 field.

Definition at line 3811 of file nrf51_bitfields.h.

◆ POWER_RAMONB_OFFRAM3_RAM3Off

#define POWER_RAMONB_OFFRAM3_RAM3Off (0UL)

RAM block 3 OFF in OFF mode.

Definition at line 3813 of file nrf51_bitfields.h.

◆ POWER_RAMONB_OFFRAM3_RAM3On

#define POWER_RAMONB_OFFRAM3_RAM3On (1UL)

RAM block 3 ON in OFF mode.

Definition at line 3814 of file nrf51_bitfields.h.

◆ POWER_RAMONB_ONRAM2_Msk

#define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos)

Bit mask of ONRAM2 field.

Definition at line 3830 of file nrf51_bitfields.h.

◆ POWER_RAMONB_ONRAM2_Pos

#define POWER_RAMONB_ONRAM2_Pos (0UL)

Position of ONRAM2 field.

Definition at line 3829 of file nrf51_bitfields.h.

◆ POWER_RAMONB_ONRAM2_RAM2Off

#define POWER_RAMONB_ONRAM2_RAM2Off (0UL)

RAM block 2 OFF in ON mode.

Definition at line 3831 of file nrf51_bitfields.h.

◆ POWER_RAMONB_ONRAM2_RAM2On

#define POWER_RAMONB_ONRAM2_RAM2On (1UL)

RAM block 2 ON in ON mode.

Definition at line 3832 of file nrf51_bitfields.h.

◆ POWER_RAMONB_ONRAM3_Msk

#define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos)

Bit mask of ONRAM3 field.

Definition at line 3824 of file nrf51_bitfields.h.

◆ POWER_RAMONB_ONRAM3_Pos

#define POWER_RAMONB_ONRAM3_Pos (1UL)

Position of ONRAM3 field.

Definition at line 3823 of file nrf51_bitfields.h.

◆ POWER_RAMONB_ONRAM3_RAM3Off

#define POWER_RAMONB_ONRAM3_RAM3Off (0UL)

RAM block 33 OFF in ON mode.

Definition at line 3825 of file nrf51_bitfields.h.

◆ POWER_RAMONB_ONRAM3_RAM3On

#define POWER_RAMONB_ONRAM3_RAM3On (1UL)

RAM block 3 ON in ON mode.

Definition at line 3826 of file nrf51_bitfields.h.

◆ POWER_RAMSTATUS_RAMBLOCK0_Msk

#define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos)

Bit mask of RAMBLOCK0 field.

Definition at line 3735 of file nrf51_bitfields.h.

◆ POWER_RAMSTATUS_RAMBLOCK0_Off

#define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL)

RAM block 0 is off or powering up.

Definition at line 3736 of file nrf51_bitfields.h.

◆ POWER_RAMSTATUS_RAMBLOCK0_On

#define POWER_RAMSTATUS_RAMBLOCK0_On (1UL)

RAM block 0 is on.

Definition at line 3737 of file nrf51_bitfields.h.

◆ POWER_RAMSTATUS_RAMBLOCK0_Pos

#define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL)

Position of RAMBLOCK0 field.

Definition at line 3734 of file nrf51_bitfields.h.

◆ POWER_RAMSTATUS_RAMBLOCK1_Msk

#define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos)

Bit mask of RAMBLOCK1 field.

Definition at line 3729 of file nrf51_bitfields.h.

◆ POWER_RAMSTATUS_RAMBLOCK1_Off

#define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL)

RAM block 1 is off or powering up.

Definition at line 3730 of file nrf51_bitfields.h.

◆ POWER_RAMSTATUS_RAMBLOCK1_On

#define POWER_RAMSTATUS_RAMBLOCK1_On (1UL)

RAM block 1 is on.

Definition at line 3731 of file nrf51_bitfields.h.

◆ POWER_RAMSTATUS_RAMBLOCK1_Pos

#define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL)

Position of RAMBLOCK1 field.

Definition at line 3728 of file nrf51_bitfields.h.

◆ POWER_RAMSTATUS_RAMBLOCK2_Msk

#define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos)

Bit mask of RAMBLOCK2 field.

Definition at line 3723 of file nrf51_bitfields.h.

◆ POWER_RAMSTATUS_RAMBLOCK2_Off

#define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL)

RAM block 2 is off or powering up.

Definition at line 3724 of file nrf51_bitfields.h.

◆ POWER_RAMSTATUS_RAMBLOCK2_On

#define POWER_RAMSTATUS_RAMBLOCK2_On (1UL)

RAM block 2 is on.

Definition at line 3725 of file nrf51_bitfields.h.

◆ POWER_RAMSTATUS_RAMBLOCK2_Pos

#define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL)

Position of RAMBLOCK2 field.

Definition at line 3722 of file nrf51_bitfields.h.

◆ POWER_RAMSTATUS_RAMBLOCK3_Msk

#define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos)

Bit mask of RAMBLOCK3 field.

Definition at line 3717 of file nrf51_bitfields.h.

◆ POWER_RAMSTATUS_RAMBLOCK3_Off

#define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL)

RAM block 3 is off or powering up.

Definition at line 3718 of file nrf51_bitfields.h.

◆ POWER_RAMSTATUS_RAMBLOCK3_On

#define POWER_RAMSTATUS_RAMBLOCK3_On (1UL)

RAM block 3 is on.

Definition at line 3719 of file nrf51_bitfields.h.

◆ POWER_RAMSTATUS_RAMBLOCK3_Pos

#define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL)

Position of RAMBLOCK3 field.

Definition at line 3716 of file nrf51_bitfields.h.

◆ POWER_RESET_RESET_Disabled

#define POWER_RESET_RESET_Disabled (0UL)

Pin reset in debug interface mode disabled.

Definition at line 3804 of file nrf51_bitfields.h.

◆ POWER_RESET_RESET_Enabled

#define POWER_RESET_RESET_Enabled (1UL)

Pin reset in debug interface mode enabled.

Definition at line 3805 of file nrf51_bitfields.h.

◆ POWER_RESET_RESET_Msk

#define POWER_RESET_RESET_Msk (0x1UL << POWER_RESET_RESET_Pos)

Bit mask of RESET field.

Definition at line 3803 of file nrf51_bitfields.h.

◆ POWER_RESET_RESET_Pos

#define POWER_RESET_RESET_Pos (0UL)

Position of RESET field.

Definition at line 3802 of file nrf51_bitfields.h.

◆ POWER_RESETREAS_DIF_Detected

#define POWER_RESETREAS_DIF_Detected (1UL)

Reset detected.

Definition at line 3674 of file nrf51_bitfields.h.

◆ POWER_RESETREAS_DIF_Msk

#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos)

Bit mask of DIF field.

Definition at line 3672 of file nrf51_bitfields.h.

◆ POWER_RESETREAS_DIF_NotDetected

#define POWER_RESETREAS_DIF_NotDetected (0UL)

Reset not detected.

Definition at line 3673 of file nrf51_bitfields.h.

◆ POWER_RESETREAS_DIF_Pos

#define POWER_RESETREAS_DIF_Pos (18UL)

Position of DIF field.

Definition at line 3671 of file nrf51_bitfields.h.

◆ POWER_RESETREAS_DOG_Detected

#define POWER_RESETREAS_DOG_Detected (1UL)

Reset detected.

Definition at line 3704 of file nrf51_bitfields.h.

◆ POWER_RESETREAS_DOG_Msk

#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos)

Bit mask of DOG field.

Definition at line 3702 of file nrf51_bitfields.h.

◆ POWER_RESETREAS_DOG_NotDetected

#define POWER_RESETREAS_DOG_NotDetected (0UL)

Reset not detected.

Definition at line 3703 of file nrf51_bitfields.h.

◆ POWER_RESETREAS_DOG_Pos

#define POWER_RESETREAS_DOG_Pos (1UL)

Position of DOG field.

Definition at line 3701 of file nrf51_bitfields.h.

◆ POWER_RESETREAS_LOCKUP_Detected

#define POWER_RESETREAS_LOCKUP_Detected (1UL)

Reset detected.

Definition at line 3692 of file nrf51_bitfields.h.

◆ POWER_RESETREAS_LOCKUP_Msk

#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos)

Bit mask of LOCKUP field.

Definition at line 3690 of file nrf51_bitfields.h.

◆ POWER_RESETREAS_LOCKUP_NotDetected

#define POWER_RESETREAS_LOCKUP_NotDetected (0UL)

Reset not detected.

Definition at line 3691 of file nrf51_bitfields.h.

◆ POWER_RESETREAS_LOCKUP_Pos

#define POWER_RESETREAS_LOCKUP_Pos (3UL)

Position of LOCKUP field.

Definition at line 3689 of file nrf51_bitfields.h.

◆ POWER_RESETREAS_LPCOMP_Detected

#define POWER_RESETREAS_LPCOMP_Detected (1UL)

Reset detected.

Definition at line 3680 of file nrf51_bitfields.h.

◆ POWER_RESETREAS_LPCOMP_Msk

#define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos)

Bit mask of LPCOMP field.

Definition at line 3678 of file nrf51_bitfields.h.

◆ POWER_RESETREAS_LPCOMP_NotDetected

#define POWER_RESETREAS_LPCOMP_NotDetected (0UL)

Reset not detected.

Definition at line 3679 of file nrf51_bitfields.h.

◆ POWER_RESETREAS_LPCOMP_Pos

#define POWER_RESETREAS_LPCOMP_Pos (17UL)

Position of LPCOMP field.

Definition at line 3677 of file nrf51_bitfields.h.

◆ POWER_RESETREAS_OFF_Detected

#define POWER_RESETREAS_OFF_Detected (1UL)

Reset detected.

Definition at line 3686 of file nrf51_bitfields.h.

◆ POWER_RESETREAS_OFF_Msk

#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos)

Bit mask of OFF field.

Definition at line 3684 of file nrf51_bitfields.h.

◆ POWER_RESETREAS_OFF_NotDetected

#define POWER_RESETREAS_OFF_NotDetected (0UL)

Reset not detected.

Definition at line 3685 of file nrf51_bitfields.h.

◆ POWER_RESETREAS_OFF_Pos

#define POWER_RESETREAS_OFF_Pos (16UL)

Position of OFF field.

Definition at line 3683 of file nrf51_bitfields.h.

◆ POWER_RESETREAS_RESETPIN_Detected

#define POWER_RESETREAS_RESETPIN_Detected (1UL)

Reset detected.

Definition at line 3710 of file nrf51_bitfields.h.

◆ POWER_RESETREAS_RESETPIN_Msk

#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos)

Bit mask of RESETPIN field.

Definition at line 3708 of file nrf51_bitfields.h.

◆ POWER_RESETREAS_RESETPIN_NotDetected

#define POWER_RESETREAS_RESETPIN_NotDetected (0UL)

Reset not detected.

Definition at line 3709 of file nrf51_bitfields.h.

◆ POWER_RESETREAS_RESETPIN_Pos

#define POWER_RESETREAS_RESETPIN_Pos (0UL)

Position of RESETPIN field.

Definition at line 3707 of file nrf51_bitfields.h.

◆ POWER_RESETREAS_SREQ_Detected

#define POWER_RESETREAS_SREQ_Detected (1UL)

Reset detected.

Definition at line 3698 of file nrf51_bitfields.h.

◆ POWER_RESETREAS_SREQ_Msk

#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos)

Bit mask of SREQ field.

Definition at line 3696 of file nrf51_bitfields.h.

◆ POWER_RESETREAS_SREQ_NotDetected

#define POWER_RESETREAS_SREQ_NotDetected (0UL)

Reset not detected.

Definition at line 3697 of file nrf51_bitfields.h.

◆ POWER_RESETREAS_SREQ_Pos

#define POWER_RESETREAS_SREQ_Pos (2UL)

Position of SREQ field.

Definition at line 3695 of file nrf51_bitfields.h.

◆ POWER_SYSTEMOFF_SYSTEMOFF_Enter

#define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL)

Enter system off mode.

Definition at line 3745 of file nrf51_bitfields.h.

◆ POWER_SYSTEMOFF_SYSTEMOFF_Msk

#define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos)

Bit mask of SYSTEMOFF field.

Definition at line 3744 of file nrf51_bitfields.h.

◆ POWER_SYSTEMOFF_SYSTEMOFF_Pos

#define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL)

Position of SYSTEMOFF field.

Definition at line 3743 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH0_Disabled

#define PPI_CHEN_CH0_Disabled (0UL)

Channel disabled.

Definition at line 4030 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH0_Enabled

#define PPI_CHEN_CH0_Enabled (1UL)

Channel enabled.

Definition at line 4031 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH0_Msk

#define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos)

Bit mask of CH0 field.

Definition at line 4029 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH0_Pos

#define PPI_CHEN_CH0_Pos (0UL)

Position of CH0 field.

Definition at line 4028 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH10_Disabled

#define PPI_CHEN_CH10_Disabled (0UL)

Channel disabled.

Definition at line 3970 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH10_Enabled

#define PPI_CHEN_CH10_Enabled (1UL)

Channel enabled.

Definition at line 3971 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH10_Msk

#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos)

Bit mask of CH10 field.

Definition at line 3969 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH10_Pos

#define PPI_CHEN_CH10_Pos (10UL)

Position of CH10 field.

Definition at line 3968 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH11_Disabled

#define PPI_CHEN_CH11_Disabled (0UL)

Channel disabled.

Definition at line 3964 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH11_Enabled

#define PPI_CHEN_CH11_Enabled (1UL)

Channel enabled.

Definition at line 3965 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH11_Msk

#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos)

Bit mask of CH11 field.

Definition at line 3963 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH11_Pos

#define PPI_CHEN_CH11_Pos (11UL)

Position of CH11 field.

Definition at line 3962 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH12_Disabled

#define PPI_CHEN_CH12_Disabled (0UL)

Channel disabled.

Definition at line 3958 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH12_Enabled

#define PPI_CHEN_CH12_Enabled (1UL)

Channel enabled.

Definition at line 3959 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH12_Msk

#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos)

Bit mask of CH12 field.

Definition at line 3957 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH12_Pos

#define PPI_CHEN_CH12_Pos (12UL)

Position of CH12 field.

Definition at line 3956 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH13_Disabled

#define PPI_CHEN_CH13_Disabled (0UL)

Channel disabled.

Definition at line 3952 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH13_Enabled

#define PPI_CHEN_CH13_Enabled (1UL)

Channel enabled.

Definition at line 3953 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH13_Msk

#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos)

Bit mask of CH13 field.

Definition at line 3951 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH13_Pos

#define PPI_CHEN_CH13_Pos (13UL)

Position of CH13 field.

Definition at line 3950 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH14_Disabled

#define PPI_CHEN_CH14_Disabled (0UL)

Channel disabled.

Definition at line 3946 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH14_Enabled

#define PPI_CHEN_CH14_Enabled (1UL)

Channel enabled.

Definition at line 3947 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH14_Msk

#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos)

Bit mask of CH14 field.

Definition at line 3945 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH14_Pos

#define PPI_CHEN_CH14_Pos (14UL)

Position of CH14 field.

Definition at line 3944 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH15_Disabled

#define PPI_CHEN_CH15_Disabled (0UL)

Channel disabled.

Definition at line 3940 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH15_Enabled

#define PPI_CHEN_CH15_Enabled (1UL)

Channel enabled.

Definition at line 3941 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH15_Msk

#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos)

Bit mask of CH15 field.

Definition at line 3939 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH15_Pos

#define PPI_CHEN_CH15_Pos (15UL)

Position of CH15 field.

Definition at line 3938 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH1_Disabled

#define PPI_CHEN_CH1_Disabled (0UL)

Channel disabled.

Definition at line 4024 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH1_Enabled

#define PPI_CHEN_CH1_Enabled (1UL)

Channel enabled.

Definition at line 4025 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH1_Msk

#define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos)

Bit mask of CH1 field.

Definition at line 4023 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH1_Pos

#define PPI_CHEN_CH1_Pos (1UL)

Position of CH1 field.

Definition at line 4022 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH20_Disabled

#define PPI_CHEN_CH20_Disabled (0UL)

Channel disabled.

Definition at line 3934 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH20_Enabled

#define PPI_CHEN_CH20_Enabled (1UL)

Channel enabled.

Definition at line 3935 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH20_Msk

#define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos)

Bit mask of CH20 field.

Definition at line 3933 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH20_Pos

#define PPI_CHEN_CH20_Pos (20UL)

Position of CH20 field.

Definition at line 3932 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH21_Disabled

#define PPI_CHEN_CH21_Disabled (0UL)

Channel disabled.

Definition at line 3928 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH21_Enabled

#define PPI_CHEN_CH21_Enabled (1UL)

Channel enabled.

Definition at line 3929 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH21_Msk

#define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos)

Bit mask of CH21 field.

Definition at line 3927 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH21_Pos

#define PPI_CHEN_CH21_Pos (21UL)

Position of CH21 field.

Definition at line 3926 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH22_Disabled

#define PPI_CHEN_CH22_Disabled (0UL)

Channel disabled.

Definition at line 3922 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH22_Enabled

#define PPI_CHEN_CH22_Enabled (1UL)

Channel enabled.

Definition at line 3923 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH22_Msk

#define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos)

Bit mask of CH22 field.

Definition at line 3921 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH22_Pos

#define PPI_CHEN_CH22_Pos (22UL)

Position of CH22 field.

Definition at line 3920 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH23_Disabled

#define PPI_CHEN_CH23_Disabled (0UL)

Channel disabled.

Definition at line 3916 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH23_Enabled

#define PPI_CHEN_CH23_Enabled (1UL)

Channel enabled.

Definition at line 3917 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH23_Msk

#define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos)

Bit mask of CH23 field.

Definition at line 3915 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH23_Pos

#define PPI_CHEN_CH23_Pos (23UL)

Position of CH23 field.

Definition at line 3914 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH24_Disabled

#define PPI_CHEN_CH24_Disabled (0UL)

Channel disabled.

Definition at line 3910 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH24_Enabled

#define PPI_CHEN_CH24_Enabled (1UL)

Channel enabled.

Definition at line 3911 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH24_Msk

#define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos)

Bit mask of CH24 field.

Definition at line 3909 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH24_Pos

#define PPI_CHEN_CH24_Pos (24UL)

Position of CH24 field.

Definition at line 3908 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH25_Disabled

#define PPI_CHEN_CH25_Disabled (0UL)

Channel disabled.

Definition at line 3904 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH25_Enabled

#define PPI_CHEN_CH25_Enabled (1UL)

Channel enabled.

Definition at line 3905 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH25_Msk

#define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos)

Bit mask of CH25 field.

Definition at line 3903 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH25_Pos

#define PPI_CHEN_CH25_Pos (25UL)

Position of CH25 field.

Definition at line 3902 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH26_Disabled

#define PPI_CHEN_CH26_Disabled (0UL)

Channel disabled.

Definition at line 3898 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH26_Enabled

#define PPI_CHEN_CH26_Enabled (1UL)

Channel enabled.

Definition at line 3899 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH26_Msk

#define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos)

Bit mask of CH26 field.

Definition at line 3897 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH26_Pos

#define PPI_CHEN_CH26_Pos (26UL)

Position of CH26 field.

Definition at line 3896 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH27_Disabled

#define PPI_CHEN_CH27_Disabled (0UL)

Channel disabled.

Definition at line 3892 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH27_Enabled

#define PPI_CHEN_CH27_Enabled (1UL)

Channel enabled.

Definition at line 3893 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH27_Msk

#define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos)

Bit mask of CH27 field.

Definition at line 3891 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH27_Pos

#define PPI_CHEN_CH27_Pos (27UL)

Position of CH27 field.

Definition at line 3890 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH28_Disabled

#define PPI_CHEN_CH28_Disabled (0UL)

Channel disabled.

Definition at line 3886 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH28_Enabled

#define PPI_CHEN_CH28_Enabled (1UL)

Channel enabled.

Definition at line 3887 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH28_Msk

#define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos)

Bit mask of CH28 field.

Definition at line 3885 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH28_Pos

#define PPI_CHEN_CH28_Pos (28UL)

Position of CH28 field.

Definition at line 3884 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH29_Disabled

#define PPI_CHEN_CH29_Disabled (0UL)

Channel disabled.

Definition at line 3880 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH29_Enabled

#define PPI_CHEN_CH29_Enabled (1UL)

Channel enabled.

Definition at line 3881 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH29_Msk

#define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos)

Bit mask of CH29 field.

Definition at line 3879 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH29_Pos

#define PPI_CHEN_CH29_Pos (29UL)

Position of CH29 field.

Definition at line 3878 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH2_Disabled

#define PPI_CHEN_CH2_Disabled (0UL)

Channel disabled.

Definition at line 4018 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH2_Enabled

#define PPI_CHEN_CH2_Enabled (1UL)

Channel enabled.

Definition at line 4019 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH2_Msk

#define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos)

Bit mask of CH2 field.

Definition at line 4017 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH2_Pos

#define PPI_CHEN_CH2_Pos (2UL)

Position of CH2 field.

Definition at line 4016 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH30_Disabled

#define PPI_CHEN_CH30_Disabled (0UL)

Channel disabled.

Definition at line 3874 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH30_Enabled

#define PPI_CHEN_CH30_Enabled (1UL)

Channel enabled.

Definition at line 3875 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH30_Msk

#define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos)

Bit mask of CH30 field.

Definition at line 3873 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH30_Pos

#define PPI_CHEN_CH30_Pos (30UL)

Position of CH30 field.

Definition at line 3872 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH31_Disabled

#define PPI_CHEN_CH31_Disabled (0UL)

Channel disabled.

Definition at line 3868 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH31_Enabled

#define PPI_CHEN_CH31_Enabled (1UL)

Channel enabled.

Definition at line 3869 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH31_Msk

#define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos)

Bit mask of CH31 field.

Definition at line 3867 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH31_Pos

#define PPI_CHEN_CH31_Pos (31UL)

Position of CH31 field.

Definition at line 3866 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH3_Disabled

#define PPI_CHEN_CH3_Disabled (0UL)

Channel disabled

Definition at line 4012 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH3_Enabled

#define PPI_CHEN_CH3_Enabled (1UL)

Channel enabled

Definition at line 4013 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH3_Msk

#define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos)

Bit mask of CH3 field.

Definition at line 4011 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH3_Pos

#define PPI_CHEN_CH3_Pos (3UL)

Position of CH3 field.

Definition at line 4010 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH4_Disabled

#define PPI_CHEN_CH4_Disabled (0UL)

Channel disabled.

Definition at line 4006 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH4_Enabled

#define PPI_CHEN_CH4_Enabled (1UL)

Channel enabled.

Definition at line 4007 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH4_Msk

#define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos)

Bit mask of CH4 field.

Definition at line 4005 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH4_Pos

#define PPI_CHEN_CH4_Pos (4UL)

Position of CH4 field.

Definition at line 4004 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH5_Disabled

#define PPI_CHEN_CH5_Disabled (0UL)

Channel disabled.

Definition at line 4000 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH5_Enabled

#define PPI_CHEN_CH5_Enabled (1UL)

Channel enabled.

Definition at line 4001 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH5_Msk

#define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos)

Bit mask of CH5 field.

Definition at line 3999 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH5_Pos

#define PPI_CHEN_CH5_Pos (5UL)

Position of CH5 field.

Definition at line 3998 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH6_Disabled

#define PPI_CHEN_CH6_Disabled (0UL)

Channel disabled.

Definition at line 3994 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH6_Enabled

#define PPI_CHEN_CH6_Enabled (1UL)

Channel enabled.

Definition at line 3995 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH6_Msk

#define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos)

Bit mask of CH6 field.

Definition at line 3993 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH6_Pos

#define PPI_CHEN_CH6_Pos (6UL)

Position of CH6 field.

Definition at line 3992 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH7_Disabled

#define PPI_CHEN_CH7_Disabled (0UL)

Channel disabled.

Definition at line 3988 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH7_Enabled

#define PPI_CHEN_CH7_Enabled (1UL)

Channel enabled.

Definition at line 3989 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH7_Msk

#define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos)

Bit mask of CH7 field.

Definition at line 3987 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH7_Pos

#define PPI_CHEN_CH7_Pos (7UL)

Position of CH7 field.

Definition at line 3986 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH8_Disabled

#define PPI_CHEN_CH8_Disabled (0UL)

Channel disabled.

Definition at line 3982 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH8_Enabled

#define PPI_CHEN_CH8_Enabled (1UL)

Channel enabled.

Definition at line 3983 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH8_Msk

#define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos)

Bit mask of CH8 field.

Definition at line 3981 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH8_Pos

#define PPI_CHEN_CH8_Pos (8UL)

Position of CH8 field.

Definition at line 3980 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH9_Disabled

#define PPI_CHEN_CH9_Disabled (0UL)

Channel disabled.

Definition at line 3976 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH9_Enabled

#define PPI_CHEN_CH9_Enabled (1UL)

Channel enabled.

Definition at line 3977 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH9_Msk

#define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos)

Bit mask of CH9 field.

Definition at line 3975 of file nrf51_bitfields.h.

◆ PPI_CHEN_CH9_Pos

#define PPI_CHEN_CH9_Pos (9UL)

Position of CH9 field.

Definition at line 3974 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH0_Clear

#define PPI_CHENCLR_CH0_Clear (1UL)

Disable channel on write.

Definition at line 4429 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH0_Disabled

#define PPI_CHENCLR_CH0_Disabled (0UL)

Channel disabled.

Definition at line 4427 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH0_Enabled

#define PPI_CHENCLR_CH0_Enabled (1UL)

Channel enabled.

Definition at line 4428 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH0_Msk

#define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos)

Bit mask of CH0 field.

Definition at line 4426 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH0_Pos

#define PPI_CHENCLR_CH0_Pos (0UL)

Position of CH0 field.

Definition at line 4425 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH10_Clear

#define PPI_CHENCLR_CH10_Clear (1UL)

Disable channel on write.

Definition at line 4359 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH10_Disabled

#define PPI_CHENCLR_CH10_Disabled (0UL)

Channel disabled.

Definition at line 4357 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH10_Enabled

#define PPI_CHENCLR_CH10_Enabled (1UL)

Channel enabled.

Definition at line 4358 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH10_Msk

#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos)

Bit mask of CH10 field.

Definition at line 4356 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH10_Pos

#define PPI_CHENCLR_CH10_Pos (10UL)

Position of CH10 field.

Definition at line 4355 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH11_Clear

#define PPI_CHENCLR_CH11_Clear (1UL)

Disable channel on write.

Definition at line 4352 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH11_Disabled

#define PPI_CHENCLR_CH11_Disabled (0UL)

Channel disabled.

Definition at line 4350 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH11_Enabled

#define PPI_CHENCLR_CH11_Enabled (1UL)

Channel enabled.

Definition at line 4351 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH11_Msk

#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos)

Bit mask of CH11 field.

Definition at line 4349 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH11_Pos

#define PPI_CHENCLR_CH11_Pos (11UL)

Position of CH11 field.

Definition at line 4348 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH12_Clear

#define PPI_CHENCLR_CH12_Clear (1UL)

Disable channel on write.

Definition at line 4345 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH12_Disabled

#define PPI_CHENCLR_CH12_Disabled (0UL)

Channel disabled.

Definition at line 4343 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH12_Enabled

#define PPI_CHENCLR_CH12_Enabled (1UL)

Channel enabled.

Definition at line 4344 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH12_Msk

#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos)

Bit mask of CH12 field.

Definition at line 4342 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH12_Pos

#define PPI_CHENCLR_CH12_Pos (12UL)

Position of CH12 field.

Definition at line 4341 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH13_Clear

#define PPI_CHENCLR_CH13_Clear (1UL)

Disable channel on write.

Definition at line 4338 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH13_Disabled

#define PPI_CHENCLR_CH13_Disabled (0UL)

Channel disabled.

Definition at line 4336 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH13_Enabled

#define PPI_CHENCLR_CH13_Enabled (1UL)

Channel enabled.

Definition at line 4337 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH13_Msk

#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos)

Bit mask of CH13 field.

Definition at line 4335 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH13_Pos

#define PPI_CHENCLR_CH13_Pos (13UL)

Position of CH13 field.

Definition at line 4334 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH14_Clear

#define PPI_CHENCLR_CH14_Clear (1UL)

Disable channel on write.

Definition at line 4331 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH14_Disabled

#define PPI_CHENCLR_CH14_Disabled (0UL)

Channel disabled.

Definition at line 4329 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH14_Enabled

#define PPI_CHENCLR_CH14_Enabled (1UL)

Channel enabled.

Definition at line 4330 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH14_Msk

#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos)

Bit mask of CH14 field.

Definition at line 4328 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH14_Pos

#define PPI_CHENCLR_CH14_Pos (14UL)

Position of CH14 field.

Definition at line 4327 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH15_Clear

#define PPI_CHENCLR_CH15_Clear (1UL)

Disable channel on write.

Definition at line 4324 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH15_Disabled

#define PPI_CHENCLR_CH15_Disabled (0UL)

Channel disabled.

Definition at line 4322 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH15_Enabled

#define PPI_CHENCLR_CH15_Enabled (1UL)

Channel enabled.

Definition at line 4323 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH15_Msk

#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos)

Bit mask of CH15 field.

Definition at line 4321 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH15_Pos

#define PPI_CHENCLR_CH15_Pos (15UL)

Position of CH15 field.

Definition at line 4320 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH1_Clear

#define PPI_CHENCLR_CH1_Clear (1UL)

Disable channel on write.

Definition at line 4422 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH1_Disabled

#define PPI_CHENCLR_CH1_Disabled (0UL)

Channel disabled.

Definition at line 4420 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH1_Enabled

#define PPI_CHENCLR_CH1_Enabled (1UL)

Channel enabled.

Definition at line 4421 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH1_Msk

#define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos)

Bit mask of CH1 field.

Definition at line 4419 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH1_Pos

#define PPI_CHENCLR_CH1_Pos (1UL)

Position of CH1 field.

Definition at line 4418 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH20_Clear

#define PPI_CHENCLR_CH20_Clear (1UL)

Disable channel on write.

Definition at line 4317 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH20_Disabled

#define PPI_CHENCLR_CH20_Disabled (0UL)

Channel disabled.

Definition at line 4315 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH20_Enabled

#define PPI_CHENCLR_CH20_Enabled (1UL)

Channel enabled.

Definition at line 4316 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH20_Msk

#define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos)

Bit mask of CH20 field.

Definition at line 4314 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH20_Pos

#define PPI_CHENCLR_CH20_Pos (20UL)

Position of CH20 field.

Definition at line 4313 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH21_Clear

#define PPI_CHENCLR_CH21_Clear (1UL)

Disable channel on write.

Definition at line 4310 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH21_Disabled

#define PPI_CHENCLR_CH21_Disabled (0UL)

Channel disabled.

Definition at line 4308 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH21_Enabled

#define PPI_CHENCLR_CH21_Enabled (1UL)

Channel enabled.

Definition at line 4309 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH21_Msk

#define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos)

Bit mask of CH21 field.

Definition at line 4307 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH21_Pos

#define PPI_CHENCLR_CH21_Pos (21UL)

Position of CH21 field.

Definition at line 4306 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH22_Clear

#define PPI_CHENCLR_CH22_Clear (1UL)

Disable channel on write.

Definition at line 4303 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH22_Disabled

#define PPI_CHENCLR_CH22_Disabled (0UL)

Channel disabled.

Definition at line 4301 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH22_Enabled

#define PPI_CHENCLR_CH22_Enabled (1UL)

Channel enabled.

Definition at line 4302 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH22_Msk

#define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos)

Bit mask of CH22 field.

Definition at line 4300 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH22_Pos

#define PPI_CHENCLR_CH22_Pos (22UL)

Position of CH22 field.

Definition at line 4299 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH23_Clear

#define PPI_CHENCLR_CH23_Clear (1UL)

Disable channel on write.

Definition at line 4296 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH23_Disabled

#define PPI_CHENCLR_CH23_Disabled (0UL)

Channel disabled.

Definition at line 4294 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH23_Enabled

#define PPI_CHENCLR_CH23_Enabled (1UL)

Channel enabled.

Definition at line 4295 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH23_Msk

#define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos)

Bit mask of CH23 field.

Definition at line 4293 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH23_Pos

#define PPI_CHENCLR_CH23_Pos (23UL)

Position of CH23 field.

Definition at line 4292 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH24_Clear

#define PPI_CHENCLR_CH24_Clear (1UL)

Disable channel on write.

Definition at line 4289 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH24_Disabled

#define PPI_CHENCLR_CH24_Disabled (0UL)

Channel disabled.

Definition at line 4287 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH24_Enabled

#define PPI_CHENCLR_CH24_Enabled (1UL)

Channel enabled.

Definition at line 4288 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH24_Msk

#define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos)

Bit mask of CH24 field.

Definition at line 4286 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH24_Pos

#define PPI_CHENCLR_CH24_Pos (24UL)

Position of CH24 field.

Definition at line 4285 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH25_Clear

#define PPI_CHENCLR_CH25_Clear (1UL)

Disable channel on write.

Definition at line 4282 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH25_Disabled

#define PPI_CHENCLR_CH25_Disabled (0UL)

Channel disabled.

Definition at line 4280 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH25_Enabled

#define PPI_CHENCLR_CH25_Enabled (1UL)

Channel enabled.

Definition at line 4281 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH25_Msk

#define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos)

Bit mask of CH25 field.

Definition at line 4279 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH25_Pos

#define PPI_CHENCLR_CH25_Pos (25UL)

Position of CH25 field.

Definition at line 4278 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH26_Clear

#define PPI_CHENCLR_CH26_Clear (1UL)

Disable channel on write.

Definition at line 4275 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH26_Disabled

#define PPI_CHENCLR_CH26_Disabled (0UL)

Channel disabled.

Definition at line 4273 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH26_Enabled

#define PPI_CHENCLR_CH26_Enabled (1UL)

Channel enabled.

Definition at line 4274 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH26_Msk

#define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos)

Bit mask of CH26 field.

Definition at line 4272 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH26_Pos

#define PPI_CHENCLR_CH26_Pos (26UL)

Position of CH26 field.

Definition at line 4271 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH27_Clear

#define PPI_CHENCLR_CH27_Clear (1UL)

Disable channel on write.

Definition at line 4268 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH27_Disabled

#define PPI_CHENCLR_CH27_Disabled (0UL)

Channel disabled.

Definition at line 4266 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH27_Enabled

#define PPI_CHENCLR_CH27_Enabled (1UL)

Channel enabled.

Definition at line 4267 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH27_Msk

#define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos)

Bit mask of CH27 field.

Definition at line 4265 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH27_Pos

#define PPI_CHENCLR_CH27_Pos (27UL)

Position of CH27 field.

Definition at line 4264 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH28_Clear

#define PPI_CHENCLR_CH28_Clear (1UL)

Disable channel on write.

Definition at line 4261 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH28_Disabled

#define PPI_CHENCLR_CH28_Disabled (0UL)

Channel disabled.

Definition at line 4259 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH28_Enabled

#define PPI_CHENCLR_CH28_Enabled (1UL)

Channel enabled.

Definition at line 4260 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH28_Msk

#define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos)

Bit mask of CH28 field.

Definition at line 4258 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH28_Pos

#define PPI_CHENCLR_CH28_Pos (28UL)

Position of CH28 field.

Definition at line 4257 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH29_Clear

#define PPI_CHENCLR_CH29_Clear (1UL)

Disable channel on write.

Definition at line 4254 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH29_Disabled

#define PPI_CHENCLR_CH29_Disabled (0UL)

Channel disabled.

Definition at line 4252 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH29_Enabled

#define PPI_CHENCLR_CH29_Enabled (1UL)

Channel enabled.

Definition at line 4253 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH29_Msk

#define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos)

Bit mask of CH29 field.

Definition at line 4251 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH29_Pos

#define PPI_CHENCLR_CH29_Pos (29UL)

Position of CH29 field.

Definition at line 4250 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH2_Clear

#define PPI_CHENCLR_CH2_Clear (1UL)

Disable channel on write.

Definition at line 4415 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH2_Disabled

#define PPI_CHENCLR_CH2_Disabled (0UL)

Channel disabled.

Definition at line 4413 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH2_Enabled

#define PPI_CHENCLR_CH2_Enabled (1UL)

Channel enabled.

Definition at line 4414 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH2_Msk

#define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos)

Bit mask of CH2 field.

Definition at line 4412 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH2_Pos

#define PPI_CHENCLR_CH2_Pos (2UL)

Position of CH2 field.

Definition at line 4411 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH30_Clear

#define PPI_CHENCLR_CH30_Clear (1UL)

Disable channel on write.

Definition at line 4247 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH30_Disabled

#define PPI_CHENCLR_CH30_Disabled (0UL)

Channel disabled.

Definition at line 4245 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH30_Enabled

#define PPI_CHENCLR_CH30_Enabled (1UL)

Channel enabled.

Definition at line 4246 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH30_Msk

#define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos)

Bit mask of CH30 field.

Definition at line 4244 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH30_Pos

#define PPI_CHENCLR_CH30_Pos (30UL)

Position of CH30 field.

Definition at line 4243 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH31_Clear

#define PPI_CHENCLR_CH31_Clear (1UL)

Disable channel on write.

Definition at line 4240 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH31_Disabled

#define PPI_CHENCLR_CH31_Disabled (0UL)

Channel disabled.

Definition at line 4238 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH31_Enabled

#define PPI_CHENCLR_CH31_Enabled (1UL)

Channel enabled.

Definition at line 4239 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH31_Msk

#define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos)

Bit mask of CH31 field.

Definition at line 4237 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH31_Pos

#define PPI_CHENCLR_CH31_Pos (31UL)

Position of CH31 field.

Definition at line 4236 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH3_Clear

#define PPI_CHENCLR_CH3_Clear (1UL)

Disable channel on write.

Definition at line 4408 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH3_Disabled

#define PPI_CHENCLR_CH3_Disabled (0UL)

Channel disabled.

Definition at line 4406 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH3_Enabled

#define PPI_CHENCLR_CH3_Enabled (1UL)

Channel enabled.

Definition at line 4407 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH3_Msk

#define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos)

Bit mask of CH3 field.

Definition at line 4405 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH3_Pos

#define PPI_CHENCLR_CH3_Pos (3UL)

Position of CH3 field.

Definition at line 4404 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH4_Clear

#define PPI_CHENCLR_CH4_Clear (1UL)

Disable channel on write.

Definition at line 4401 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH4_Disabled

#define PPI_CHENCLR_CH4_Disabled (0UL)

Channel disabled.

Definition at line 4399 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH4_Enabled

#define PPI_CHENCLR_CH4_Enabled (1UL)

Channel enabled.

Definition at line 4400 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH4_Msk

#define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos)

Bit mask of CH4 field.

Definition at line 4398 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH4_Pos

#define PPI_CHENCLR_CH4_Pos (4UL)

Position of CH4 field.

Definition at line 4397 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH5_Clear

#define PPI_CHENCLR_CH5_Clear (1UL)

Disable channel on write.

Definition at line 4394 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH5_Disabled

#define PPI_CHENCLR_CH5_Disabled (0UL)

Channel disabled.

Definition at line 4392 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH5_Enabled

#define PPI_CHENCLR_CH5_Enabled (1UL)

Channel enabled.

Definition at line 4393 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH5_Msk

#define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos)

Bit mask of CH5 field.

Definition at line 4391 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH5_Pos

#define PPI_CHENCLR_CH5_Pos (5UL)

Position of CH5 field.

Definition at line 4390 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH6_Clear

#define PPI_CHENCLR_CH6_Clear (1UL)

Disable channel on write.

Definition at line 4387 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH6_Disabled

#define PPI_CHENCLR_CH6_Disabled (0UL)

Channel disabled.

Definition at line 4385 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH6_Enabled

#define PPI_CHENCLR_CH6_Enabled (1UL)

Channel enabled.

Definition at line 4386 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH6_Msk

#define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos)

Bit mask of CH6 field.

Definition at line 4384 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH6_Pos

#define PPI_CHENCLR_CH6_Pos (6UL)

Position of CH6 field.

Definition at line 4383 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH7_Clear

#define PPI_CHENCLR_CH7_Clear (1UL)

Disable channel on write.

Definition at line 4380 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH7_Disabled

#define PPI_CHENCLR_CH7_Disabled (0UL)

Channel disabled.

Definition at line 4378 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH7_Enabled

#define PPI_CHENCLR_CH7_Enabled (1UL)

Channel enabled.

Definition at line 4379 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH7_Msk

#define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos)

Bit mask of CH7 field.

Definition at line 4377 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH7_Pos

#define PPI_CHENCLR_CH7_Pos (7UL)

Position of CH7 field.

Definition at line 4376 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH8_Clear

#define PPI_CHENCLR_CH8_Clear (1UL)

Disable channel on write.

Definition at line 4373 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH8_Disabled

#define PPI_CHENCLR_CH8_Disabled (0UL)

Channel disabled.

Definition at line 4371 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH8_Enabled

#define PPI_CHENCLR_CH8_Enabled (1UL)

Channel enabled.

Definition at line 4372 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH8_Msk

#define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos)

Bit mask of CH8 field.

Definition at line 4370 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH8_Pos

#define PPI_CHENCLR_CH8_Pos (8UL)

Position of CH8 field.

Definition at line 4369 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH9_Clear

#define PPI_CHENCLR_CH9_Clear (1UL)

Disable channel on write.

Definition at line 4366 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH9_Disabled

#define PPI_CHENCLR_CH9_Disabled (0UL)

Channel disabled.

Definition at line 4364 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH9_Enabled

#define PPI_CHENCLR_CH9_Enabled (1UL)

Channel enabled.

Definition at line 4365 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH9_Msk

#define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos)

Bit mask of CH9 field.

Definition at line 4363 of file nrf51_bitfields.h.

◆ PPI_CHENCLR_CH9_Pos

#define PPI_CHENCLR_CH9_Pos (9UL)

Position of CH9 field.

Definition at line 4362 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH0_Disabled

#define PPI_CHENSET_CH0_Disabled (0UL)

Channel disabled.

Definition at line 4228 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH0_Enabled

#define PPI_CHENSET_CH0_Enabled (1UL)

Channel enabled.

Definition at line 4229 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH0_Msk

#define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos)

Bit mask of CH0 field.

Definition at line 4227 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH0_Pos

#define PPI_CHENSET_CH0_Pos (0UL)

Position of CH0 field.

Definition at line 4226 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH0_Set

#define PPI_CHENSET_CH0_Set (1UL)

Enable channel on write.

Definition at line 4230 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH10_Disabled

#define PPI_CHENSET_CH10_Disabled (0UL)

Channel disabled.

Definition at line 4158 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH10_Enabled

#define PPI_CHENSET_CH10_Enabled (1UL)

Channel enabled.

Definition at line 4159 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH10_Msk

#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos)

Bit mask of CH10 field.

Definition at line 4157 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH10_Pos

#define PPI_CHENSET_CH10_Pos (10UL)

Position of CH10 field.

Definition at line 4156 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH10_Set

#define PPI_CHENSET_CH10_Set (1UL)

Enable channel on write.

Definition at line 4160 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH11_Disabled

#define PPI_CHENSET_CH11_Disabled (0UL)

Channel disabled.

Definition at line 4151 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH11_Enabled

#define PPI_CHENSET_CH11_Enabled (1UL)

Channel enabled.

Definition at line 4152 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH11_Msk

#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos)

Bit mask of CH11 field.

Definition at line 4150 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH11_Pos

#define PPI_CHENSET_CH11_Pos (11UL)

Position of CH11 field.

Definition at line 4149 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH11_Set

#define PPI_CHENSET_CH11_Set (1UL)

Enable channel on write.

Definition at line 4153 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH12_Disabled

#define PPI_CHENSET_CH12_Disabled (0UL)

Channel disabled.

Definition at line 4144 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH12_Enabled

#define PPI_CHENSET_CH12_Enabled (1UL)

Channel enabled.

Definition at line 4145 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH12_Msk

#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos)

Bit mask of CH12 field.

Definition at line 4143 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH12_Pos

#define PPI_CHENSET_CH12_Pos (12UL)

Position of CH12 field.

Definition at line 4142 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH12_Set

#define PPI_CHENSET_CH12_Set (1UL)

Enable channel on write.

Definition at line 4146 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH13_Disabled

#define PPI_CHENSET_CH13_Disabled (0UL)

Channel disabled.

Definition at line 4137 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH13_Enabled

#define PPI_CHENSET_CH13_Enabled (1UL)

Channel enabled.

Definition at line 4138 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH13_Msk

#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos)

Bit mask of CH13 field.

Definition at line 4136 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH13_Pos

#define PPI_CHENSET_CH13_Pos (13UL)

Position of CH13 field.

Definition at line 4135 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH13_Set

#define PPI_CHENSET_CH13_Set (1UL)

Enable channel on write.

Definition at line 4139 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH14_Disabled

#define PPI_CHENSET_CH14_Disabled (0UL)

Channel disabled.

Definition at line 4130 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH14_Enabled

#define PPI_CHENSET_CH14_Enabled (1UL)

Channel enabled.

Definition at line 4131 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH14_Msk

#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos)

Bit mask of CH14 field.

Definition at line 4129 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH14_Pos

#define PPI_CHENSET_CH14_Pos (14UL)

Position of CH14 field.

Definition at line 4128 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH14_Set

#define PPI_CHENSET_CH14_Set (1UL)

Enable channel on write.

Definition at line 4132 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH15_Disabled

#define PPI_CHENSET_CH15_Disabled (0UL)

Channel disabled.

Definition at line 4123 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH15_Enabled

#define PPI_CHENSET_CH15_Enabled (1UL)

Channel enabled.

Definition at line 4124 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH15_Msk

#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos)

Bit mask of CH15 field.

Definition at line 4122 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH15_Pos

#define PPI_CHENSET_CH15_Pos (15UL)

Position of CH15 field.

Definition at line 4121 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH15_Set

#define PPI_CHENSET_CH15_Set (1UL)

Enable channel on write.

Definition at line 4125 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH1_Disabled

#define PPI_CHENSET_CH1_Disabled (0UL)

Channel disabled.

Definition at line 4221 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH1_Enabled

#define PPI_CHENSET_CH1_Enabled (1UL)

Channel enabled.

Definition at line 4222 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH1_Msk

#define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos)

Bit mask of CH1 field.

Definition at line 4220 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH1_Pos

#define PPI_CHENSET_CH1_Pos (1UL)

Position of CH1 field.

Definition at line 4219 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH1_Set

#define PPI_CHENSET_CH1_Set (1UL)

Enable channel on write.

Definition at line 4223 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH20_Disabled

#define PPI_CHENSET_CH20_Disabled (0UL)

Channel disabled.

Definition at line 4116 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH20_Enabled

#define PPI_CHENSET_CH20_Enabled (1UL)

Channel enabled.

Definition at line 4117 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH20_Msk

#define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos)

Bit mask of CH20 field.

Definition at line 4115 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH20_Pos

#define PPI_CHENSET_CH20_Pos (20UL)

Position of CH20 field.

Definition at line 4114 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH20_Set

#define PPI_CHENSET_CH20_Set (1UL)

Enable channel on write.

Definition at line 4118 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH21_Disabled

#define PPI_CHENSET_CH21_Disabled (0UL)

Channel disabled.

Definition at line 4109 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH21_Enabled

#define PPI_CHENSET_CH21_Enabled (1UL)

Channel enabled.

Definition at line 4110 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH21_Msk

#define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos)

Bit mask of CH21 field.

Definition at line 4108 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH21_Pos

#define PPI_CHENSET_CH21_Pos (21UL)

Position of CH21 field.

Definition at line 4107 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH21_Set

#define PPI_CHENSET_CH21_Set (1UL)

Enable channel on write.

Definition at line 4111 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH22_Disabled

#define PPI_CHENSET_CH22_Disabled (0UL)

Channel disabled.

Definition at line 4102 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH22_Enabled

#define PPI_CHENSET_CH22_Enabled (1UL)

Channel enabled.

Definition at line 4103 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH22_Msk

#define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos)

Bit mask of CH22 field.

Definition at line 4101 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH22_Pos

#define PPI_CHENSET_CH22_Pos (22UL)

Position of CH22 field.

Definition at line 4100 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH22_Set

#define PPI_CHENSET_CH22_Set (1UL)

Enable channel on write.

Definition at line 4104 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH23_Disabled

#define PPI_CHENSET_CH23_Disabled (0UL)

Channel disabled.

Definition at line 4095 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH23_Enabled

#define PPI_CHENSET_CH23_Enabled (1UL)

Channel enabled.

Definition at line 4096 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH23_Msk

#define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos)

Bit mask of CH23 field.

Definition at line 4094 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH23_Pos

#define PPI_CHENSET_CH23_Pos (23UL)

Position of CH23 field.

Definition at line 4093 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH23_Set

#define PPI_CHENSET_CH23_Set (1UL)

Enable channel on write.

Definition at line 4097 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH24_Disabled

#define PPI_CHENSET_CH24_Disabled (0UL)

Channel disabled.

Definition at line 4088 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH24_Enabled

#define PPI_CHENSET_CH24_Enabled (1UL)

Channel enabled.

Definition at line 4089 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH24_Msk

#define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos)

Bit mask of CH24 field.

Definition at line 4087 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH24_Pos

#define PPI_CHENSET_CH24_Pos (24UL)

Position of CH24 field.

Definition at line 4086 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH24_Set

#define PPI_CHENSET_CH24_Set (1UL)

Enable channel on write.

Definition at line 4090 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH25_Disabled

#define PPI_CHENSET_CH25_Disabled (0UL)

Channel disabled.

Definition at line 4081 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH25_Enabled

#define PPI_CHENSET_CH25_Enabled (1UL)

Channel enabled.

Definition at line 4082 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH25_Msk

#define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos)

Bit mask of CH25 field.

Definition at line 4080 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH25_Pos

#define PPI_CHENSET_CH25_Pos (25UL)

Position of CH25 field.

Definition at line 4079 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH25_Set

#define PPI_CHENSET_CH25_Set (1UL)

Enable channel on write.

Definition at line 4083 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH26_Disabled

#define PPI_CHENSET_CH26_Disabled (0UL)

Channel disabled.

Definition at line 4074 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH26_Enabled

#define PPI_CHENSET_CH26_Enabled (1UL)

Channel enabled.

Definition at line 4075 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH26_Msk

#define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos)

Bit mask of CH26 field.

Definition at line 4073 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH26_Pos

#define PPI_CHENSET_CH26_Pos (26UL)

Position of CH26 field.

Definition at line 4072 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH26_Set

#define PPI_CHENSET_CH26_Set (1UL)

Enable channel on write.

Definition at line 4076 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH27_Disabled

#define PPI_CHENSET_CH27_Disabled (0UL)

Channel disabled.

Definition at line 4067 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH27_Enabled

#define PPI_CHENSET_CH27_Enabled (1UL)

Channel enabled.

Definition at line 4068 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH27_Msk

#define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos)

Bit mask of CH27 field.

Definition at line 4066 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH27_Pos

#define PPI_CHENSET_CH27_Pos (27UL)

Position of CH27 field.

Definition at line 4065 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH27_Set

#define PPI_CHENSET_CH27_Set (1UL)

Enable channel on write.

Definition at line 4069 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH28_Disabled

#define PPI_CHENSET_CH28_Disabled (0UL)

Channel disabled.

Definition at line 4060 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH28_Enabled

#define PPI_CHENSET_CH28_Enabled (1UL)

Channel enabled.

Definition at line 4061 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH28_Msk

#define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos)

Bit mask of CH28 field.

Definition at line 4059 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH28_Pos

#define PPI_CHENSET_CH28_Pos (28UL)

Position of CH28 field.

Definition at line 4058 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH28_Set

#define PPI_CHENSET_CH28_Set (1UL)

Enable channel on write.

Definition at line 4062 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH29_Disabled

#define PPI_CHENSET_CH29_Disabled (0UL)

Channel disabled.

Definition at line 4053 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH29_Enabled

#define PPI_CHENSET_CH29_Enabled (1UL)

Channel enabled.

Definition at line 4054 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH29_Msk

#define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos)

Bit mask of CH29 field.

Definition at line 4052 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH29_Pos

#define PPI_CHENSET_CH29_Pos (29UL)

Position of CH29 field.

Definition at line 4051 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH29_Set

#define PPI_CHENSET_CH29_Set (1UL)

Enable channel on write.

Definition at line 4055 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH2_Disabled

#define PPI_CHENSET_CH2_Disabled (0UL)

Channel disabled.

Definition at line 4214 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH2_Enabled

#define PPI_CHENSET_CH2_Enabled (1UL)

Channel enabled.

Definition at line 4215 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH2_Msk

#define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos)

Bit mask of CH2 field.

Definition at line 4213 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH2_Pos

#define PPI_CHENSET_CH2_Pos (2UL)

Position of CH2 field.

Definition at line 4212 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH2_Set

#define PPI_CHENSET_CH2_Set (1UL)

Enable channel on write.

Definition at line 4216 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH30_Disabled

#define PPI_CHENSET_CH30_Disabled (0UL)

Channel disabled.

Definition at line 4046 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH30_Enabled

#define PPI_CHENSET_CH30_Enabled (1UL)

Channel enabled.

Definition at line 4047 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH30_Msk

#define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos)

Bit mask of CH30 field.

Definition at line 4045 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH30_Pos

#define PPI_CHENSET_CH30_Pos (30UL)

Position of CH30 field.

Definition at line 4044 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH30_Set

#define PPI_CHENSET_CH30_Set (1UL)

Enable channel on write.

Definition at line 4048 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH31_Disabled

#define PPI_CHENSET_CH31_Disabled (0UL)

Channel disabled.

Definition at line 4039 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH31_Enabled

#define PPI_CHENSET_CH31_Enabled (1UL)

Channel enabled.

Definition at line 4040 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH31_Msk

#define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos)

Bit mask of CH31 field.

Definition at line 4038 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH31_Pos

#define PPI_CHENSET_CH31_Pos (31UL)

Position of CH31 field.

Definition at line 4037 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH31_Set

#define PPI_CHENSET_CH31_Set (1UL)

Enable channel on write.

Definition at line 4041 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH3_Disabled

#define PPI_CHENSET_CH3_Disabled (0UL)

Channel disabled.

Definition at line 4207 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH3_Enabled

#define PPI_CHENSET_CH3_Enabled (1UL)

Channel enabled.

Definition at line 4208 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH3_Msk

#define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos)

Bit mask of CH3 field.

Definition at line 4206 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH3_Pos

#define PPI_CHENSET_CH3_Pos (3UL)

Position of CH3 field.

Definition at line 4205 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH3_Set

#define PPI_CHENSET_CH3_Set (1UL)

Enable channel on write.

Definition at line 4209 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH4_Disabled

#define PPI_CHENSET_CH4_Disabled (0UL)

Channel disabled.

Definition at line 4200 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH4_Enabled

#define PPI_CHENSET_CH4_Enabled (1UL)

Channel enabled.

Definition at line 4201 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH4_Msk

#define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos)

Bit mask of CH4 field.

Definition at line 4199 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH4_Pos

#define PPI_CHENSET_CH4_Pos (4UL)

Position of CH4 field.

Definition at line 4198 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH4_Set

#define PPI_CHENSET_CH4_Set (1UL)

Enable channel on write.

Definition at line 4202 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH5_Disabled

#define PPI_CHENSET_CH5_Disabled (0UL)

Channel disabled.

Definition at line 4193 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH5_Enabled

#define PPI_CHENSET_CH5_Enabled (1UL)

Channel enabled.

Definition at line 4194 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH5_Msk

#define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos)

Bit mask of CH5 field.

Definition at line 4192 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH5_Pos

#define PPI_CHENSET_CH5_Pos (5UL)

Position of CH5 field.

Definition at line 4191 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH5_Set

#define PPI_CHENSET_CH5_Set (1UL)

Enable channel on write.

Definition at line 4195 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH6_Disabled

#define PPI_CHENSET_CH6_Disabled (0UL)

Channel disabled.

Definition at line 4186 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH6_Enabled

#define PPI_CHENSET_CH6_Enabled (1UL)

Channel enabled.

Definition at line 4187 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH6_Msk

#define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos)

Bit mask of CH6 field.

Definition at line 4185 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH6_Pos

#define PPI_CHENSET_CH6_Pos (6UL)

Position of CH6 field.

Definition at line 4184 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH6_Set

#define PPI_CHENSET_CH6_Set (1UL)

Enable channel on write.

Definition at line 4188 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH7_Disabled

#define PPI_CHENSET_CH7_Disabled (0UL)

Channel disabled.

Definition at line 4179 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH7_Enabled

#define PPI_CHENSET_CH7_Enabled (1UL)

Channel enabled.

Definition at line 4180 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH7_Msk

#define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos)

Bit mask of CH7 field.

Definition at line 4178 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH7_Pos

#define PPI_CHENSET_CH7_Pos (7UL)

Position of CH7 field.

Definition at line 4177 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH7_Set

#define PPI_CHENSET_CH7_Set (1UL)

Enable channel on write.

Definition at line 4181 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH8_Disabled

#define PPI_CHENSET_CH8_Disabled (0UL)

Channel disabled.

Definition at line 4172 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH8_Enabled

#define PPI_CHENSET_CH8_Enabled (1UL)

Channel enabled.

Definition at line 4173 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH8_Msk

#define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos)

Bit mask of CH8 field.

Definition at line 4171 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH8_Pos

#define PPI_CHENSET_CH8_Pos (8UL)

Position of CH8 field.

Definition at line 4170 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH8_Set

#define PPI_CHENSET_CH8_Set (1UL)

Enable channel on write.

Definition at line 4174 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH9_Disabled

#define PPI_CHENSET_CH9_Disabled (0UL)

Channel disabled.

Definition at line 4165 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH9_Enabled

#define PPI_CHENSET_CH9_Enabled (1UL)

Channel enabled.

Definition at line 4166 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH9_Msk

#define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos)

Bit mask of CH9 field.

Definition at line 4164 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH9_Pos

#define PPI_CHENSET_CH9_Pos (9UL)

Position of CH9 field.

Definition at line 4163 of file nrf51_bitfields.h.

◆ PPI_CHENSET_CH9_Set

#define PPI_CHENSET_CH9_Set (1UL)

Enable channel on write.

Definition at line 4167 of file nrf51_bitfields.h.

◆ PPI_CHG_CH0_Excluded

#define PPI_CHG_CH0_Excluded (0UL)

Channel excluded.

Definition at line 4599 of file nrf51_bitfields.h.

◆ PPI_CHG_CH0_Included

#define PPI_CHG_CH0_Included (1UL)

Channel included.

Definition at line 4600 of file nrf51_bitfields.h.

◆ PPI_CHG_CH0_Msk

#define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos)

Bit mask of CH0 field.

Definition at line 4598 of file nrf51_bitfields.h.

◆ PPI_CHG_CH0_Pos

#define PPI_CHG_CH0_Pos (0UL)

Position of CH0 field.

Definition at line 4597 of file nrf51_bitfields.h.

◆ PPI_CHG_CH10_Excluded

#define PPI_CHG_CH10_Excluded (0UL)

Channel excluded.

Definition at line 4539 of file nrf51_bitfields.h.

◆ PPI_CHG_CH10_Included

#define PPI_CHG_CH10_Included (1UL)

Channel included.

Definition at line 4540 of file nrf51_bitfields.h.

◆ PPI_CHG_CH10_Msk

#define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos)

Bit mask of CH10 field.

Definition at line 4538 of file nrf51_bitfields.h.

◆ PPI_CHG_CH10_Pos

#define PPI_CHG_CH10_Pos (10UL)

Position of CH10 field.

Definition at line 4537 of file nrf51_bitfields.h.

◆ PPI_CHG_CH11_Excluded

#define PPI_CHG_CH11_Excluded (0UL)

Channel excluded.

Definition at line 4533 of file nrf51_bitfields.h.

◆ PPI_CHG_CH11_Included

#define PPI_CHG_CH11_Included (1UL)

Channel included.

Definition at line 4534 of file nrf51_bitfields.h.

◆ PPI_CHG_CH11_Msk

#define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos)

Bit mask of CH11 field.

Definition at line 4532 of file nrf51_bitfields.h.

◆ PPI_CHG_CH11_Pos

#define PPI_CHG_CH11_Pos (11UL)

Position of CH11 field.

Definition at line 4531 of file nrf51_bitfields.h.

◆ PPI_CHG_CH12_Excluded

#define PPI_CHG_CH12_Excluded (0UL)

Channel excluded.

Definition at line 4527 of file nrf51_bitfields.h.

◆ PPI_CHG_CH12_Included

#define PPI_CHG_CH12_Included (1UL)

Channel included.

Definition at line 4528 of file nrf51_bitfields.h.

◆ PPI_CHG_CH12_Msk

#define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos)

Bit mask of CH12 field.

Definition at line 4526 of file nrf51_bitfields.h.

◆ PPI_CHG_CH12_Pos

#define PPI_CHG_CH12_Pos (12UL)

Position of CH12 field.

Definition at line 4525 of file nrf51_bitfields.h.

◆ PPI_CHG_CH13_Excluded

#define PPI_CHG_CH13_Excluded (0UL)

Channel excluded.

Definition at line 4521 of file nrf51_bitfields.h.

◆ PPI_CHG_CH13_Included

#define PPI_CHG_CH13_Included (1UL)

Channel included.

Definition at line 4522 of file nrf51_bitfields.h.

◆ PPI_CHG_CH13_Msk

#define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos)

Bit mask of CH13 field.

Definition at line 4520 of file nrf51_bitfields.h.

◆ PPI_CHG_CH13_Pos

#define PPI_CHG_CH13_Pos (13UL)

Position of CH13 field.

Definition at line 4519 of file nrf51_bitfields.h.

◆ PPI_CHG_CH14_Excluded

#define PPI_CHG_CH14_Excluded (0UL)

Channel excluded.

Definition at line 4515 of file nrf51_bitfields.h.

◆ PPI_CHG_CH14_Included

#define PPI_CHG_CH14_Included (1UL)

Channel included.

Definition at line 4516 of file nrf51_bitfields.h.

◆ PPI_CHG_CH14_Msk

#define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos)

Bit mask of CH14 field.

Definition at line 4514 of file nrf51_bitfields.h.

◆ PPI_CHG_CH14_Pos

#define PPI_CHG_CH14_Pos (14UL)

Position of CH14 field.

Definition at line 4513 of file nrf51_bitfields.h.

◆ PPI_CHG_CH15_Excluded

#define PPI_CHG_CH15_Excluded (0UL)

Channel excluded.

Definition at line 4509 of file nrf51_bitfields.h.

◆ PPI_CHG_CH15_Included

#define PPI_CHG_CH15_Included (1UL)

Channel included.

Definition at line 4510 of file nrf51_bitfields.h.

◆ PPI_CHG_CH15_Msk

#define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos)

Bit mask of CH15 field.

Definition at line 4508 of file nrf51_bitfields.h.

◆ PPI_CHG_CH15_Pos

#define PPI_CHG_CH15_Pos (15UL)

Position of CH15 field.

Definition at line 4507 of file nrf51_bitfields.h.

◆ PPI_CHG_CH1_Excluded

#define PPI_CHG_CH1_Excluded (0UL)

Channel excluded.

Definition at line 4593 of file nrf51_bitfields.h.

◆ PPI_CHG_CH1_Included

#define PPI_CHG_CH1_Included (1UL)

Channel included.

Definition at line 4594 of file nrf51_bitfields.h.

◆ PPI_CHG_CH1_Msk

#define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos)

Bit mask of CH1 field.

Definition at line 4592 of file nrf51_bitfields.h.

◆ PPI_CHG_CH1_Pos

#define PPI_CHG_CH1_Pos (1UL)

Position of CH1 field.

Definition at line 4591 of file nrf51_bitfields.h.

◆ PPI_CHG_CH20_Excluded

#define PPI_CHG_CH20_Excluded (0UL)

Channel excluded.

Definition at line 4503 of file nrf51_bitfields.h.

◆ PPI_CHG_CH20_Included

#define PPI_CHG_CH20_Included (1UL)

Channel included.

Definition at line 4504 of file nrf51_bitfields.h.

◆ PPI_CHG_CH20_Msk

#define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos)

Bit mask of CH20 field.

Definition at line 4502 of file nrf51_bitfields.h.

◆ PPI_CHG_CH20_Pos

#define PPI_CHG_CH20_Pos (20UL)

Position of CH20 field.

Definition at line 4501 of file nrf51_bitfields.h.

◆ PPI_CHG_CH21_Excluded

#define PPI_CHG_CH21_Excluded (0UL)

Channel excluded.

Definition at line 4497 of file nrf51_bitfields.h.

◆ PPI_CHG_CH21_Included

#define PPI_CHG_CH21_Included (1UL)

Channel included.

Definition at line 4498 of file nrf51_bitfields.h.

◆ PPI_CHG_CH21_Msk

#define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos)

Bit mask of CH21 field.

Definition at line 4496 of file nrf51_bitfields.h.

◆ PPI_CHG_CH21_Pos

#define PPI_CHG_CH21_Pos (21UL)

Position of CH21 field.

Definition at line 4495 of file nrf51_bitfields.h.

◆ PPI_CHG_CH22_Excluded

#define PPI_CHG_CH22_Excluded (0UL)

Channel excluded.

Definition at line 4491 of file nrf51_bitfields.h.

◆ PPI_CHG_CH22_Included

#define PPI_CHG_CH22_Included (1UL)

Channel included.

Definition at line 4492 of file nrf51_bitfields.h.

◆ PPI_CHG_CH22_Msk

#define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos)

Bit mask of CH22 field.

Definition at line 4490 of file nrf51_bitfields.h.

◆ PPI_CHG_CH22_Pos

#define PPI_CHG_CH22_Pos (22UL)

Position of CH22 field.

Definition at line 4489 of file nrf51_bitfields.h.

◆ PPI_CHG_CH23_Excluded

#define PPI_CHG_CH23_Excluded (0UL)

Channel excluded.

Definition at line 4485 of file nrf51_bitfields.h.

◆ PPI_CHG_CH23_Included

#define PPI_CHG_CH23_Included (1UL)

Channel included.

Definition at line 4486 of file nrf51_bitfields.h.

◆ PPI_CHG_CH23_Msk

#define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos)

Bit mask of CH23 field.

Definition at line 4484 of file nrf51_bitfields.h.

◆ PPI_CHG_CH23_Pos

#define PPI_CHG_CH23_Pos (23UL)

Position of CH23 field.

Definition at line 4483 of file nrf51_bitfields.h.

◆ PPI_CHG_CH24_Excluded

#define PPI_CHG_CH24_Excluded (0UL)

Channel excluded.

Definition at line 4479 of file nrf51_bitfields.h.

◆ PPI_CHG_CH24_Included

#define PPI_CHG_CH24_Included (1UL)

Channel included.

Definition at line 4480 of file nrf51_bitfields.h.

◆ PPI_CHG_CH24_Msk

#define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos)

Bit mask of CH24 field.

Definition at line 4478 of file nrf51_bitfields.h.

◆ PPI_CHG_CH24_Pos

#define PPI_CHG_CH24_Pos (24UL)

Position of CH24 field.

Definition at line 4477 of file nrf51_bitfields.h.

◆ PPI_CHG_CH25_Excluded

#define PPI_CHG_CH25_Excluded (0UL)

Channel excluded.

Definition at line 4473 of file nrf51_bitfields.h.

◆ PPI_CHG_CH25_Included

#define PPI_CHG_CH25_Included (1UL)

Channel included.

Definition at line 4474 of file nrf51_bitfields.h.

◆ PPI_CHG_CH25_Msk

#define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos)

Bit mask of CH25 field.

Definition at line 4472 of file nrf51_bitfields.h.

◆ PPI_CHG_CH25_Pos

#define PPI_CHG_CH25_Pos (25UL)

Position of CH25 field.

Definition at line 4471 of file nrf51_bitfields.h.

◆ PPI_CHG_CH26_Excluded

#define PPI_CHG_CH26_Excluded (0UL)

Channel excluded.

Definition at line 4467 of file nrf51_bitfields.h.

◆ PPI_CHG_CH26_Included

#define PPI_CHG_CH26_Included (1UL)

Channel included.

Definition at line 4468 of file nrf51_bitfields.h.

◆ PPI_CHG_CH26_Msk

#define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos)

Bit mask of CH26 field.

Definition at line 4466 of file nrf51_bitfields.h.

◆ PPI_CHG_CH26_Pos

#define PPI_CHG_CH26_Pos (26UL)

Position of CH26 field.

Definition at line 4465 of file nrf51_bitfields.h.

◆ PPI_CHG_CH27_Excluded

#define PPI_CHG_CH27_Excluded (0UL)

Channel excluded.

Definition at line 4461 of file nrf51_bitfields.h.

◆ PPI_CHG_CH27_Included

#define PPI_CHG_CH27_Included (1UL)

Channel included.

Definition at line 4462 of file nrf51_bitfields.h.

◆ PPI_CHG_CH27_Msk

#define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos)

Bit mask of CH27 field.

Definition at line 4460 of file nrf51_bitfields.h.

◆ PPI_CHG_CH27_Pos

#define PPI_CHG_CH27_Pos (27UL)

Position of CH27 field.

Definition at line 4459 of file nrf51_bitfields.h.

◆ PPI_CHG_CH28_Excluded

#define PPI_CHG_CH28_Excluded (0UL)

Channel excluded.

Definition at line 4455 of file nrf51_bitfields.h.

◆ PPI_CHG_CH28_Included

#define PPI_CHG_CH28_Included (1UL)

Channel included.

Definition at line 4456 of file nrf51_bitfields.h.

◆ PPI_CHG_CH28_Msk

#define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos)

Bit mask of CH28 field.

Definition at line 4454 of file nrf51_bitfields.h.

◆ PPI_CHG_CH28_Pos

#define PPI_CHG_CH28_Pos (28UL)

Position of CH28 field.

Definition at line 4453 of file nrf51_bitfields.h.

◆ PPI_CHG_CH29_Excluded

#define PPI_CHG_CH29_Excluded (0UL)

Channel excluded.

Definition at line 4449 of file nrf51_bitfields.h.

◆ PPI_CHG_CH29_Included

#define PPI_CHG_CH29_Included (1UL)

Channel included.

Definition at line 4450 of file nrf51_bitfields.h.

◆ PPI_CHG_CH29_Msk

#define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos)

Bit mask of CH29 field.

Definition at line 4448 of file nrf51_bitfields.h.

◆ PPI_CHG_CH29_Pos

#define PPI_CHG_CH29_Pos (29UL)

Position of CH29 field.

Definition at line 4447 of file nrf51_bitfields.h.

◆ PPI_CHG_CH2_Excluded

#define PPI_CHG_CH2_Excluded (0UL)

Channel excluded.

Definition at line 4587 of file nrf51_bitfields.h.

◆ PPI_CHG_CH2_Included

#define PPI_CHG_CH2_Included (1UL)

Channel included.

Definition at line 4588 of file nrf51_bitfields.h.

◆ PPI_CHG_CH2_Msk

#define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos)

Bit mask of CH2 field.

Definition at line 4586 of file nrf51_bitfields.h.

◆ PPI_CHG_CH2_Pos

#define PPI_CHG_CH2_Pos (2UL)

Position of CH2 field.

Definition at line 4585 of file nrf51_bitfields.h.

◆ PPI_CHG_CH30_Excluded

#define PPI_CHG_CH30_Excluded (0UL)

Channel excluded.

Definition at line 4443 of file nrf51_bitfields.h.

◆ PPI_CHG_CH30_Included

#define PPI_CHG_CH30_Included (1UL)

Channel included.

Definition at line 4444 of file nrf51_bitfields.h.

◆ PPI_CHG_CH30_Msk

#define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos)

Bit mask of CH30 field.

Definition at line 4442 of file nrf51_bitfields.h.

◆ PPI_CHG_CH30_Pos

#define PPI_CHG_CH30_Pos (30UL)

Position of CH30 field.

Definition at line 4441 of file nrf51_bitfields.h.

◆ PPI_CHG_CH31_Excluded

#define PPI_CHG_CH31_Excluded (0UL)

Channel excluded.

Definition at line 4437 of file nrf51_bitfields.h.

◆ PPI_CHG_CH31_Included

#define PPI_CHG_CH31_Included (1UL)

Channel included.

Definition at line 4438 of file nrf51_bitfields.h.

◆ PPI_CHG_CH31_Msk

#define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos)

Bit mask of CH31 field.

Definition at line 4436 of file nrf51_bitfields.h.

◆ PPI_CHG_CH31_Pos

#define PPI_CHG_CH31_Pos (31UL)

Position of CH31 field.

Definition at line 4435 of file nrf51_bitfields.h.

◆ PPI_CHG_CH3_Excluded

#define PPI_CHG_CH3_Excluded (0UL)

Channel excluded.

Definition at line 4581 of file nrf51_bitfields.h.

◆ PPI_CHG_CH3_Included

#define PPI_CHG_CH3_Included (1UL)

Channel included.

Definition at line 4582 of file nrf51_bitfields.h.

◆ PPI_CHG_CH3_Msk

#define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos)

Bit mask of CH3 field.

Definition at line 4580 of file nrf51_bitfields.h.

◆ PPI_CHG_CH3_Pos

#define PPI_CHG_CH3_Pos (3UL)

Position of CH3 field.

Definition at line 4579 of file nrf51_bitfields.h.

◆ PPI_CHG_CH4_Excluded

#define PPI_CHG_CH4_Excluded (0UL)

Channel excluded.

Definition at line 4575 of file nrf51_bitfields.h.

◆ PPI_CHG_CH4_Included

#define PPI_CHG_CH4_Included (1UL)

Channel included.

Definition at line 4576 of file nrf51_bitfields.h.

◆ PPI_CHG_CH4_Msk

#define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos)

Bit mask of CH4 field.

Definition at line 4574 of file nrf51_bitfields.h.

◆ PPI_CHG_CH4_Pos

#define PPI_CHG_CH4_Pos (4UL)

Position of CH4 field.

Definition at line 4573 of file nrf51_bitfields.h.

◆ PPI_CHG_CH5_Excluded

#define PPI_CHG_CH5_Excluded (0UL)

Channel excluded.

Definition at line 4569 of file nrf51_bitfields.h.

◆ PPI_CHG_CH5_Included

#define PPI_CHG_CH5_Included (1UL)

Channel included.

Definition at line 4570 of file nrf51_bitfields.h.

◆ PPI_CHG_CH5_Msk

#define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos)

Bit mask of CH5 field.

Definition at line 4568 of file nrf51_bitfields.h.

◆ PPI_CHG_CH5_Pos

#define PPI_CHG_CH5_Pos (5UL)

Position of CH5 field.

Definition at line 4567 of file nrf51_bitfields.h.

◆ PPI_CHG_CH6_Excluded

#define PPI_CHG_CH6_Excluded (0UL)

Channel excluded.

Definition at line 4563 of file nrf51_bitfields.h.

◆ PPI_CHG_CH6_Included

#define PPI_CHG_CH6_Included (1UL)

Channel included.

Definition at line 4564 of file nrf51_bitfields.h.

◆ PPI_CHG_CH6_Msk

#define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos)

Bit mask of CH6 field.

Definition at line 4562 of file nrf51_bitfields.h.

◆ PPI_CHG_CH6_Pos

#define PPI_CHG_CH6_Pos (6UL)

Position of CH6 field.

Definition at line 4561 of file nrf51_bitfields.h.

◆ PPI_CHG_CH7_Excluded

#define PPI_CHG_CH7_Excluded (0UL)

Channel excluded.

Definition at line 4557 of file nrf51_bitfields.h.

◆ PPI_CHG_CH7_Included

#define PPI_CHG_CH7_Included (1UL)

Channel included.

Definition at line 4558 of file nrf51_bitfields.h.

◆ PPI_CHG_CH7_Msk

#define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos)

Bit mask of CH7 field.

Definition at line 4556 of file nrf51_bitfields.h.

◆ PPI_CHG_CH7_Pos

#define PPI_CHG_CH7_Pos (7UL)

Position of CH7 field.

Definition at line 4555 of file nrf51_bitfields.h.

◆ PPI_CHG_CH8_Excluded

#define PPI_CHG_CH8_Excluded (0UL)

Channel excluded.

Definition at line 4551 of file nrf51_bitfields.h.

◆ PPI_CHG_CH8_Included

#define PPI_CHG_CH8_Included (1UL)

Channel included.

Definition at line 4552 of file nrf51_bitfields.h.

◆ PPI_CHG_CH8_Msk

#define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos)

Bit mask of CH8 field.

Definition at line 4550 of file nrf51_bitfields.h.

◆ PPI_CHG_CH8_Pos

#define PPI_CHG_CH8_Pos (8UL)

Position of CH8 field.

Definition at line 4549 of file nrf51_bitfields.h.

◆ PPI_CHG_CH9_Excluded

#define PPI_CHG_CH9_Excluded (0UL)

Channel excluded.

Definition at line 4545 of file nrf51_bitfields.h.

◆ PPI_CHG_CH9_Included

#define PPI_CHG_CH9_Included (1UL)

Channel included.

Definition at line 4546 of file nrf51_bitfields.h.

◆ PPI_CHG_CH9_Msk

#define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos)

Bit mask of CH9 field.

Definition at line 4544 of file nrf51_bitfields.h.

◆ PPI_CHG_CH9_Pos

#define PPI_CHG_CH9_Pos (9UL)

Position of CH9 field.

Definition at line 4543 of file nrf51_bitfields.h.

◆ PU_PATCHADDR_PATCHADDR_Msk

#define PU_PATCHADDR_PATCHADDR_Msk (0x1FFFFFFUL << PU_PATCHADDR_PATCHADDR_Pos)

Bit mask of PATCHADDR field.

Definition at line 4611 of file nrf51_bitfields.h.

◆ PU_PATCHADDR_PATCHADDR_Pos

#define PU_PATCHADDR_PATCHADDR_Pos (0UL)

Position of PATCHADDR field.

Definition at line 4610 of file nrf51_bitfields.h.

◆ PU_PATCHEN_PATCH0_Disabled

#define PU_PATCHEN_PATCH0_Disabled (0UL)

Patch disabled.

Definition at line 4661 of file nrf51_bitfields.h.

◆ PU_PATCHEN_PATCH0_Enabled

#define PU_PATCHEN_PATCH0_Enabled (1UL)

Patch enabled.

Definition at line 4662 of file nrf51_bitfields.h.

◆ PU_PATCHEN_PATCH0_Msk

#define PU_PATCHEN_PATCH0_Msk (0x1UL << PU_PATCHEN_PATCH0_Pos)

Bit mask of PATCH0 field.

Definition at line 4660 of file nrf51_bitfields.h.

◆ PU_PATCHEN_PATCH0_Pos

#define PU_PATCHEN_PATCH0_Pos (0UL)

Position of PATCH0 field.

Definition at line 4659 of file nrf51_bitfields.h.

◆ PU_PATCHEN_PATCH1_Disabled

#define PU_PATCHEN_PATCH1_Disabled (0UL)

Patch disabled.

Definition at line 4655 of file nrf51_bitfields.h.

◆ PU_PATCHEN_PATCH1_Enabled

#define PU_PATCHEN_PATCH1_Enabled (1UL)

Patch enabled.

Definition at line 4656 of file nrf51_bitfields.h.

◆ PU_PATCHEN_PATCH1_Msk

#define PU_PATCHEN_PATCH1_Msk (0x1UL << PU_PATCHEN_PATCH1_Pos)

Bit mask of PATCH1 field.

Definition at line 4654 of file nrf51_bitfields.h.

◆ PU_PATCHEN_PATCH1_Pos

#define PU_PATCHEN_PATCH1_Pos (1UL)

Position of PATCH1 field.

Definition at line 4653 of file nrf51_bitfields.h.

◆ PU_PATCHEN_PATCH2_Disabled

#define PU_PATCHEN_PATCH2_Disabled (0UL)

Patch disabled.

Definition at line 4649 of file nrf51_bitfields.h.

◆ PU_PATCHEN_PATCH2_Enabled

#define PU_PATCHEN_PATCH2_Enabled (1UL)

Patch enabled.

Definition at line 4650 of file nrf51_bitfields.h.

◆ PU_PATCHEN_PATCH2_Msk

#define PU_PATCHEN_PATCH2_Msk (0x1UL << PU_PATCHEN_PATCH2_Pos)

Bit mask of PATCH2 field.

Definition at line 4648 of file nrf51_bitfields.h.

◆ PU_PATCHEN_PATCH2_Pos

#define PU_PATCHEN_PATCH2_Pos (2UL)

Position of PATCH2 field.

Definition at line 4647 of file nrf51_bitfields.h.

◆ PU_PATCHEN_PATCH3_Disabled

#define PU_PATCHEN_PATCH3_Disabled (0UL)

Patch disabled.

Definition at line 4643 of file nrf51_bitfields.h.

◆ PU_PATCHEN_PATCH3_Enabled

#define PU_PATCHEN_PATCH3_Enabled (1UL)

Patch enabled.

Definition at line 4644 of file nrf51_bitfields.h.

◆ PU_PATCHEN_PATCH3_Msk

#define PU_PATCHEN_PATCH3_Msk (0x1UL << PU_PATCHEN_PATCH3_Pos)

Bit mask of PATCH3 field.

Definition at line 4642 of file nrf51_bitfields.h.

◆ PU_PATCHEN_PATCH3_Pos

#define PU_PATCHEN_PATCH3_Pos (3UL)

Position of PATCH3 field.

Definition at line 4641 of file nrf51_bitfields.h.

◆ PU_PATCHEN_PATCH4_Disabled

#define PU_PATCHEN_PATCH4_Disabled (0UL)

Patch disabled.

Definition at line 4637 of file nrf51_bitfields.h.

◆ PU_PATCHEN_PATCH4_Enabled

#define PU_PATCHEN_PATCH4_Enabled (1UL)

Patch enabled.

Definition at line 4638 of file nrf51_bitfields.h.

◆ PU_PATCHEN_PATCH4_Msk

#define PU_PATCHEN_PATCH4_Msk (0x1UL << PU_PATCHEN_PATCH4_Pos)

Bit mask of PATCH4 field.

Definition at line 4636 of file nrf51_bitfields.h.

◆ PU_PATCHEN_PATCH4_Pos

#define PU_PATCHEN_PATCH4_Pos (4UL)

Position of PATCH4 field.

Definition at line 4635 of file nrf51_bitfields.h.

◆ PU_PATCHEN_PATCH5_Disabled

#define PU_PATCHEN_PATCH5_Disabled (0UL)

Patch disabled.

Definition at line 4631 of file nrf51_bitfields.h.

◆ PU_PATCHEN_PATCH5_Enabled

#define PU_PATCHEN_PATCH5_Enabled (1UL)

Patch enabled.

Definition at line 4632 of file nrf51_bitfields.h.

◆ PU_PATCHEN_PATCH5_Msk

#define PU_PATCHEN_PATCH5_Msk (0x1UL << PU_PATCHEN_PATCH5_Pos)

Bit mask of PATCH5 field.

Definition at line 4630 of file nrf51_bitfields.h.

◆ PU_PATCHEN_PATCH5_Pos

#define PU_PATCHEN_PATCH5_Pos (5UL)

Position of PATCH5 field.

Definition at line 4629 of file nrf51_bitfields.h.

◆ PU_PATCHEN_PATCH6_Disabled

#define PU_PATCHEN_PATCH6_Disabled (0UL)

Patch disabled.

Definition at line 4625 of file nrf51_bitfields.h.

◆ PU_PATCHEN_PATCH6_Enabled

#define PU_PATCHEN_PATCH6_Enabled (1UL)

Patch enabled.

Definition at line 4626 of file nrf51_bitfields.h.

◆ PU_PATCHEN_PATCH6_Msk

#define PU_PATCHEN_PATCH6_Msk (0x1UL << PU_PATCHEN_PATCH6_Pos)

Bit mask of PATCH6 field.

Definition at line 4624 of file nrf51_bitfields.h.

◆ PU_PATCHEN_PATCH6_Pos

#define PU_PATCHEN_PATCH6_Pos (6UL)

Position of PATCH6 field.

Definition at line 4623 of file nrf51_bitfields.h.

◆ PU_PATCHEN_PATCH7_Disabled

#define PU_PATCHEN_PATCH7_Disabled (0UL)

Patch disabled.

Definition at line 4619 of file nrf51_bitfields.h.

◆ PU_PATCHEN_PATCH7_Enabled

#define PU_PATCHEN_PATCH7_Enabled (1UL)

Patch enabled.

Definition at line 4620 of file nrf51_bitfields.h.

◆ PU_PATCHEN_PATCH7_Msk

#define PU_PATCHEN_PATCH7_Msk (0x1UL << PU_PATCHEN_PATCH7_Pos)

Bit mask of PATCH7 field.

Definition at line 4618 of file nrf51_bitfields.h.

◆ PU_PATCHEN_PATCH7_Pos

#define PU_PATCHEN_PATCH7_Pos (7UL)

Position of PATCH7 field.

Definition at line 4617 of file nrf51_bitfields.h.

◆ PU_PATCHENCLR_PATCH0_Clear

#define PU_PATCHENCLR_PATCH0_Clear (1UL)

Disable patch on write.

Definition at line 4780 of file nrf51_bitfields.h.

◆ PU_PATCHENCLR_PATCH0_Disabled

#define PU_PATCHENCLR_PATCH0_Disabled (0UL)

Patch disabled.

Definition at line 4778 of file nrf51_bitfields.h.

◆ PU_PATCHENCLR_PATCH0_Enabled

#define PU_PATCHENCLR_PATCH0_Enabled (1UL)

Patch enabled.

Definition at line 4779 of file nrf51_bitfields.h.

◆ PU_PATCHENCLR_PATCH0_Msk

#define PU_PATCHENCLR_PATCH0_Msk (0x1UL << PU_PATCHENCLR_PATCH0_Pos)

Bit mask of PATCH0 field.

Definition at line 4777 of file nrf51_bitfields.h.

◆ PU_PATCHENCLR_PATCH0_Pos

#define PU_PATCHENCLR_PATCH0_Pos (0UL)

Position of PATCH0 field.

Definition at line 4776 of file nrf51_bitfields.h.

◆ PU_PATCHENCLR_PATCH1_Clear

#define PU_PATCHENCLR_PATCH1_Clear (1UL)

Disable patch on write.

Definition at line 4773 of file nrf51_bitfields.h.

◆ PU_PATCHENCLR_PATCH1_Disabled

#define PU_PATCHENCLR_PATCH1_Disabled (0UL)

Patch disabled.

Definition at line 4771 of file nrf51_bitfields.h.

◆ PU_PATCHENCLR_PATCH1_Enabled

#define PU_PATCHENCLR_PATCH1_Enabled (1UL)

Patch enabled.

Definition at line 4772 of file nrf51_bitfields.h.

◆ PU_PATCHENCLR_PATCH1_Msk

#define PU_PATCHENCLR_PATCH1_Msk (0x1UL << PU_PATCHENCLR_PATCH1_Pos)

Bit mask of PATCH1 field.

Definition at line 4770 of file nrf51_bitfields.h.

◆ PU_PATCHENCLR_PATCH1_Pos

#define PU_PATCHENCLR_PATCH1_Pos (1UL)

Position of PATCH1 field.

Definition at line 4769 of file nrf51_bitfields.h.

◆ PU_PATCHENCLR_PATCH2_Clear

#define PU_PATCHENCLR_PATCH2_Clear (1UL)

Disable patch on write.

Definition at line 4766 of file nrf51_bitfields.h.

◆ PU_PATCHENCLR_PATCH2_Disabled

#define PU_PATCHENCLR_PATCH2_Disabled (0UL)

Patch disabled.

Definition at line 4764 of file nrf51_bitfields.h.

◆ PU_PATCHENCLR_PATCH2_Enabled

#define PU_PATCHENCLR_PATCH2_Enabled (1UL)

Patch enabled.

Definition at line 4765 of file nrf51_bitfields.h.

◆ PU_PATCHENCLR_PATCH2_Msk

#define PU_PATCHENCLR_PATCH2_Msk (0x1UL << PU_PATCHENCLR_PATCH2_Pos)

Bit mask of PATCH2 field.

Definition at line 4763 of file nrf51_bitfields.h.

◆ PU_PATCHENCLR_PATCH2_Pos

#define PU_PATCHENCLR_PATCH2_Pos (2UL)

Position of PATCH2 field.

Definition at line 4762 of file nrf51_bitfields.h.

◆ PU_PATCHENCLR_PATCH3_Clear

#define PU_PATCHENCLR_PATCH3_Clear (1UL)

Disable patch on write.

Definition at line 4759 of file nrf51_bitfields.h.

◆ PU_PATCHENCLR_PATCH3_Disabled

#define PU_PATCHENCLR_PATCH3_Disabled (0UL)

Patch disabled.

Definition at line 4757 of file nrf51_bitfields.h.

◆ PU_PATCHENCLR_PATCH3_Enabled

#define PU_PATCHENCLR_PATCH3_Enabled (1UL)

Patch enabled.

Definition at line 4758 of file nrf51_bitfields.h.

◆ PU_PATCHENCLR_PATCH3_Msk

#define PU_PATCHENCLR_PATCH3_Msk (0x1UL << PU_PATCHENCLR_PATCH3_Pos)

Bit mask of PATCH3 field.

Definition at line 4756 of file nrf51_bitfields.h.

◆ PU_PATCHENCLR_PATCH3_Pos

#define PU_PATCHENCLR_PATCH3_Pos (3UL)

Position of PATCH3 field.

Definition at line 4755 of file nrf51_bitfields.h.

◆ PU_PATCHENCLR_PATCH4_Clear

#define PU_PATCHENCLR_PATCH4_Clear (1UL)

Disable patch on write.

Definition at line 4752 of file nrf51_bitfields.h.

◆ PU_PATCHENCLR_PATCH4_Disabled

#define PU_PATCHENCLR_PATCH4_Disabled (0UL)

Patch disabled.

Definition at line 4750 of file nrf51_bitfields.h.

◆ PU_PATCHENCLR_PATCH4_Enabled

#define PU_PATCHENCLR_PATCH4_Enabled (1UL)

Patch enabled.

Definition at line 4751 of file nrf51_bitfields.h.

◆ PU_PATCHENCLR_PATCH4_Msk

#define PU_PATCHENCLR_PATCH4_Msk (0x1UL << PU_PATCHENCLR_PATCH4_Pos)

Bit mask of PATCH4 field.

Definition at line 4749 of file nrf51_bitfields.h.

◆ PU_PATCHENCLR_PATCH4_Pos

#define PU_PATCHENCLR_PATCH4_Pos (4UL)

Position of PATCH4 field.

Definition at line 4748 of file nrf51_bitfields.h.

◆ PU_PATCHENCLR_PATCH5_Clear

#define PU_PATCHENCLR_PATCH5_Clear (1UL)

Disable patch on write.

Definition at line 4745 of file nrf51_bitfields.h.

◆ PU_PATCHENCLR_PATCH5_Disabled

#define PU_PATCHENCLR_PATCH5_Disabled (0UL)

Patch disabled.

Definition at line 4743 of file nrf51_bitfields.h.

◆ PU_PATCHENCLR_PATCH5_Enabled

#define PU_PATCHENCLR_PATCH5_Enabled (1UL)

Patch enabled.

Definition at line 4744 of file nrf51_bitfields.h.

◆ PU_PATCHENCLR_PATCH5_Msk

#define PU_PATCHENCLR_PATCH5_Msk (0x1UL << PU_PATCHENCLR_PATCH5_Pos)

Bit mask of PATCH5 field.

Definition at line 4742 of file nrf51_bitfields.h.

◆ PU_PATCHENCLR_PATCH5_Pos

#define PU_PATCHENCLR_PATCH5_Pos (5UL)

Position of PATCH5 field.

Definition at line 4741 of file nrf51_bitfields.h.

◆ PU_PATCHENCLR_PATCH6_Clear

#define PU_PATCHENCLR_PATCH6_Clear (1UL)

Disable patch on write.

Definition at line 4738 of file nrf51_bitfields.h.

◆ PU_PATCHENCLR_PATCH6_Disabled

#define PU_PATCHENCLR_PATCH6_Disabled (0UL)

Patch disabled.

Definition at line 4736 of file nrf51_bitfields.h.

◆ PU_PATCHENCLR_PATCH6_Enabled

#define PU_PATCHENCLR_PATCH6_Enabled (1UL)

Patch enabled.

Definition at line 4737 of file nrf51_bitfields.h.

◆ PU_PATCHENCLR_PATCH6_Msk

#define PU_PATCHENCLR_PATCH6_Msk (0x1UL << PU_PATCHENCLR_PATCH6_Pos)

Bit mask of PATCH6 field.

Definition at line 4735 of file nrf51_bitfields.h.

◆ PU_PATCHENCLR_PATCH6_Pos

#define PU_PATCHENCLR_PATCH6_Pos (6UL)

Position of PATCH6 field.

Definition at line 4734 of file nrf51_bitfields.h.

◆ PU_PATCHENCLR_PATCH7_Clear

#define PU_PATCHENCLR_PATCH7_Clear (1UL)

Disable patch on write.

Definition at line 4731 of file nrf51_bitfields.h.

◆ PU_PATCHENCLR_PATCH7_Disabled

#define PU_PATCHENCLR_PATCH7_Disabled (0UL)

Patch disabled.

Definition at line 4729 of file nrf51_bitfields.h.

◆ PU_PATCHENCLR_PATCH7_Enabled

#define PU_PATCHENCLR_PATCH7_Enabled (1UL)

Patch enabled.

Definition at line 4730 of file nrf51_bitfields.h.

◆ PU_PATCHENCLR_PATCH7_Msk

#define PU_PATCHENCLR_PATCH7_Msk (0x1UL << PU_PATCHENCLR_PATCH7_Pos)

Bit mask of PATCH7 field.

Definition at line 4728 of file nrf51_bitfields.h.

◆ PU_PATCHENCLR_PATCH7_Pos

#define PU_PATCHENCLR_PATCH7_Pos (7UL)

Position of PATCH7 field.

Definition at line 4727 of file nrf51_bitfields.h.

◆ PU_PATCHENSET_PATCH0_Disabled

#define PU_PATCHENSET_PATCH0_Disabled (0UL)

Patch disabled.

Definition at line 4719 of file nrf51_bitfields.h.

◆ PU_PATCHENSET_PATCH0_Enabled

#define PU_PATCHENSET_PATCH0_Enabled (1UL)

Patch enabled.

Definition at line 4720 of file nrf51_bitfields.h.

◆ PU_PATCHENSET_PATCH0_Msk

#define PU_PATCHENSET_PATCH0_Msk (0x1UL << PU_PATCHENSET_PATCH0_Pos)

Bit mask of PATCH0 field.

Definition at line 4718 of file nrf51_bitfields.h.

◆ PU_PATCHENSET_PATCH0_Pos

#define PU_PATCHENSET_PATCH0_Pos (0UL)

Position of PATCH0 field.

Definition at line 4717 of file nrf51_bitfields.h.

◆ PU_PATCHENSET_PATCH0_Set

#define PU_PATCHENSET_PATCH0_Set (1UL)

Enable patch on write.

Definition at line 4721 of file nrf51_bitfields.h.

◆ PU_PATCHENSET_PATCH1_Disabled

#define PU_PATCHENSET_PATCH1_Disabled (0UL)

Patch disabled.

Definition at line 4712 of file nrf51_bitfields.h.

◆ PU_PATCHENSET_PATCH1_Enabled

#define PU_PATCHENSET_PATCH1_Enabled (1UL)

Patch enabled.

Definition at line 4713 of file nrf51_bitfields.h.

◆ PU_PATCHENSET_PATCH1_Msk

#define PU_PATCHENSET_PATCH1_Msk (0x1UL << PU_PATCHENSET_PATCH1_Pos)

Bit mask of PATCH1 field.

Definition at line 4711 of file nrf51_bitfields.h.

◆ PU_PATCHENSET_PATCH1_Pos

#define PU_PATCHENSET_PATCH1_Pos (1UL)

Position of PATCH1 field.

Definition at line 4710 of file nrf51_bitfields.h.

◆ PU_PATCHENSET_PATCH1_Set

#define PU_PATCHENSET_PATCH1_Set (1UL)

Enable patch on write.

Definition at line 4714 of file nrf51_bitfields.h.

◆ PU_PATCHENSET_PATCH2_Disabled

#define PU_PATCHENSET_PATCH2_Disabled (0UL)

Patch disabled.

Definition at line 4705 of file nrf51_bitfields.h.

◆ PU_PATCHENSET_PATCH2_Enabled

#define PU_PATCHENSET_PATCH2_Enabled (1UL)

Patch enabled.

Definition at line 4706 of file nrf51_bitfields.h.

◆ PU_PATCHENSET_PATCH2_Msk

#define PU_PATCHENSET_PATCH2_Msk (0x1UL << PU_PATCHENSET_PATCH2_Pos)

Bit mask of PATCH2 field.

Definition at line 4704 of file nrf51_bitfields.h.

◆ PU_PATCHENSET_PATCH2_Pos

#define PU_PATCHENSET_PATCH2_Pos (2UL)

Position of PATCH2 field.

Definition at line 4703 of file nrf51_bitfields.h.

◆ PU_PATCHENSET_PATCH2_Set

#define PU_PATCHENSET_PATCH2_Set (1UL)

Enable patch on write.

Definition at line 4707 of file nrf51_bitfields.h.

◆ PU_PATCHENSET_PATCH3_Disabled

#define PU_PATCHENSET_PATCH3_Disabled (0UL)

Patch disabled.

Definition at line 4698 of file nrf51_bitfields.h.

◆ PU_PATCHENSET_PATCH3_Enabled

#define PU_PATCHENSET_PATCH3_Enabled (1UL)

Patch enabled.

Definition at line 4699 of file nrf51_bitfields.h.

◆ PU_PATCHENSET_PATCH3_Msk

#define PU_PATCHENSET_PATCH3_Msk (0x1UL << PU_PATCHENSET_PATCH3_Pos)

Bit mask of PATCH3 field.

Definition at line 4697 of file nrf51_bitfields.h.

◆ PU_PATCHENSET_PATCH3_Pos

#define PU_PATCHENSET_PATCH3_Pos (3UL)

Position of PATCH3 field.

Definition at line 4696 of file nrf51_bitfields.h.

◆ PU_PATCHENSET_PATCH3_Set

#define PU_PATCHENSET_PATCH3_Set (1UL)

Enable patch on write.

Definition at line 4700 of file nrf51_bitfields.h.

◆ PU_PATCHENSET_PATCH4_Disabled

#define PU_PATCHENSET_PATCH4_Disabled (0UL)

Patch disabled.

Definition at line 4691 of file nrf51_bitfields.h.

◆ PU_PATCHENSET_PATCH4_Enabled

#define PU_PATCHENSET_PATCH4_Enabled (1UL)

Patch enabled.

Definition at line 4692 of file nrf51_bitfields.h.

◆ PU_PATCHENSET_PATCH4_Msk

#define PU_PATCHENSET_PATCH4_Msk (0x1UL << PU_PATCHENSET_PATCH4_Pos)

Bit mask of PATCH4 field.

Definition at line 4690 of file nrf51_bitfields.h.

◆ PU_PATCHENSET_PATCH4_Pos

#define PU_PATCHENSET_PATCH4_Pos (4UL)

Position of PATCH4 field.

Definition at line 4689 of file nrf51_bitfields.h.

◆ PU_PATCHENSET_PATCH4_Set

#define PU_PATCHENSET_PATCH4_Set (1UL)

Enable patch on write.

Definition at line 4693 of file nrf51_bitfields.h.

◆ PU_PATCHENSET_PATCH5_Disabled

#define PU_PATCHENSET_PATCH5_Disabled (0UL)

Patch disabled.

Definition at line 4684 of file nrf51_bitfields.h.

◆ PU_PATCHENSET_PATCH5_Enabled

#define PU_PATCHENSET_PATCH5_Enabled (1UL)

Patch enabled.

Definition at line 4685 of file nrf51_bitfields.h.

◆ PU_PATCHENSET_PATCH5_Msk

#define PU_PATCHENSET_PATCH5_Msk (0x1UL << PU_PATCHENSET_PATCH5_Pos)

Bit mask of PATCH5 field.

Definition at line 4683 of file nrf51_bitfields.h.

◆ PU_PATCHENSET_PATCH5_Pos

#define PU_PATCHENSET_PATCH5_Pos (5UL)

Position of PATCH5 field.

Definition at line 4682 of file nrf51_bitfields.h.

◆ PU_PATCHENSET_PATCH5_Set

#define PU_PATCHENSET_PATCH5_Set (1UL)

Enable patch on write.

Definition at line 4686 of file nrf51_bitfields.h.

◆ PU_PATCHENSET_PATCH6_Disabled

#define PU_PATCHENSET_PATCH6_Disabled (0UL)

Patch disabled.

Definition at line 4677 of file nrf51_bitfields.h.

◆ PU_PATCHENSET_PATCH6_Enabled

#define PU_PATCHENSET_PATCH6_Enabled (1UL)

Patch enabled.

Definition at line 4678 of file nrf51_bitfields.h.

◆ PU_PATCHENSET_PATCH6_Msk

#define PU_PATCHENSET_PATCH6_Msk (0x1UL << PU_PATCHENSET_PATCH6_Pos)

Bit mask of PATCH6 field.

Definition at line 4676 of file nrf51_bitfields.h.

◆ PU_PATCHENSET_PATCH6_Pos

#define PU_PATCHENSET_PATCH6_Pos (6UL)

Position of PATCH6 field.

Definition at line 4675 of file nrf51_bitfields.h.

◆ PU_PATCHENSET_PATCH6_Set

#define PU_PATCHENSET_PATCH6_Set (1UL)

Enable patch on write.

Definition at line 4679 of file nrf51_bitfields.h.

◆ PU_PATCHENSET_PATCH7_Disabled

#define PU_PATCHENSET_PATCH7_Disabled (0UL)

Patch disabled.

Definition at line 4670 of file nrf51_bitfields.h.

◆ PU_PATCHENSET_PATCH7_Enabled

#define PU_PATCHENSET_PATCH7_Enabled (1UL)

Patch enabled.

Definition at line 4671 of file nrf51_bitfields.h.

◆ PU_PATCHENSET_PATCH7_Msk

#define PU_PATCHENSET_PATCH7_Msk (0x1UL << PU_PATCHENSET_PATCH7_Pos)

Bit mask of PATCH7 field.

Definition at line 4669 of file nrf51_bitfields.h.

◆ PU_PATCHENSET_PATCH7_Pos

#define PU_PATCHENSET_PATCH7_Pos (7UL)

Position of PATCH7 field.

Definition at line 4668 of file nrf51_bitfields.h.

◆ PU_PATCHENSET_PATCH7_Set

#define PU_PATCHENSET_PATCH7_Set (1UL)

Enable patch on write.

Definition at line 4672 of file nrf51_bitfields.h.

◆ QDEC_ACCDBL_ACCDBL_Msk

#define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos)

Bit mask of ACCDBL field.

Definition at line 4925 of file nrf51_bitfields.h.

◆ QDEC_ACCDBL_ACCDBL_Pos

#define QDEC_ACCDBL_ACCDBL_Pos (0UL)

Position of ACCDBL field.

Definition at line 4924 of file nrf51_bitfields.h.

◆ QDEC_ACCDBLREAD_ACCDBLREAD_Msk

#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos)

Bit mask of ACCDBLREAD field.

Definition at line 4932 of file nrf51_bitfields.h.

◆ QDEC_ACCDBLREAD_ACCDBLREAD_Pos

#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL)

Position of ACCDBLREAD field.

Definition at line 4931 of file nrf51_bitfields.h.

◆ QDEC_DBFEN_DBFEN_Disabled

#define QDEC_DBFEN_DBFEN_Disabled (0UL)

Debounce input filters disabled.

Definition at line 4910 of file nrf51_bitfields.h.

◆ QDEC_DBFEN_DBFEN_Enabled

#define QDEC_DBFEN_DBFEN_Enabled (1UL)

Debounce input filters enabled.

Definition at line 4911 of file nrf51_bitfields.h.

◆ QDEC_DBFEN_DBFEN_Msk

#define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos)

Bit mask of DBFEN field.

Definition at line 4909 of file nrf51_bitfields.h.

◆ QDEC_DBFEN_DBFEN_Pos

#define QDEC_DBFEN_DBFEN_Pos (0UL)

Position of DBFEN field.

Definition at line 4908 of file nrf51_bitfields.h.

◆ QDEC_ENABLE_ENABLE_Disabled

#define QDEC_ENABLE_ENABLE_Disabled (0UL)

Disabled QDEC.

Definition at line 4855 of file nrf51_bitfields.h.

◆ QDEC_ENABLE_ENABLE_Enabled

#define QDEC_ENABLE_ENABLE_Enabled (1UL)

Enable QDEC.

Definition at line 4856 of file nrf51_bitfields.h.

◆ QDEC_ENABLE_ENABLE_Msk

#define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos)

Bit mask of ENABLE field.

Definition at line 4854 of file nrf51_bitfields.h.

◆ QDEC_ENABLE_ENABLE_Pos

#define QDEC_ENABLE_ENABLE_Pos (0UL)

Position of ENABLE field.

Definition at line 4853 of file nrf51_bitfields.h.

◆ QDEC_INTENCLR_ACCOF_Clear

#define QDEC_INTENCLR_ACCOF_Clear (1UL)

Disable interrupt on write.

Definition at line 4833 of file nrf51_bitfields.h.

◆ QDEC_INTENCLR_ACCOF_Disabled

#define QDEC_INTENCLR_ACCOF_Disabled (0UL)

Interrupt disabled.

Definition at line 4831 of file nrf51_bitfields.h.

◆ QDEC_INTENCLR_ACCOF_Enabled

#define QDEC_INTENCLR_ACCOF_Enabled (1UL)

Interrupt enabled.

Definition at line 4832 of file nrf51_bitfields.h.

◆ QDEC_INTENCLR_ACCOF_Msk

#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos)

Bit mask of ACCOF field.

Definition at line 4830 of file nrf51_bitfields.h.

◆ QDEC_INTENCLR_ACCOF_Pos

#define QDEC_INTENCLR_ACCOF_Pos (2UL)

Position of ACCOF field.

Definition at line 4829 of file nrf51_bitfields.h.

◆ QDEC_INTENCLR_REPORTRDY_Clear

#define QDEC_INTENCLR_REPORTRDY_Clear (1UL)

Disable interrupt on write.

Definition at line 4840 of file nrf51_bitfields.h.

◆ QDEC_INTENCLR_REPORTRDY_Disabled

#define QDEC_INTENCLR_REPORTRDY_Disabled (0UL)

Interrupt disabled.

Definition at line 4838 of file nrf51_bitfields.h.

◆ QDEC_INTENCLR_REPORTRDY_Enabled

#define QDEC_INTENCLR_REPORTRDY_Enabled (1UL)

Interrupt enabled.

Definition at line 4839 of file nrf51_bitfields.h.

◆ QDEC_INTENCLR_REPORTRDY_Msk

#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos)

Bit mask of REPORTRDY field.

Definition at line 4837 of file nrf51_bitfields.h.

◆ QDEC_INTENCLR_REPORTRDY_Pos

#define QDEC_INTENCLR_REPORTRDY_Pos (1UL)

Position of REPORTRDY field.

Definition at line 4836 of file nrf51_bitfields.h.

◆ QDEC_INTENCLR_SAMPLERDY_Clear

#define QDEC_INTENCLR_SAMPLERDY_Clear (1UL)

Disable interrupt on write.

Definition at line 4847 of file nrf51_bitfields.h.

◆ QDEC_INTENCLR_SAMPLERDY_Disabled

#define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL)

Interrupt disabled.

Definition at line 4845 of file nrf51_bitfields.h.

◆ QDEC_INTENCLR_SAMPLERDY_Enabled

#define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL)

Interrupt enabled.

Definition at line 4846 of file nrf51_bitfields.h.

◆ QDEC_INTENCLR_SAMPLERDY_Msk

#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos)

Bit mask of SAMPLERDY field.

Definition at line 4844 of file nrf51_bitfields.h.

◆ QDEC_INTENCLR_SAMPLERDY_Pos

#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL)

Position of SAMPLERDY field.

Definition at line 4843 of file nrf51_bitfields.h.

◆ QDEC_INTENSET_ACCOF_Disabled

#define QDEC_INTENSET_ACCOF_Disabled (0UL)

Interrupt disabled.

Definition at line 4807 of file nrf51_bitfields.h.

◆ QDEC_INTENSET_ACCOF_Enabled

#define QDEC_INTENSET_ACCOF_Enabled (1UL)

Interrupt enabled.

Definition at line 4808 of file nrf51_bitfields.h.

◆ QDEC_INTENSET_ACCOF_Msk

#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos)

Bit mask of ACCOF field.

Definition at line 4806 of file nrf51_bitfields.h.

◆ QDEC_INTENSET_ACCOF_Pos

#define QDEC_INTENSET_ACCOF_Pos (2UL)

Position of ACCOF field.

Definition at line 4805 of file nrf51_bitfields.h.

◆ QDEC_INTENSET_ACCOF_Set

#define QDEC_INTENSET_ACCOF_Set (1UL)

Enable interrupt on write.

Definition at line 4809 of file nrf51_bitfields.h.

◆ QDEC_INTENSET_REPORTRDY_Disabled

#define QDEC_INTENSET_REPORTRDY_Disabled (0UL)

Interrupt disabled.

Definition at line 4814 of file nrf51_bitfields.h.

◆ QDEC_INTENSET_REPORTRDY_Enabled

#define QDEC_INTENSET_REPORTRDY_Enabled (1UL)

Interrupt enabled.

Definition at line 4815 of file nrf51_bitfields.h.

◆ QDEC_INTENSET_REPORTRDY_Msk

#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos)

Bit mask of REPORTRDY field.

Definition at line 4813 of file nrf51_bitfields.h.

◆ QDEC_INTENSET_REPORTRDY_Pos

#define QDEC_INTENSET_REPORTRDY_Pos (1UL)

Position of REPORTRDY field.

Definition at line 4812 of file nrf51_bitfields.h.

◆ QDEC_INTENSET_REPORTRDY_Set

#define QDEC_INTENSET_REPORTRDY_Set (1UL)

Enable interrupt on write.

Definition at line 4816 of file nrf51_bitfields.h.

◆ QDEC_INTENSET_SAMPLERDY_Disabled

#define QDEC_INTENSET_SAMPLERDY_Disabled (0UL)

Interrupt disabled.

Definition at line 4821 of file nrf51_bitfields.h.

◆ QDEC_INTENSET_SAMPLERDY_Enabled

#define QDEC_INTENSET_SAMPLERDY_Enabled (1UL)

Interrupt enabled.

Definition at line 4822 of file nrf51_bitfields.h.

◆ QDEC_INTENSET_SAMPLERDY_Msk

#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos)

Bit mask of SAMPLERDY field.

Definition at line 4820 of file nrf51_bitfields.h.

◆ QDEC_INTENSET_SAMPLERDY_Pos

#define QDEC_INTENSET_SAMPLERDY_Pos (0UL)

Position of SAMPLERDY field.

Definition at line 4819 of file nrf51_bitfields.h.

◆ QDEC_INTENSET_SAMPLERDY_Set

#define QDEC_INTENSET_SAMPLERDY_Set (1UL)

Enable interrupt on write.

Definition at line 4823 of file nrf51_bitfields.h.

◆ QDEC_LEDPOL_LEDPOL_ActiveHigh

#define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL)

LED output is active high.

Definition at line 4865 of file nrf51_bitfields.h.

◆ QDEC_LEDPOL_LEDPOL_ActiveLow

#define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL)

LED output is active low.

Definition at line 4864 of file nrf51_bitfields.h.

◆ QDEC_LEDPOL_LEDPOL_Msk

#define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos)

Bit mask of LEDPOL field.

Definition at line 4863 of file nrf51_bitfields.h.

◆ QDEC_LEDPOL_LEDPOL_Pos

#define QDEC_LEDPOL_LEDPOL_Pos (0UL)

Position of LEDPOL field.

Definition at line 4862 of file nrf51_bitfields.h.

◆ QDEC_LEDPRE_LEDPRE_Msk

#define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos)

Bit mask of LEDPRE field.

Definition at line 4918 of file nrf51_bitfields.h.

◆ QDEC_LEDPRE_LEDPRE_Pos

#define QDEC_LEDPRE_LEDPRE_Pos (0UL)

Position of LEDPRE field.

Definition at line 4917 of file nrf51_bitfields.h.

◆ QDEC_POWER_POWER_Disabled

#define QDEC_POWER_POWER_Disabled (0UL)

Module power disabled.

Definition at line 4940 of file nrf51_bitfields.h.

◆ QDEC_POWER_POWER_Enabled

#define QDEC_POWER_POWER_Enabled (1UL)

Module power enabled.

Definition at line 4941 of file nrf51_bitfields.h.

◆ QDEC_POWER_POWER_Msk

#define QDEC_POWER_POWER_Msk (0x1UL << QDEC_POWER_POWER_Pos)

Bit mask of POWER field.

Definition at line 4939 of file nrf51_bitfields.h.

◆ QDEC_POWER_POWER_Pos

#define QDEC_POWER_POWER_Pos (0UL)

Position of POWER field.

Definition at line 4938 of file nrf51_bitfields.h.

◆ QDEC_REPORTPER_REPORTPER_10Smpl

#define QDEC_REPORTPER_REPORTPER_10Smpl (0x00UL)

10 samples per report.

Definition at line 4895 of file nrf51_bitfields.h.

◆ QDEC_REPORTPER_REPORTPER_120Smpl

#define QDEC_REPORTPER_REPORTPER_120Smpl (0x03UL)

120 samples per report.

Definition at line 4898 of file nrf51_bitfields.h.

◆ QDEC_REPORTPER_REPORTPER_160Smpl

#define QDEC_REPORTPER_REPORTPER_160Smpl (0x04UL)

160 samples per report.

Definition at line 4899 of file nrf51_bitfields.h.

◆ QDEC_REPORTPER_REPORTPER_200Smpl

#define QDEC_REPORTPER_REPORTPER_200Smpl (0x05UL)

200 samples per report.

Definition at line 4900 of file nrf51_bitfields.h.

◆ QDEC_REPORTPER_REPORTPER_240Smpl

#define QDEC_REPORTPER_REPORTPER_240Smpl (0x06UL)

240 samples per report.

Definition at line 4901 of file nrf51_bitfields.h.

◆ QDEC_REPORTPER_REPORTPER_280Smpl

#define QDEC_REPORTPER_REPORTPER_280Smpl (0x07UL)

280 samples per report.

Definition at line 4902 of file nrf51_bitfields.h.

◆ QDEC_REPORTPER_REPORTPER_40Smpl

#define QDEC_REPORTPER_REPORTPER_40Smpl (0x01UL)

40 samples per report.

Definition at line 4896 of file nrf51_bitfields.h.

◆ QDEC_REPORTPER_REPORTPER_80Smpl

#define QDEC_REPORTPER_REPORTPER_80Smpl (0x02UL)

80 samples per report.

Definition at line 4897 of file nrf51_bitfields.h.

◆ QDEC_REPORTPER_REPORTPER_Msk

#define QDEC_REPORTPER_REPORTPER_Msk (0x7UL << QDEC_REPORTPER_REPORTPER_Pos)

Bit mask of REPORTPER field.

Definition at line 4894 of file nrf51_bitfields.h.

◆ QDEC_REPORTPER_REPORTPER_Pos

#define QDEC_REPORTPER_REPORTPER_Pos (0UL)

Position of REPORTPER field.

Definition at line 4893 of file nrf51_bitfields.h.

◆ QDEC_SAMPLE_SAMPLE_Msk

#define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos)

Bit mask of SAMPLE field.

Definition at line 4887 of file nrf51_bitfields.h.

◆ QDEC_SAMPLE_SAMPLE_Pos

#define QDEC_SAMPLE_SAMPLE_Pos (0UL)

Position of SAMPLE field.

Definition at line 4886 of file nrf51_bitfields.h.

◆ QDEC_SAMPLEPER_SAMPLEPER_1024us

#define QDEC_SAMPLEPER_SAMPLEPER_1024us (0x03UL)

1024us sample period.

Definition at line 4876 of file nrf51_bitfields.h.

◆ QDEC_SAMPLEPER_SAMPLEPER_128us

#define QDEC_SAMPLEPER_SAMPLEPER_128us (0x00UL)

128us sample period.

Definition at line 4873 of file nrf51_bitfields.h.

◆ QDEC_SAMPLEPER_SAMPLEPER_16384us

#define QDEC_SAMPLEPER_SAMPLEPER_16384us (0x07UL)

16384us sample period.

Definition at line 4880 of file nrf51_bitfields.h.

◆ QDEC_SAMPLEPER_SAMPLEPER_2048us

#define QDEC_SAMPLEPER_SAMPLEPER_2048us (0x04UL)

2048us sample period.

Definition at line 4877 of file nrf51_bitfields.h.

◆ QDEC_SAMPLEPER_SAMPLEPER_256us

#define QDEC_SAMPLEPER_SAMPLEPER_256us (0x01UL)

256us sample period.

Definition at line 4874 of file nrf51_bitfields.h.

◆ QDEC_SAMPLEPER_SAMPLEPER_4096us

#define QDEC_SAMPLEPER_SAMPLEPER_4096us (0x05UL)

4096us sample period.

Definition at line 4878 of file nrf51_bitfields.h.

◆ QDEC_SAMPLEPER_SAMPLEPER_512us

#define QDEC_SAMPLEPER_SAMPLEPER_512us (0x02UL)

512us sample period.

Definition at line 4875 of file nrf51_bitfields.h.

◆ QDEC_SAMPLEPER_SAMPLEPER_8192us

#define QDEC_SAMPLEPER_SAMPLEPER_8192us (0x06UL)

8192us sample period.

Definition at line 4879 of file nrf51_bitfields.h.

◆ QDEC_SAMPLEPER_SAMPLEPER_Msk

#define QDEC_SAMPLEPER_SAMPLEPER_Msk (0x7UL << QDEC_SAMPLEPER_SAMPLEPER_Pos)

Bit mask of SAMPLEPER field.

Definition at line 4872 of file nrf51_bitfields.h.

◆ QDEC_SAMPLEPER_SAMPLEPER_Pos

#define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL)

Position of SAMPLEPER field.

Definition at line 4871 of file nrf51_bitfields.h.

◆ QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled

#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL)

Shortcut disabled.

Definition at line 4798 of file nrf51_bitfields.h.

◆ QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled

#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL)

Shortcut enabled.

Definition at line 4799 of file nrf51_bitfields.h.

◆ QDEC_SHORTS_REPORTRDY_READCLRACC_Msk

#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos)

Bit mask of REPORTRDY_READCLRACC field.

Definition at line 4797 of file nrf51_bitfields.h.

◆ QDEC_SHORTS_REPORTRDY_READCLRACC_Pos

#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL)

Position of REPORTRDY_READCLRACC field.

Definition at line 4796 of file nrf51_bitfields.h.

◆ QDEC_SHORTS_SAMPLERDY_STOP_Disabled

#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL)

Shortcut disabled.

Definition at line 4792 of file nrf51_bitfields.h.

◆ QDEC_SHORTS_SAMPLERDY_STOP_Enabled

#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL)

Shortcut enabled.

Definition at line 4793 of file nrf51_bitfields.h.

◆ QDEC_SHORTS_SAMPLERDY_STOP_Msk

#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos)

Bit mask of SAMPLERDY_STOP field.

Definition at line 4791 of file nrf51_bitfields.h.

◆ QDEC_SHORTS_SAMPLERDY_STOP_Pos

#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL)

Position of SAMPLERDY_STOP field.

Definition at line 4790 of file nrf51_bitfields.h.

◆ RADIO_CD_CD_Msk

#define RADIO_CD_CD_Msk (0x1UL << RADIO_CD_CD_Pos)

Bit mask of CD field.

Definition at line 5144 of file nrf51_bitfields.h.

◆ RADIO_CD_CD_Pos

#define RADIO_CD_CD_Pos (0UL)

Position of CD field.

Definition at line 5143 of file nrf51_bitfields.h.

◆ RADIO_CRCCNF_LEN_Disabled

#define RADIO_CRCCNF_LEN_Disabled (0UL)

CRC calculation disabled.

Definition at line 5350 of file nrf51_bitfields.h.

◆ RADIO_CRCCNF_LEN_Msk

#define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos)

Bit mask of LEN field.

Definition at line 5349 of file nrf51_bitfields.h.

◆ RADIO_CRCCNF_LEN_One

#define RADIO_CRCCNF_LEN_One (1UL)

One byte long CRC.

Definition at line 5351 of file nrf51_bitfields.h.

◆ RADIO_CRCCNF_LEN_Pos

#define RADIO_CRCCNF_LEN_Pos (0UL)

Position of LEN field.

Definition at line 5348 of file nrf51_bitfields.h.

◆ RADIO_CRCCNF_LEN_Three

#define RADIO_CRCCNF_LEN_Three (3UL)

Three bytes long CRC.

Definition at line 5353 of file nrf51_bitfields.h.

◆ RADIO_CRCCNF_LEN_Two

#define RADIO_CRCCNF_LEN_Two (2UL)

Two bytes long CRC.

Definition at line 5352 of file nrf51_bitfields.h.

◆ RADIO_CRCCNF_SKIPADDR_Include

#define RADIO_CRCCNF_SKIPADDR_Include (0UL)

Include packet address in CRC calculation.

Definition at line 5344 of file nrf51_bitfields.h.

◆ RADIO_CRCCNF_SKIPADDR_Msk

#define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos)

Bit mask of SKIPADDR field.

Definition at line 5343 of file nrf51_bitfields.h.

◆ RADIO_CRCCNF_SKIPADDR_Pos

#define RADIO_CRCCNF_SKIPADDR_Pos (8UL)

Position of SKIPADDR field.

Definition at line 5342 of file nrf51_bitfields.h.

◆ RADIO_CRCCNF_SKIPADDR_Skip

#define RADIO_CRCCNF_SKIPADDR_Skip (1UL)

Packet address is skipped in CRC calculation. The CRC calculation will start at the first byte after the address.

Definition at line 5345 of file nrf51_bitfields.h.

◆ RADIO_CRCINIT_CRCINIT_Msk

#define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos)

Bit mask of CRCINIT field.

Definition at line 5367 of file nrf51_bitfields.h.

◆ RADIO_CRCINIT_CRCINIT_Pos

#define RADIO_CRCINIT_CRCINIT_Pos (0UL)

Position of CRCINIT field.

Definition at line 5366 of file nrf51_bitfields.h.

◆ RADIO_CRCPOLY_CRCPOLY_Msk

#define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos)

Bit mask of CRCPOLY field.

Definition at line 5360 of file nrf51_bitfields.h.

◆ RADIO_CRCPOLY_CRCPOLY_Pos

#define RADIO_CRCPOLY_CRCPOLY_Pos (0UL)

Position of CRCPOLY field.

Definition at line 5359 of file nrf51_bitfields.h.

◆ RADIO_CRCSTATUS_CRCSTATUS_CRCError

#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL)

Packet received with CRC error.

Definition at line 5136 of file nrf51_bitfields.h.

◆ RADIO_CRCSTATUS_CRCSTATUS_CRCOk

#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL)

Packet received with CRC ok.

Definition at line 5137 of file nrf51_bitfields.h.

◆ RADIO_CRCSTATUS_CRCSTATUS_Msk

#define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos)

Bit mask of CRCSTATUS field.

Definition at line 5135 of file nrf51_bitfields.h.

◆ RADIO_CRCSTATUS_CRCSTATUS_Pos

#define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL)

Position of CRCSTATUS field.

Definition at line 5134 of file nrf51_bitfields.h.

◆ RADIO_DACNF_ENA0_Disabled

#define RADIO_DACNF_ENA0_Disabled (0UL)

Disabled.

Definition at line 5508 of file nrf51_bitfields.h.

◆ RADIO_DACNF_ENA0_Enabled

#define RADIO_DACNF_ENA0_Enabled (1UL)

Enabled.

Definition at line 5509 of file nrf51_bitfields.h.

◆ RADIO_DACNF_ENA0_Msk

#define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos)

Bit mask of ENA0 field.

Definition at line 5507 of file nrf51_bitfields.h.

◆ RADIO_DACNF_ENA0_Pos

#define RADIO_DACNF_ENA0_Pos (0UL)

Position of ENA0 field.

Definition at line 5506 of file nrf51_bitfields.h.

◆ RADIO_DACNF_ENA1_Disabled

#define RADIO_DACNF_ENA1_Disabled (0UL)

Disabled.

Definition at line 5502 of file nrf51_bitfields.h.

◆ RADIO_DACNF_ENA1_Enabled

#define RADIO_DACNF_ENA1_Enabled (1UL)

Enabled.

Definition at line 5503 of file nrf51_bitfields.h.

◆ RADIO_DACNF_ENA1_Msk

#define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos)

Bit mask of ENA1 field.

Definition at line 5501 of file nrf51_bitfields.h.

◆ RADIO_DACNF_ENA1_Pos

#define RADIO_DACNF_ENA1_Pos (1UL)

Position of ENA1 field.

Definition at line 5500 of file nrf51_bitfields.h.

◆ RADIO_DACNF_ENA2_Disabled

#define RADIO_DACNF_ENA2_Disabled (0UL)

Disabled.

Definition at line 5496 of file nrf51_bitfields.h.

◆ RADIO_DACNF_ENA2_Enabled

#define RADIO_DACNF_ENA2_Enabled (1UL)

Enabled.

Definition at line 5497 of file nrf51_bitfields.h.

◆ RADIO_DACNF_ENA2_Msk

#define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos)

Bit mask of ENA2 field.

Definition at line 5495 of file nrf51_bitfields.h.

◆ RADIO_DACNF_ENA2_Pos

#define RADIO_DACNF_ENA2_Pos (2UL)

Position of ENA2 field.

Definition at line 5494 of file nrf51_bitfields.h.

◆ RADIO_DACNF_ENA3_Disabled

#define RADIO_DACNF_ENA3_Disabled (0UL)

Disabled.

Definition at line 5490 of file nrf51_bitfields.h.

◆ RADIO_DACNF_ENA3_Enabled

#define RADIO_DACNF_ENA3_Enabled (1UL)

Enabled.

Definition at line 5491 of file nrf51_bitfields.h.

◆ RADIO_DACNF_ENA3_Msk

#define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos)

Bit mask of ENA3 field.

Definition at line 5489 of file nrf51_bitfields.h.

◆ RADIO_DACNF_ENA3_Pos

#define RADIO_DACNF_ENA3_Pos (3UL)

Position of ENA3 field.

Definition at line 5488 of file nrf51_bitfields.h.

◆ RADIO_DACNF_ENA4_Disabled

#define RADIO_DACNF_ENA4_Disabled (0UL)

Disabled.

Definition at line 5484 of file nrf51_bitfields.h.

◆ RADIO_DACNF_ENA4_Enabled

#define RADIO_DACNF_ENA4_Enabled (1UL)

Enabled.

Definition at line 5485 of file nrf51_bitfields.h.

◆ RADIO_DACNF_ENA4_Msk

#define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos)

Bit mask of ENA4 field.

Definition at line 5483 of file nrf51_bitfields.h.

◆ RADIO_DACNF_ENA4_Pos

#define RADIO_DACNF_ENA4_Pos (4UL)

Position of ENA4 field.

Definition at line 5482 of file nrf51_bitfields.h.

◆ RADIO_DACNF_ENA5_Disabled

#define RADIO_DACNF_ENA5_Disabled (0UL)

Disabled.

Definition at line 5478 of file nrf51_bitfields.h.

◆ RADIO_DACNF_ENA5_Enabled

#define RADIO_DACNF_ENA5_Enabled (1UL)

Enabled.

Definition at line 5479 of file nrf51_bitfields.h.

◆ RADIO_DACNF_ENA5_Msk

#define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos)

Bit mask of ENA5 field.

Definition at line 5477 of file nrf51_bitfields.h.

◆ RADIO_DACNF_ENA5_Pos

#define RADIO_DACNF_ENA5_Pos (5UL)

Position of ENA5 field.

Definition at line 5476 of file nrf51_bitfields.h.

◆ RADIO_DACNF_ENA6_Disabled

#define RADIO_DACNF_ENA6_Disabled (0UL)

Disabled.

Definition at line 5472 of file nrf51_bitfields.h.

◆ RADIO_DACNF_ENA6_Enabled

#define RADIO_DACNF_ENA6_Enabled (1UL)

Enabled.

Definition at line 5473 of file nrf51_bitfields.h.

◆ RADIO_DACNF_ENA6_Msk

#define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos)

Bit mask of ENA6 field.

Definition at line 5471 of file nrf51_bitfields.h.

◆ RADIO_DACNF_ENA6_Pos

#define RADIO_DACNF_ENA6_Pos (6UL)

Position of ENA6 field.

Definition at line 5470 of file nrf51_bitfields.h.

◆ RADIO_DACNF_ENA7_Disabled

#define RADIO_DACNF_ENA7_Disabled (0UL)

Disabled.

Definition at line 5466 of file nrf51_bitfields.h.

◆ RADIO_DACNF_ENA7_Enabled

#define RADIO_DACNF_ENA7_Enabled (1UL)

Enabled.

Definition at line 5467 of file nrf51_bitfields.h.

◆ RADIO_DACNF_ENA7_Msk

#define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos)

Bit mask of ENA7 field.

Definition at line 5465 of file nrf51_bitfields.h.

◆ RADIO_DACNF_ENA7_Pos

#define RADIO_DACNF_ENA7_Pos (7UL)

Position of ENA7 field.

Definition at line 5464 of file nrf51_bitfields.h.

◆ RADIO_DACNF_TXADD0_Msk

#define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos)

Bit mask of TXADD0 field.

Definition at line 5461 of file nrf51_bitfields.h.

◆ RADIO_DACNF_TXADD0_Pos

#define RADIO_DACNF_TXADD0_Pos (8UL)

Position of TXADD0 field.

Definition at line 5460 of file nrf51_bitfields.h.

◆ RADIO_DACNF_TXADD1_Msk

#define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos)

Bit mask of TXADD1 field.

Definition at line 5457 of file nrf51_bitfields.h.

◆ RADIO_DACNF_TXADD1_Pos

#define RADIO_DACNF_TXADD1_Pos (9UL)

Position of TXADD1 field.

Definition at line 5456 of file nrf51_bitfields.h.

◆ RADIO_DACNF_TXADD2_Msk

#define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos)

Bit mask of TXADD2 field.

Definition at line 5453 of file nrf51_bitfields.h.

◆ RADIO_DACNF_TXADD2_Pos

#define RADIO_DACNF_TXADD2_Pos (10UL)

Position of TXADD2 field.

Definition at line 5452 of file nrf51_bitfields.h.

◆ RADIO_DACNF_TXADD3_Msk

#define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos)

Bit mask of TXADD3 field.

Definition at line 5449 of file nrf51_bitfields.h.

◆ RADIO_DACNF_TXADD3_Pos

#define RADIO_DACNF_TXADD3_Pos (11UL)

Position of TXADD3 field.

Definition at line 5448 of file nrf51_bitfields.h.

◆ RADIO_DACNF_TXADD4_Msk

#define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos)

Bit mask of TXADD4 field.

Definition at line 5445 of file nrf51_bitfields.h.

◆ RADIO_DACNF_TXADD4_Pos

#define RADIO_DACNF_TXADD4_Pos (12UL)

Position of TXADD4 field.

Definition at line 5444 of file nrf51_bitfields.h.

◆ RADIO_DACNF_TXADD5_Msk

#define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos)

Bit mask of TXADD5 field.

Definition at line 5441 of file nrf51_bitfields.h.

◆ RADIO_DACNF_TXADD5_Pos

#define RADIO_DACNF_TXADD5_Pos (13UL)

Position of TXADD5 field.

Definition at line 5440 of file nrf51_bitfields.h.

◆ RADIO_DACNF_TXADD6_Msk

#define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos)

Bit mask of TXADD6 field.

Definition at line 5437 of file nrf51_bitfields.h.

◆ RADIO_DACNF_TXADD6_Pos

#define RADIO_DACNF_TXADD6_Pos (14UL)

Position of TXADD6 field.

Definition at line 5436 of file nrf51_bitfields.h.

◆ RADIO_DACNF_TXADD7_Msk

#define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos)

Bit mask of TXADD7 field.

Definition at line 5433 of file nrf51_bitfields.h.

◆ RADIO_DACNF_TXADD7_Pos

#define RADIO_DACNF_TXADD7_Pos (15UL)

Position of TXADD7 field.

Definition at line 5432 of file nrf51_bitfields.h.

◆ RADIO_DAI_DAI_Msk

#define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos)

Bit mask of DAI field.

Definition at line 5165 of file nrf51_bitfields.h.

◆ RADIO_DAI_DAI_Pos

#define RADIO_DAI_DAI_Pos (0UL)

Position of DAI field.

Definition at line 5164 of file nrf51_bitfields.h.

◆ RADIO_DAP_DAP_Msk

#define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos)

Bit mask of DAP field.

Definition at line 5426 of file nrf51_bitfields.h.

◆ RADIO_DAP_DAP_Pos

#define RADIO_DAP_DAP_Pos (0UL)

Position of DAP field.

Definition at line 5425 of file nrf51_bitfields.h.

◆ RADIO_DATAWHITEIV_DATAWHITEIV_Msk

#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos)

Bit mask of DATAWHITEIV field.

Definition at line 5419 of file nrf51_bitfields.h.

◆ RADIO_DATAWHITEIV_DATAWHITEIV_Pos

#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL)

Position of DATAWHITEIV field.

Definition at line 5418 of file nrf51_bitfields.h.

◆ RADIO_FREQUENCY_FREQUENCY_Msk

#define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos)

Bit mask of FREQUENCY field.

Definition at line 5172 of file nrf51_bitfields.h.

◆ RADIO_FREQUENCY_FREQUENCY_Pos

#define RADIO_FREQUENCY_FREQUENCY_Pos (0UL)

Position of FREQUENCY field.

Definition at line 5171 of file nrf51_bitfields.h.

◆ RADIO_INTENCLR_ADDRESS_Clear

#define RADIO_INTENCLR_ADDRESS_Clear (1UL)

Disable interrupt on write.

Definition at line 5121 of file nrf51_bitfields.h.

◆ RADIO_INTENCLR_ADDRESS_Disabled

#define RADIO_INTENCLR_ADDRESS_Disabled (0UL)

Interrupt disabled.

Definition at line 5119 of file nrf51_bitfields.h.

◆ RADIO_INTENCLR_ADDRESS_Enabled

#define RADIO_INTENCLR_ADDRESS_Enabled (1UL)

Interrupt enabled.

Definition at line 5120 of file nrf51_bitfields.h.

◆ RADIO_INTENCLR_ADDRESS_Msk

#define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos)

Bit mask of ADDRESS field.

Definition at line 5118 of file nrf51_bitfields.h.

◆ RADIO_INTENCLR_ADDRESS_Pos

#define RADIO_INTENCLR_ADDRESS_Pos (1UL)

Position of ADDRESS field.

Definition at line 5117 of file nrf51_bitfields.h.

◆ RADIO_INTENCLR_BCMATCH_Clear

#define RADIO_INTENCLR_BCMATCH_Clear (1UL)

Disable interrupt on write.

Definition at line 5072 of file nrf51_bitfields.h.

◆ RADIO_INTENCLR_BCMATCH_Disabled

#define RADIO_INTENCLR_BCMATCH_Disabled (0UL)

Interrupt disabled.

Definition at line 5070 of file nrf51_bitfields.h.

◆ RADIO_INTENCLR_BCMATCH_Enabled

#define RADIO_INTENCLR_BCMATCH_Enabled (1UL)

Interrupt enabled.

Definition at line 5071 of file nrf51_bitfields.h.

◆ RADIO_INTENCLR_BCMATCH_Msk

#define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos)

Bit mask of BCMATCH field.

Definition at line 5069 of file nrf51_bitfields.h.

◆ RADIO_INTENCLR_BCMATCH_Pos

#define RADIO_INTENCLR_BCMATCH_Pos (10UL)

Position of BCMATCH field.

Definition at line 5068 of file nrf51_bitfields.h.

◆ RADIO_INTENCLR_DEVMATCH_Clear

#define RADIO_INTENCLR_DEVMATCH_Clear (1UL)

Disable interrupt on write.

Definition at line 5093 of file nrf51_bitfields.h.

◆ RADIO_INTENCLR_DEVMATCH_Disabled

#define RADIO_INTENCLR_DEVMATCH_Disabled (0UL)

Interrupt disabled.

Definition at line 5091 of file nrf51_bitfields.h.

◆ RADIO_INTENCLR_DEVMATCH_Enabled

#define RADIO_INTENCLR_DEVMATCH_Enabled (1UL)

Interrupt enabled.

Definition at line 5092 of file nrf51_bitfields.h.

◆ RADIO_INTENCLR_DEVMATCH_Msk

#define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos)

Bit mask of DEVMATCH field.

Definition at line 5090 of file nrf51_bitfields.h.

◆ RADIO_INTENCLR_DEVMATCH_Pos

#define RADIO_INTENCLR_DEVMATCH_Pos (5UL)

Position of DEVMATCH field.

Definition at line 5089 of file nrf51_bitfields.h.

◆ RADIO_INTENCLR_DEVMISS_Clear

#define RADIO_INTENCLR_DEVMISS_Clear (1UL)

Disable interrupt on write.

Definition at line 5086 of file nrf51_bitfields.h.

◆ RADIO_INTENCLR_DEVMISS_Disabled

#define RADIO_INTENCLR_DEVMISS_Disabled (0UL)

Interrupt disabled.

Definition at line 5084 of file nrf51_bitfields.h.

◆ RADIO_INTENCLR_DEVMISS_Enabled

#define RADIO_INTENCLR_DEVMISS_Enabled (1UL)

Interrupt enabled.

Definition at line 5085 of file nrf51_bitfields.h.

◆ RADIO_INTENCLR_DEVMISS_Msk

#define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos)

Bit mask of DEVMISS field.

Definition at line 5083 of file nrf51_bitfields.h.

◆ RADIO_INTENCLR_DEVMISS_Pos

#define RADIO_INTENCLR_DEVMISS_Pos (6UL)

Position of DEVMISS field.

Definition at line 5082 of file nrf51_bitfields.h.

◆ RADIO_INTENCLR_DISABLED_Clear

#define RADIO_INTENCLR_DISABLED_Clear (1UL)

Disable interrupt on write.

Definition at line 5100 of file nrf51_bitfields.h.

◆ RADIO_INTENCLR_DISABLED_Disabled

#define RADIO_INTENCLR_DISABLED_Disabled (0UL)

Interrupt disabled.

Definition at line 5098 of file nrf51_bitfields.h.

◆ RADIO_INTENCLR_DISABLED_Enabled

#define RADIO_INTENCLR_DISABLED_Enabled (1UL)

Interrupt enabled.

Definition at line 5099 of file nrf51_bitfields.h.

◆ RADIO_INTENCLR_DISABLED_Msk

#define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos)

Bit mask of DISABLED field.

Definition at line 5097 of file nrf51_bitfields.h.

◆ RADIO_INTENCLR_DISABLED_Pos

#define RADIO_INTENCLR_DISABLED_Pos (4UL)

Position of DISABLED field.

Definition at line 5096 of file nrf51_bitfields.h.

◆ RADIO_INTENCLR_END_Clear

#define RADIO_INTENCLR_END_Clear (1UL)

Disable interrupt on write.

Definition at line 5107 of file nrf51_bitfields.h.

◆ RADIO_INTENCLR_END_Disabled

#define RADIO_INTENCLR_END_Disabled (0UL)

Interrupt disabled.

Definition at line 5105 of file nrf51_bitfields.h.

◆ RADIO_INTENCLR_END_Enabled

#define RADIO_INTENCLR_END_Enabled (1UL)

Interrupt enabled.

Definition at line 5106 of file nrf51_bitfields.h.

◆ RADIO_INTENCLR_END_Msk

#define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos)

Bit mask of END field.

Definition at line 5104 of file nrf51_bitfields.h.

◆ RADIO_INTENCLR_END_Pos

#define RADIO_INTENCLR_END_Pos (3UL)

Position of END field.

Definition at line 5103 of file nrf51_bitfields.h.

◆ RADIO_INTENCLR_PAYLOAD_Clear

#define RADIO_INTENCLR_PAYLOAD_Clear (1UL)

Disable interrupt on write.

Definition at line 5114 of file nrf51_bitfields.h.

◆ RADIO_INTENCLR_PAYLOAD_Disabled

#define RADIO_INTENCLR_PAYLOAD_Disabled (0UL)

Interrupt disabled.

Definition at line 5112 of file nrf51_bitfields.h.

◆ RADIO_INTENCLR_PAYLOAD_Enabled

#define RADIO_INTENCLR_PAYLOAD_Enabled (1UL)

Interrupt enabled.

Definition at line 5113 of file nrf51_bitfields.h.

◆ RADIO_INTENCLR_PAYLOAD_Msk

#define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos)

Bit mask of PAYLOAD field.

Definition at line 5111 of file nrf51_bitfields.h.

◆ RADIO_INTENCLR_PAYLOAD_Pos

#define RADIO_INTENCLR_PAYLOAD_Pos (2UL)

Position of PAYLOAD field.

Definition at line 5110 of file nrf51_bitfields.h.

◆ RADIO_INTENCLR_READY_Clear

#define RADIO_INTENCLR_READY_Clear (1UL)

Disable interrupt on write.

Definition at line 5128 of file nrf51_bitfields.h.

◆ RADIO_INTENCLR_READY_Disabled

#define RADIO_INTENCLR_READY_Disabled (0UL)

Interrupt disabled.

Definition at line 5126 of file nrf51_bitfields.h.

◆ RADIO_INTENCLR_READY_Enabled

#define RADIO_INTENCLR_READY_Enabled (1UL)

Interrupt enabled.

Definition at line 5127 of file nrf51_bitfields.h.

◆ RADIO_INTENCLR_READY_Msk

#define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos)

Bit mask of READY field.

Definition at line 5125 of file nrf51_bitfields.h.

◆ RADIO_INTENCLR_READY_Pos

#define RADIO_INTENCLR_READY_Pos (0UL)

Position of READY field.

Definition at line 5124 of file nrf51_bitfields.h.

◆ RADIO_INTENCLR_RSSIEND_Clear

#define RADIO_INTENCLR_RSSIEND_Clear (1UL)

Disable interrupt on write.

Definition at line 5079 of file nrf51_bitfields.h.

◆ RADIO_INTENCLR_RSSIEND_Disabled

#define RADIO_INTENCLR_RSSIEND_Disabled (0UL)

Interrupt disabled.

Definition at line 5077 of file nrf51_bitfields.h.

◆ RADIO_INTENCLR_RSSIEND_Enabled

#define RADIO_INTENCLR_RSSIEND_Enabled (1UL)

Interrupt enabled.

Definition at line 5078 of file nrf51_bitfields.h.

◆ RADIO_INTENCLR_RSSIEND_Msk

#define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos)

Bit mask of RSSIEND field.

Definition at line 5076 of file nrf51_bitfields.h.

◆ RADIO_INTENCLR_RSSIEND_Pos

#define RADIO_INTENCLR_RSSIEND_Pos (7UL)

Position of RSSIEND field.

Definition at line 5075 of file nrf51_bitfields.h.

◆ RADIO_INTENSET_ADDRESS_Disabled

#define RADIO_INTENSET_ADDRESS_Disabled (0UL)

Interrupt disabled.

Definition at line 5053 of file nrf51_bitfields.h.

◆ RADIO_INTENSET_ADDRESS_Enabled

#define RADIO_INTENSET_ADDRESS_Enabled (1UL)

Interrupt enabled.

Definition at line 5054 of file nrf51_bitfields.h.

◆ RADIO_INTENSET_ADDRESS_Msk

#define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos)

Bit mask of ADDRESS field.

Definition at line 5052 of file nrf51_bitfields.h.

◆ RADIO_INTENSET_ADDRESS_Pos

#define RADIO_INTENSET_ADDRESS_Pos (1UL)

Position of ADDRESS field.

Definition at line 5051 of file nrf51_bitfields.h.

◆ RADIO_INTENSET_ADDRESS_Set

#define RADIO_INTENSET_ADDRESS_Set (1UL)

Enable interrupt on write.

Definition at line 5055 of file nrf51_bitfields.h.

◆ RADIO_INTENSET_BCMATCH_Disabled

#define RADIO_INTENSET_BCMATCH_Disabled (0UL)

Interrupt disabled.

Definition at line 5004 of file nrf51_bitfields.h.

◆ RADIO_INTENSET_BCMATCH_Enabled

#define RADIO_INTENSET_BCMATCH_Enabled (1UL)

Interrupt enabled.

Definition at line 5005 of file nrf51_bitfields.h.

◆ RADIO_INTENSET_BCMATCH_Msk

#define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos)

Bit mask of BCMATCH field.

Definition at line 5003 of file nrf51_bitfields.h.

◆ RADIO_INTENSET_BCMATCH_Pos

#define RADIO_INTENSET_BCMATCH_Pos (10UL)

Position of BCMATCH field.

Definition at line 5002 of file nrf51_bitfields.h.

◆ RADIO_INTENSET_BCMATCH_Set

#define RADIO_INTENSET_BCMATCH_Set (1UL)

Enable interrupt on write.

Definition at line 5006 of file nrf51_bitfields.h.

◆ RADIO_INTENSET_DEVMATCH_Disabled

#define RADIO_INTENSET_DEVMATCH_Disabled (0UL)

Interrupt disabled.

Definition at line 5025 of file nrf51_bitfields.h.

◆ RADIO_INTENSET_DEVMATCH_Enabled

#define RADIO_INTENSET_DEVMATCH_Enabled (1UL)

Interrupt enabled.

Definition at line 5026 of file nrf51_bitfields.h.

◆ RADIO_INTENSET_DEVMATCH_Msk

#define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos)

Bit mask of DEVMATCH field.

Definition at line 5024 of file nrf51_bitfields.h.

◆ RADIO_INTENSET_DEVMATCH_Pos

#define RADIO_INTENSET_DEVMATCH_Pos (5UL)

Position of DEVMATCH field.

Definition at line 5023 of file nrf51_bitfields.h.

◆ RADIO_INTENSET_DEVMATCH_Set

#define RADIO_INTENSET_DEVMATCH_Set (1UL)

Enable interrupt on write.

Definition at line 5027 of file nrf51_bitfields.h.

◆ RADIO_INTENSET_DEVMISS_Disabled

#define RADIO_INTENSET_DEVMISS_Disabled (0UL)

Interrupt disabled.

Definition at line 5018 of file nrf51_bitfields.h.

◆ RADIO_INTENSET_DEVMISS_Enabled

#define RADIO_INTENSET_DEVMISS_Enabled (1UL)

Interrupt enabled.

Definition at line 5019 of file nrf51_bitfields.h.

◆ RADIO_INTENSET_DEVMISS_Msk

#define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos)

Bit mask of DEVMISS field.

Definition at line 5017 of file nrf51_bitfields.h.

◆ RADIO_INTENSET_DEVMISS_Pos

#define RADIO_INTENSET_DEVMISS_Pos (6UL)

Position of DEVMISS field.

Definition at line 5016 of file nrf51_bitfields.h.

◆ RADIO_INTENSET_DEVMISS_Set

#define RADIO_INTENSET_DEVMISS_Set (1UL)

Enable interrupt on write.

Definition at line 5020 of file nrf51_bitfields.h.

◆ RADIO_INTENSET_DISABLED_Disabled

#define RADIO_INTENSET_DISABLED_Disabled (0UL)

Interrupt disabled.

Definition at line 5032 of file nrf51_bitfields.h.

◆ RADIO_INTENSET_DISABLED_Enabled

#define RADIO_INTENSET_DISABLED_Enabled (1UL)

Interrupt enabled.

Definition at line 5033 of file nrf51_bitfields.h.

◆ RADIO_INTENSET_DISABLED_Msk

#define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos)

Bit mask of DISABLED field.

Definition at line 5031 of file nrf51_bitfields.h.

◆ RADIO_INTENSET_DISABLED_Pos

#define RADIO_INTENSET_DISABLED_Pos (4UL)

Position of DISABLED field.

Definition at line 5030 of file nrf51_bitfields.h.

◆ RADIO_INTENSET_DISABLED_Set

#define RADIO_INTENSET_DISABLED_Set (1UL)

Enable interrupt on write.

Definition at line 5034 of file nrf51_bitfields.h.

◆ RADIO_INTENSET_END_Disabled

#define RADIO_INTENSET_END_Disabled (0UL)

Interrupt disabled.

Definition at line 5039 of file nrf51_bitfields.h.

◆ RADIO_INTENSET_END_Enabled

#define RADIO_INTENSET_END_Enabled (1UL)

Interrupt enabled.

Definition at line 5040 of file nrf51_bitfields.h.

◆ RADIO_INTENSET_END_Msk

#define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos)

Bit mask of END field.

Definition at line 5038 of file nrf51_bitfields.h.

◆ RADIO_INTENSET_END_Pos

#define RADIO_INTENSET_END_Pos (3UL)

Position of END field.

Definition at line 5037 of file nrf51_bitfields.h.

◆ RADIO_INTENSET_END_Set

#define RADIO_INTENSET_END_Set (1UL)

Enable interrupt on write.

Definition at line 5041 of file nrf51_bitfields.h.

◆ RADIO_INTENSET_PAYLOAD_Disabled

#define RADIO_INTENSET_PAYLOAD_Disabled (0UL)

Interrupt disabled.

Definition at line 5046 of file nrf51_bitfields.h.

◆ RADIO_INTENSET_PAYLOAD_Enabled

#define RADIO_INTENSET_PAYLOAD_Enabled (1UL)

Interrupt enabled.

Definition at line 5047 of file nrf51_bitfields.h.

◆ RADIO_INTENSET_PAYLOAD_Msk

#define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos)

Bit mask of PAYLOAD field.

Definition at line 5045 of file nrf51_bitfields.h.

◆ RADIO_INTENSET_PAYLOAD_Pos

#define RADIO_INTENSET_PAYLOAD_Pos (2UL)

Position of PAYLOAD field.

Definition at line 5044 of file nrf51_bitfields.h.

◆ RADIO_INTENSET_PAYLOAD_Set

#define RADIO_INTENSET_PAYLOAD_Set (1UL)

Enable interrupt on write.

Definition at line 5048 of file nrf51_bitfields.h.

◆ RADIO_INTENSET_READY_Disabled

#define RADIO_INTENSET_READY_Disabled (0UL)

Interrupt disabled.

Definition at line 5060 of file nrf51_bitfields.h.

◆ RADIO_INTENSET_READY_Enabled

#define RADIO_INTENSET_READY_Enabled (1UL)

Interrupt enabled.

Definition at line 5061 of file nrf51_bitfields.h.

◆ RADIO_INTENSET_READY_Msk

#define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos)

Bit mask of READY field.

Definition at line 5059 of file nrf51_bitfields.h.

◆ RADIO_INTENSET_READY_Pos

#define RADIO_INTENSET_READY_Pos (0UL)

Position of READY field.

Definition at line 5058 of file nrf51_bitfields.h.

◆ RADIO_INTENSET_READY_Set

#define RADIO_INTENSET_READY_Set (1UL)

Enable interrupt on write.

Definition at line 5062 of file nrf51_bitfields.h.

◆ RADIO_INTENSET_RSSIEND_Disabled

#define RADIO_INTENSET_RSSIEND_Disabled (0UL)

Interrupt disabled.

Definition at line 5011 of file nrf51_bitfields.h.

◆ RADIO_INTENSET_RSSIEND_Enabled

#define RADIO_INTENSET_RSSIEND_Enabled (1UL)

Interrupt enabled.

Definition at line 5012 of file nrf51_bitfields.h.

◆ RADIO_INTENSET_RSSIEND_Msk

#define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos)

Bit mask of RSSIEND field.

Definition at line 5010 of file nrf51_bitfields.h.

◆ RADIO_INTENSET_RSSIEND_Pos

#define RADIO_INTENSET_RSSIEND_Pos (7UL)

Position of RSSIEND field.

Definition at line 5009 of file nrf51_bitfields.h.

◆ RADIO_INTENSET_RSSIEND_Set

#define RADIO_INTENSET_RSSIEND_Set (1UL)

Enable interrupt on write.

Definition at line 5013 of file nrf51_bitfields.h.

◆ RADIO_MODE_MODE_Ble_1Mbit

#define RADIO_MODE_MODE_Ble_1Mbit (0x03UL)

1Mbit/s Bluetooth Low Energy

Definition at line 5198 of file nrf51_bitfields.h.

◆ RADIO_MODE_MODE_Msk

#define RADIO_MODE_MODE_Msk (0x3UL << RADIO_MODE_MODE_Pos)

Bit mask of MODE field.

Definition at line 5194 of file nrf51_bitfields.h.

◆ RADIO_MODE_MODE_Nrf_1Mbit

#define RADIO_MODE_MODE_Nrf_1Mbit (0x00UL)

1Mbit/s Nordic propietary radio mode.

Definition at line 5195 of file nrf51_bitfields.h.

◆ RADIO_MODE_MODE_Nrf_250Kbit

#define RADIO_MODE_MODE_Nrf_250Kbit (0x02UL)

250kbit/s Nordic propietary radio mode.

Definition at line 5197 of file nrf51_bitfields.h.

◆ RADIO_MODE_MODE_Nrf_2Mbit

#define RADIO_MODE_MODE_Nrf_2Mbit (0x01UL)

2Mbit/s Nordic propietary radio mode.

Definition at line 5196 of file nrf51_bitfields.h.

◆ RADIO_MODE_MODE_Pos

#define RADIO_MODE_MODE_Pos (0UL)

Position of MODE field.

Definition at line 5193 of file nrf51_bitfields.h.

◆ RADIO_OVERRIDE0_OVERRIDE0_Msk

#define RADIO_OVERRIDE0_OVERRIDE0_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE0_OVERRIDE0_Pos)

Bit mask of OVERRIDE0 field.

Definition at line 5516 of file nrf51_bitfields.h.

◆ RADIO_OVERRIDE0_OVERRIDE0_Pos

#define RADIO_OVERRIDE0_OVERRIDE0_Pos (0UL)

Position of OVERRIDE0 field.

Definition at line 5515 of file nrf51_bitfields.h.

◆ RADIO_OVERRIDE1_OVERRIDE1_Msk

#define RADIO_OVERRIDE1_OVERRIDE1_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE1_OVERRIDE1_Pos)

Bit mask of OVERRIDE1 field.

Definition at line 5523 of file nrf51_bitfields.h.

◆ RADIO_OVERRIDE1_OVERRIDE1_Pos

#define RADIO_OVERRIDE1_OVERRIDE1_Pos (0UL)

Position of OVERRIDE1 field.

Definition at line 5522 of file nrf51_bitfields.h.

◆ RADIO_OVERRIDE2_OVERRIDE2_Msk

#define RADIO_OVERRIDE2_OVERRIDE2_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE2_OVERRIDE2_Pos)

Bit mask of OVERRIDE2 field.

Definition at line 5530 of file nrf51_bitfields.h.

◆ RADIO_OVERRIDE2_OVERRIDE2_Pos

#define RADIO_OVERRIDE2_OVERRIDE2_Pos (0UL)

Position of OVERRIDE2 field.

Definition at line 5529 of file nrf51_bitfields.h.

◆ RADIO_OVERRIDE3_OVERRIDE3_Msk

#define RADIO_OVERRIDE3_OVERRIDE3_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE3_OVERRIDE3_Pos)

Bit mask of OVERRIDE3 field.

Definition at line 5537 of file nrf51_bitfields.h.

◆ RADIO_OVERRIDE3_OVERRIDE3_Pos

#define RADIO_OVERRIDE3_OVERRIDE3_Pos (0UL)

Position of OVERRIDE3 field.

Definition at line 5536 of file nrf51_bitfields.h.

◆ RADIO_OVERRIDE4_ENABLE_Disabled

#define RADIO_OVERRIDE4_ENABLE_Disabled (0UL)

Override trim values disabled.

Definition at line 5545 of file nrf51_bitfields.h.

◆ RADIO_OVERRIDE4_ENABLE_Enabled

#define RADIO_OVERRIDE4_ENABLE_Enabled (1UL)

Override trim values enabled.

Definition at line 5546 of file nrf51_bitfields.h.

◆ RADIO_OVERRIDE4_ENABLE_Msk

#define RADIO_OVERRIDE4_ENABLE_Msk (0x1UL << RADIO_OVERRIDE4_ENABLE_Pos)

Bit mask of ENABLE field.

Definition at line 5544 of file nrf51_bitfields.h.

◆ RADIO_OVERRIDE4_ENABLE_Pos

#define RADIO_OVERRIDE4_ENABLE_Pos (31UL)

Position of ENABLE field.

Definition at line 5543 of file nrf51_bitfields.h.

◆ RADIO_OVERRIDE4_OVERRIDE4_Msk

#define RADIO_OVERRIDE4_OVERRIDE4_Msk (0xFFFFFFFUL << RADIO_OVERRIDE4_OVERRIDE4_Pos)

Bit mask of OVERRIDE4 field.

Definition at line 5550 of file nrf51_bitfields.h.

◆ RADIO_OVERRIDE4_OVERRIDE4_Pos

#define RADIO_OVERRIDE4_OVERRIDE4_Pos (0UL)

Position of OVERRIDE4 field.

Definition at line 5549 of file nrf51_bitfields.h.

◆ RADIO_PCNF0_LFLEN_Msk

#define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos)

Bit mask of LFLEN field.

Definition at line 5213 of file nrf51_bitfields.h.

◆ RADIO_PCNF0_LFLEN_Pos

#define RADIO_PCNF0_LFLEN_Pos (0UL)

Position of LFLEN field.

Definition at line 5212 of file nrf51_bitfields.h.

◆ RADIO_PCNF0_S0LEN_Msk

#define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos)

Bit mask of S0LEN field.

Definition at line 5209 of file nrf51_bitfields.h.

◆ RADIO_PCNF0_S0LEN_Pos

#define RADIO_PCNF0_S0LEN_Pos (8UL)

Position of S0LEN field.

Definition at line 5208 of file nrf51_bitfields.h.

◆ RADIO_PCNF0_S1LEN_Msk

#define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos)

Bit mask of S1LEN field.

Definition at line 5205 of file nrf51_bitfields.h.

◆ RADIO_PCNF0_S1LEN_Pos

#define RADIO_PCNF0_S1LEN_Pos (16UL)

Position of S1LEN field.

Definition at line 5204 of file nrf51_bitfields.h.

◆ RADIO_PCNF1_BALEN_Msk

#define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos)

Bit mask of BALEN field.

Definition at line 5232 of file nrf51_bitfields.h.

◆ RADIO_PCNF1_BALEN_Pos

#define RADIO_PCNF1_BALEN_Pos (16UL)

Position of BALEN field.

Definition at line 5231 of file nrf51_bitfields.h.

◆ RADIO_PCNF1_ENDIAN_Big

#define RADIO_PCNF1_ENDIAN_Big (1UL)

Most significant bit on air first

Definition at line 5228 of file nrf51_bitfields.h.

◆ RADIO_PCNF1_ENDIAN_Little

#define RADIO_PCNF1_ENDIAN_Little (0UL)

Least significant bit on air first

Definition at line 5227 of file nrf51_bitfields.h.

◆ RADIO_PCNF1_ENDIAN_Msk

#define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos)

Bit mask of ENDIAN field.

Definition at line 5226 of file nrf51_bitfields.h.

◆ RADIO_PCNF1_ENDIAN_Pos

#define RADIO_PCNF1_ENDIAN_Pos (24UL)

Position of ENDIAN field.

Definition at line 5225 of file nrf51_bitfields.h.

◆ RADIO_PCNF1_MAXLEN_Msk

#define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos)

Bit mask of MAXLEN field.

Definition at line 5240 of file nrf51_bitfields.h.

◆ RADIO_PCNF1_MAXLEN_Pos

#define RADIO_PCNF1_MAXLEN_Pos (0UL)

Position of MAXLEN field.

Definition at line 5239 of file nrf51_bitfields.h.

◆ RADIO_PCNF1_STATLEN_Msk

#define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos)

Bit mask of STATLEN field.

Definition at line 5236 of file nrf51_bitfields.h.

◆ RADIO_PCNF1_STATLEN_Pos

#define RADIO_PCNF1_STATLEN_Pos (8UL)

Position of STATLEN field.

Definition at line 5235 of file nrf51_bitfields.h.

◆ RADIO_PCNF1_WHITEEN_Disabled

#define RADIO_PCNF1_WHITEEN_Disabled (0UL)

Whitening disabled.

Definition at line 5221 of file nrf51_bitfields.h.

◆ RADIO_PCNF1_WHITEEN_Enabled

#define RADIO_PCNF1_WHITEEN_Enabled (1UL)

Whitening enabled.

Definition at line 5222 of file nrf51_bitfields.h.

◆ RADIO_PCNF1_WHITEEN_Msk

#define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos)

Bit mask of WHITEEN field.

Definition at line 5220 of file nrf51_bitfields.h.

◆ RADIO_PCNF1_WHITEEN_Pos

#define RADIO_PCNF1_WHITEEN_Pos (25UL)

Position of WHITEEN field.

Definition at line 5219 of file nrf51_bitfields.h.

◆ RADIO_POWER_POWER_Disabled

#define RADIO_POWER_POWER_Disabled (0UL)

Module power disabled.

Definition at line 5558 of file nrf51_bitfields.h.

◆ RADIO_POWER_POWER_Enabled

#define RADIO_POWER_POWER_Enabled (1UL)

Module power enabled.

Definition at line 5559 of file nrf51_bitfields.h.

◆ RADIO_POWER_POWER_Msk

#define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos)

Bit mask of POWER field.

Definition at line 5557 of file nrf51_bitfields.h.

◆ RADIO_POWER_POWER_Pos

#define RADIO_POWER_POWER_Pos (0UL)

Position of POWER field.

Definition at line 5556 of file nrf51_bitfields.h.

◆ RADIO_PREFIX0_AP0_Msk

#define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos)

Bit mask of AP0 field.

Definition at line 5259 of file nrf51_bitfields.h.

◆ RADIO_PREFIX0_AP0_Pos

#define RADIO_PREFIX0_AP0_Pos (0UL)

Position of AP0 field.

Definition at line 5258 of file nrf51_bitfields.h.

◆ RADIO_PREFIX0_AP1_Msk

#define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos)

Bit mask of AP1 field.

Definition at line 5255 of file nrf51_bitfields.h.

◆ RADIO_PREFIX0_AP1_Pos

#define RADIO_PREFIX0_AP1_Pos (8UL)

Position of AP1 field.

Definition at line 5254 of file nrf51_bitfields.h.

◆ RADIO_PREFIX0_AP2_Msk

#define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos)

Bit mask of AP2 field.

Definition at line 5251 of file nrf51_bitfields.h.

◆ RADIO_PREFIX0_AP2_Pos

#define RADIO_PREFIX0_AP2_Pos (16UL)

Position of AP2 field.

Definition at line 5250 of file nrf51_bitfields.h.

◆ RADIO_PREFIX0_AP3_Msk

#define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos)

Bit mask of AP3 field.

Definition at line 5247 of file nrf51_bitfields.h.

◆ RADIO_PREFIX0_AP3_Pos

#define RADIO_PREFIX0_AP3_Pos (24UL)

Position of AP3 field.

Definition at line 5246 of file nrf51_bitfields.h.

◆ RADIO_PREFIX1_AP4_Msk

#define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos)

Bit mask of AP4 field.

Definition at line 5278 of file nrf51_bitfields.h.

◆ RADIO_PREFIX1_AP4_Pos

#define RADIO_PREFIX1_AP4_Pos (0UL)

Position of AP4 field.

Definition at line 5277 of file nrf51_bitfields.h.

◆ RADIO_PREFIX1_AP5_Msk

#define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos)

Bit mask of AP5 field.

Definition at line 5274 of file nrf51_bitfields.h.

◆ RADIO_PREFIX1_AP5_Pos

#define RADIO_PREFIX1_AP5_Pos (8UL)

Position of AP5 field.

Definition at line 5273 of file nrf51_bitfields.h.

◆ RADIO_PREFIX1_AP6_Msk

#define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos)

Bit mask of AP6 field.

Definition at line 5270 of file nrf51_bitfields.h.

◆ RADIO_PREFIX1_AP6_Pos

#define RADIO_PREFIX1_AP6_Pos (16UL)

Position of AP6 field.

Definition at line 5269 of file nrf51_bitfields.h.

◆ RADIO_PREFIX1_AP7_Msk

#define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos)

Bit mask of AP7 field.

Definition at line 5266 of file nrf51_bitfields.h.

◆ RADIO_PREFIX1_AP7_Pos

#define RADIO_PREFIX1_AP7_Pos (24UL)

Position of AP7 field.

Definition at line 5265 of file nrf51_bitfields.h.

◆ RADIO_RSSISAMPLE_RSSISAMPLE_Msk

#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos)

Bit mask of RSSISAMPLE field.

Definition at line 5396 of file nrf51_bitfields.h.

◆ RADIO_RSSISAMPLE_RSSISAMPLE_Pos

#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL)

Position of RSSISAMPLE field.

Definition at line 5395 of file nrf51_bitfields.h.

◆ RADIO_RXADDRESSES_ADDR0_Disabled

#define RADIO_RXADDRESSES_ADDR0_Disabled (0UL)

Reception disabled.

Definition at line 5335 of file nrf51_bitfields.h.

◆ RADIO_RXADDRESSES_ADDR0_Enabled

#define RADIO_RXADDRESSES_ADDR0_Enabled (1UL)

Reception enabled.

Definition at line 5336 of file nrf51_bitfields.h.

◆ RADIO_RXADDRESSES_ADDR0_Msk

#define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos)

Bit mask of ADDR0 field.

Definition at line 5334 of file nrf51_bitfields.h.

◆ RADIO_RXADDRESSES_ADDR0_Pos

#define RADIO_RXADDRESSES_ADDR0_Pos (0UL)

Position of ADDR0 field.

Definition at line 5333 of file nrf51_bitfields.h.

◆ RADIO_RXADDRESSES_ADDR1_Disabled

#define RADIO_RXADDRESSES_ADDR1_Disabled (0UL)

Reception disabled.

Definition at line 5329 of file nrf51_bitfields.h.

◆ RADIO_RXADDRESSES_ADDR1_Enabled

#define RADIO_RXADDRESSES_ADDR1_Enabled (1UL)

Reception enabled.

Definition at line 5330 of file nrf51_bitfields.h.

◆ RADIO_RXADDRESSES_ADDR1_Msk

#define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos)

Bit mask of ADDR1 field.

Definition at line 5328 of file nrf51_bitfields.h.

◆ RADIO_RXADDRESSES_ADDR1_Pos

#define RADIO_RXADDRESSES_ADDR1_Pos (1UL)

Position of ADDR1 field.

Definition at line 5327 of file nrf51_bitfields.h.

◆ RADIO_RXADDRESSES_ADDR2_Disabled

#define RADIO_RXADDRESSES_ADDR2_Disabled (0UL)

Reception disabled.

Definition at line 5323 of file nrf51_bitfields.h.

◆ RADIO_RXADDRESSES_ADDR2_Enabled

#define RADIO_RXADDRESSES_ADDR2_Enabled (1UL)

Reception enabled.

Definition at line 5324 of file nrf51_bitfields.h.

◆ RADIO_RXADDRESSES_ADDR2_Msk

#define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos)

Bit mask of ADDR2 field.

Definition at line 5322 of file nrf51_bitfields.h.

◆ RADIO_RXADDRESSES_ADDR2_Pos

#define RADIO_RXADDRESSES_ADDR2_Pos (2UL)

Position of ADDR2 field.

Definition at line 5321 of file nrf51_bitfields.h.

◆ RADIO_RXADDRESSES_ADDR3_Disabled

#define RADIO_RXADDRESSES_ADDR3_Disabled (0UL)

Reception disabled.

Definition at line 5317 of file nrf51_bitfields.h.

◆ RADIO_RXADDRESSES_ADDR3_Enabled

#define RADIO_RXADDRESSES_ADDR3_Enabled (1UL)

Reception enabled.

Definition at line 5318 of file nrf51_bitfields.h.

◆ RADIO_RXADDRESSES_ADDR3_Msk

#define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos)

Bit mask of ADDR3 field.

Definition at line 5316 of file nrf51_bitfields.h.

◆ RADIO_RXADDRESSES_ADDR3_Pos

#define RADIO_RXADDRESSES_ADDR3_Pos (3UL)

Position of ADDR3 field.

Definition at line 5315 of file nrf51_bitfields.h.

◆ RADIO_RXADDRESSES_ADDR4_Disabled

#define RADIO_RXADDRESSES_ADDR4_Disabled (0UL)

Reception disabled.

Definition at line 5311 of file nrf51_bitfields.h.

◆ RADIO_RXADDRESSES_ADDR4_Enabled

#define RADIO_RXADDRESSES_ADDR4_Enabled (1UL)

Reception enabled.

Definition at line 5312 of file nrf51_bitfields.h.

◆ RADIO_RXADDRESSES_ADDR4_Msk

#define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos)

Bit mask of ADDR4 field.

Definition at line 5310 of file nrf51_bitfields.h.

◆ RADIO_RXADDRESSES_ADDR4_Pos

#define RADIO_RXADDRESSES_ADDR4_Pos (4UL)

Position of ADDR4 field.

Definition at line 5309 of file nrf51_bitfields.h.

◆ RADIO_RXADDRESSES_ADDR5_Disabled

#define RADIO_RXADDRESSES_ADDR5_Disabled (0UL)

Reception disabled.

Definition at line 5305 of file nrf51_bitfields.h.

◆ RADIO_RXADDRESSES_ADDR5_Enabled

#define RADIO_RXADDRESSES_ADDR5_Enabled (1UL)

Reception enabled.

Definition at line 5306 of file nrf51_bitfields.h.

◆ RADIO_RXADDRESSES_ADDR5_Msk

#define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos)

Bit mask of ADDR5 field.

Definition at line 5304 of file nrf51_bitfields.h.

◆ RADIO_RXADDRESSES_ADDR5_Pos

#define RADIO_RXADDRESSES_ADDR5_Pos (5UL)

Position of ADDR5 field.

Definition at line 5303 of file nrf51_bitfields.h.

◆ RADIO_RXADDRESSES_ADDR6_Disabled

#define RADIO_RXADDRESSES_ADDR6_Disabled (0UL)

Reception disabled.

Definition at line 5299 of file nrf51_bitfields.h.

◆ RADIO_RXADDRESSES_ADDR6_Enabled

#define RADIO_RXADDRESSES_ADDR6_Enabled (1UL)

Reception enabled.

Definition at line 5300 of file nrf51_bitfields.h.

◆ RADIO_RXADDRESSES_ADDR6_Msk

#define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos)

Bit mask of ADDR6 field.

Definition at line 5298 of file nrf51_bitfields.h.

◆ RADIO_RXADDRESSES_ADDR6_Pos

#define RADIO_RXADDRESSES_ADDR6_Pos (6UL)

Position of ADDR6 field.

Definition at line 5297 of file nrf51_bitfields.h.

◆ RADIO_RXADDRESSES_ADDR7_Disabled

#define RADIO_RXADDRESSES_ADDR7_Disabled (0UL)

Reception disabled.

Definition at line 5293 of file nrf51_bitfields.h.

◆ RADIO_RXADDRESSES_ADDR7_Enabled

#define RADIO_RXADDRESSES_ADDR7_Enabled (1UL)

Reception enabled.

Definition at line 5294 of file nrf51_bitfields.h.

◆ RADIO_RXADDRESSES_ADDR7_Msk

#define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos)

Bit mask of ADDR7 field.

Definition at line 5292 of file nrf51_bitfields.h.

◆ RADIO_RXADDRESSES_ADDR7_Pos

#define RADIO_RXADDRESSES_ADDR7_Pos (7UL)

Position of ADDR7 field.

Definition at line 5291 of file nrf51_bitfields.h.

◆ RADIO_RXCRC_RXCRC_Msk

#define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos)

Bit mask of RXCRC field.

Definition at line 5158 of file nrf51_bitfields.h.

◆ RADIO_RXCRC_RXCRC_Pos

#define RADIO_RXCRC_RXCRC_Pos (0UL)

Position of RXCRC field.

Definition at line 5157 of file nrf51_bitfields.h.

◆ RADIO_RXMATCH_RXMATCH_Msk

#define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos)

Bit mask of RXMATCH field.

Definition at line 5151 of file nrf51_bitfields.h.

◆ RADIO_RXMATCH_RXMATCH_Pos

#define RADIO_RXMATCH_RXMATCH_Pos (0UL)

Position of RXMATCH field.

Definition at line 5150 of file nrf51_bitfields.h.

◆ RADIO_SHORTS_ADDRESS_BCSTART_Disabled

#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL)

Shortcut disabled.

Definition at line 4959 of file nrf51_bitfields.h.

◆ RADIO_SHORTS_ADDRESS_BCSTART_Enabled

#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL)

Shortcut enabled.

Definition at line 4960 of file nrf51_bitfields.h.

◆ RADIO_SHORTS_ADDRESS_BCSTART_Msk

#define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos)

Bit mask of ADDRESS_BCSTART field.

Definition at line 4958 of file nrf51_bitfields.h.

◆ RADIO_SHORTS_ADDRESS_BCSTART_Pos

#define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL)

Position of ADDRESS_BCSTART field.

Definition at line 4957 of file nrf51_bitfields.h.

◆ RADIO_SHORTS_ADDRESS_RSSISTART_Disabled

#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL)

Shortcut disabled.

Definition at line 4971 of file nrf51_bitfields.h.

◆ RADIO_SHORTS_ADDRESS_RSSISTART_Enabled

#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL)

Shortcut enabled.

Definition at line 4972 of file nrf51_bitfields.h.

◆ RADIO_SHORTS_ADDRESS_RSSISTART_Msk

#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos)

Bit mask of ADDRESS_RSSISTART field.

Definition at line 4970 of file nrf51_bitfields.h.

◆ RADIO_SHORTS_ADDRESS_RSSISTART_Pos

#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL)

Position of ADDRESS_RSSISTART field.

Definition at line 4969 of file nrf51_bitfields.h.

◆ RADIO_SHORTS_DISABLED_RSSISTOP_Disabled

#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL)

Shortcut disabled.

Definition at line 4953 of file nrf51_bitfields.h.

◆ RADIO_SHORTS_DISABLED_RSSISTOP_Enabled

#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL)

Shortcut enabled.

Definition at line 4954 of file nrf51_bitfields.h.

◆ RADIO_SHORTS_DISABLED_RSSISTOP_Msk

#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos)

Bit mask of DISABLED_RSSISTOP field.

Definition at line 4952 of file nrf51_bitfields.h.

◆ RADIO_SHORTS_DISABLED_RSSISTOP_Pos

#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL)

Position of DISABLED_RSSISTOP field.

Definition at line 4951 of file nrf51_bitfields.h.

◆ RADIO_SHORTS_DISABLED_RXEN_Disabled

#define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL)

Shortcut disabled.

Definition at line 4977 of file nrf51_bitfields.h.

◆ RADIO_SHORTS_DISABLED_RXEN_Enabled

#define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL)

Shortcut enabled.

Definition at line 4978 of file nrf51_bitfields.h.

◆ RADIO_SHORTS_DISABLED_RXEN_Msk

#define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos)

Bit mask of DISABLED_RXEN field.

Definition at line 4976 of file nrf51_bitfields.h.

◆ RADIO_SHORTS_DISABLED_RXEN_Pos

#define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL)

Position of DISABLED_RXEN field.

Definition at line 4975 of file nrf51_bitfields.h.

◆ RADIO_SHORTS_DISABLED_TXEN_Disabled

#define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL)

Shortcut disabled.

Definition at line 4983 of file nrf51_bitfields.h.

◆ RADIO_SHORTS_DISABLED_TXEN_Enabled

#define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL)

Shortcut enabled.

Definition at line 4984 of file nrf51_bitfields.h.

◆ RADIO_SHORTS_DISABLED_TXEN_Msk

#define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos)

Bit mask of DISABLED_TXEN field.

Definition at line 4982 of file nrf51_bitfields.h.

◆ RADIO_SHORTS_DISABLED_TXEN_Pos

#define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL)

Position of DISABLED_TXEN field.

Definition at line 4981 of file nrf51_bitfields.h.

◆ RADIO_SHORTS_END_DISABLE_Disabled

#define RADIO_SHORTS_END_DISABLE_Disabled (0UL)

Shortcut disabled.

Definition at line 4989 of file nrf51_bitfields.h.

◆ RADIO_SHORTS_END_DISABLE_Enabled

#define RADIO_SHORTS_END_DISABLE_Enabled (1UL)

Shortcut enabled.

Definition at line 4990 of file nrf51_bitfields.h.

◆ RADIO_SHORTS_END_DISABLE_Msk

#define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos)

Bit mask of END_DISABLE field.

Definition at line 4988 of file nrf51_bitfields.h.

◆ RADIO_SHORTS_END_DISABLE_Pos

#define RADIO_SHORTS_END_DISABLE_Pos (1UL)

Position of END_DISABLE field.

Definition at line 4987 of file nrf51_bitfields.h.

◆ RADIO_SHORTS_END_START_Disabled

#define RADIO_SHORTS_END_START_Disabled (0UL)

Shortcut disabled.

Definition at line 4965 of file nrf51_bitfields.h.

◆ RADIO_SHORTS_END_START_Enabled

#define RADIO_SHORTS_END_START_Enabled (1UL)

Shortcut enabled.

Definition at line 4966 of file nrf51_bitfields.h.

◆ RADIO_SHORTS_END_START_Msk

#define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos)

Bit mask of END_START field.

Definition at line 4964 of file nrf51_bitfields.h.

◆ RADIO_SHORTS_END_START_Pos

#define RADIO_SHORTS_END_START_Pos (5UL)

Position of END_START field.

Definition at line 4963 of file nrf51_bitfields.h.

◆ RADIO_SHORTS_READY_START_Disabled

#define RADIO_SHORTS_READY_START_Disabled (0UL)

Shortcut disabled.

Definition at line 4995 of file nrf51_bitfields.h.

◆ RADIO_SHORTS_READY_START_Enabled

#define RADIO_SHORTS_READY_START_Enabled (1UL)

Shortcut enabled.

Definition at line 4996 of file nrf51_bitfields.h.

◆ RADIO_SHORTS_READY_START_Msk

#define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos)

Bit mask of READY_START field.

Definition at line 4994 of file nrf51_bitfields.h.

◆ RADIO_SHORTS_READY_START_Pos

#define RADIO_SHORTS_READY_START_Pos (0UL)

Position of READY_START field.

Definition at line 4993 of file nrf51_bitfields.h.

◆ RADIO_STATE_STATE_Disabled

#define RADIO_STATE_STATE_Disabled (0x00UL)

Radio is in the Disabled state.

Definition at line 5404 of file nrf51_bitfields.h.

◆ RADIO_STATE_STATE_Msk

#define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos)

Bit mask of STATE field.

Definition at line 5403 of file nrf51_bitfields.h.

◆ RADIO_STATE_STATE_Pos

#define RADIO_STATE_STATE_Pos (0UL)

Position of STATE field.

Definition at line 5402 of file nrf51_bitfields.h.

◆ RADIO_STATE_STATE_Rx

#define RADIO_STATE_STATE_Rx (0x03UL)

Radio is in the Rx state.

Definition at line 5407 of file nrf51_bitfields.h.

◆ RADIO_STATE_STATE_RxDisable

#define RADIO_STATE_STATE_RxDisable (0x04UL)

Radio is in the Rx Disable state.

Definition at line 5408 of file nrf51_bitfields.h.

◆ RADIO_STATE_STATE_RxIdle

#define RADIO_STATE_STATE_RxIdle (0x02UL)

Radio is in the Rx Idle state.

Definition at line 5406 of file nrf51_bitfields.h.

◆ RADIO_STATE_STATE_RxRu

#define RADIO_STATE_STATE_RxRu (0x01UL)

Radio is in the Rx Ramp Up state.

Definition at line 5405 of file nrf51_bitfields.h.

◆ RADIO_STATE_STATE_Tx

#define RADIO_STATE_STATE_Tx (0x0BUL)

Radio is in the Tx state.

Definition at line 5411 of file nrf51_bitfields.h.

◆ RADIO_STATE_STATE_TxDisable

#define RADIO_STATE_STATE_TxDisable (0x0CUL)

Radio is in the Tx Disable state.

Definition at line 5412 of file nrf51_bitfields.h.

◆ RADIO_STATE_STATE_TxIdle

#define RADIO_STATE_STATE_TxIdle (0x0AUL)

Radio is in the Tx Idle state.

Definition at line 5410 of file nrf51_bitfields.h.

◆ RADIO_STATE_STATE_TxRu

#define RADIO_STATE_STATE_TxRu (0x09UL)

Radio is in the Tx Ramp Up state.

Definition at line 5409 of file nrf51_bitfields.h.

◆ RADIO_TEST_CONSTCARRIER_Disabled

#define RADIO_TEST_CONSTCARRIER_Disabled (0UL)

Constant carrier disabled.

Definition at line 5381 of file nrf51_bitfields.h.

◆ RADIO_TEST_CONSTCARRIER_Enabled

#define RADIO_TEST_CONSTCARRIER_Enabled (1UL)

Constant carrier enabled.

Definition at line 5382 of file nrf51_bitfields.h.

◆ RADIO_TEST_CONSTCARRIER_Msk

#define RADIO_TEST_CONSTCARRIER_Msk (0x1UL << RADIO_TEST_CONSTCARRIER_Pos)

Bit mask of CONSTCARRIER field.

Definition at line 5380 of file nrf51_bitfields.h.

◆ RADIO_TEST_CONSTCARRIER_Pos

#define RADIO_TEST_CONSTCARRIER_Pos (0UL)

Position of CONSTCARRIER field.

Definition at line 5379 of file nrf51_bitfields.h.

◆ RADIO_TEST_PLLLOCK_Disabled

#define RADIO_TEST_PLLLOCK_Disabled (0UL)

PLL lock disabled.

Definition at line 5375 of file nrf51_bitfields.h.

◆ RADIO_TEST_PLLLOCK_Enabled

#define RADIO_TEST_PLLLOCK_Enabled (1UL)

PLL lock enabled.

Definition at line 5376 of file nrf51_bitfields.h.

◆ RADIO_TEST_PLLLOCK_Msk

#define RADIO_TEST_PLLLOCK_Msk (0x1UL << RADIO_TEST_PLLLOCK_Pos)

Bit mask of PLLLOCK field.

Definition at line 5374 of file nrf51_bitfields.h.

◆ RADIO_TEST_PLLLOCK_Pos

#define RADIO_TEST_PLLLOCK_Pos (1UL)

Position of PLLLOCK field.

Definition at line 5373 of file nrf51_bitfields.h.

◆ RADIO_TIFS_TIFS_Msk

#define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos)

Bit mask of TIFS field.

Definition at line 5389 of file nrf51_bitfields.h.

◆ RADIO_TIFS_TIFS_Pos

#define RADIO_TIFS_TIFS_Pos (0UL)

Position of TIFS field.

Definition at line 5388 of file nrf51_bitfields.h.

◆ RADIO_TXADDRESS_TXADDRESS_Msk

#define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos)

Bit mask of TXADDRESS field.

Definition at line 5285 of file nrf51_bitfields.h.

◆ RADIO_TXADDRESS_TXADDRESS_Pos

#define RADIO_TXADDRESS_TXADDRESS_Pos (0UL)

Position of TXADDRESS field.

Definition at line 5284 of file nrf51_bitfields.h.

◆ RADIO_TXPOWER_TXPOWER_0dBm

#define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL)

0dBm.

Definition at line 5180 of file nrf51_bitfields.h.

◆ RADIO_TXPOWER_TXPOWER_Msk

#define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos)

Bit mask of TXPOWER field.

Definition at line 5179 of file nrf51_bitfields.h.

◆ RADIO_TXPOWER_TXPOWER_Neg12dBm

#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL)

-12dBm.

Definition at line 5185 of file nrf51_bitfields.h.

◆ RADIO_TXPOWER_TXPOWER_Neg16dBm

#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL)

-16dBm.

Definition at line 5184 of file nrf51_bitfields.h.

◆ RADIO_TXPOWER_TXPOWER_Neg20dBm

#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL)

-20dBm.

Definition at line 5183 of file nrf51_bitfields.h.

◆ RADIO_TXPOWER_TXPOWER_Neg30dBm

#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL)

-30dBm.

Definition at line 5182 of file nrf51_bitfields.h.

◆ RADIO_TXPOWER_TXPOWER_Neg4dBm

#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL)

-4dBm.

Definition at line 5187 of file nrf51_bitfields.h.

◆ RADIO_TXPOWER_TXPOWER_Neg8dBm

#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL)

-8dBm.

Definition at line 5186 of file nrf51_bitfields.h.

◆ RADIO_TXPOWER_TXPOWER_Pos

#define RADIO_TXPOWER_TXPOWER_Pos (0UL)

Position of TXPOWER field.

Definition at line 5178 of file nrf51_bitfields.h.

◆ RADIO_TXPOWER_TXPOWER_Pos4dBm

#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL)

+4dBm.

Definition at line 5181 of file nrf51_bitfields.h.

◆ RNG_CONFIG_DERCEN_Disabled

#define RNG_CONFIG_DERCEN_Disabled (0UL)

Digital error correction disabled.

Definition at line 5600 of file nrf51_bitfields.h.

◆ RNG_CONFIG_DERCEN_Enabled

#define RNG_CONFIG_DERCEN_Enabled (1UL)

Digital error correction enabled.

Definition at line 5601 of file nrf51_bitfields.h.

◆ RNG_CONFIG_DERCEN_Msk

#define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos)

Bit mask of DERCEN field.

Definition at line 5599 of file nrf51_bitfields.h.

◆ RNG_CONFIG_DERCEN_Pos

#define RNG_CONFIG_DERCEN_Pos (0UL)

Position of DERCEN field.

Definition at line 5598 of file nrf51_bitfields.h.

◆ RNG_INTENCLR_VALRDY_Clear

#define RNG_INTENCLR_VALRDY_Clear (1UL)

Disable interrupt on write.

Definition at line 5592 of file nrf51_bitfields.h.

◆ RNG_INTENCLR_VALRDY_Disabled

#define RNG_INTENCLR_VALRDY_Disabled (0UL)

Interrupt disabled.

Definition at line 5590 of file nrf51_bitfields.h.

◆ RNG_INTENCLR_VALRDY_Enabled

#define RNG_INTENCLR_VALRDY_Enabled (1UL)

Interrupt enabled.

Definition at line 5591 of file nrf51_bitfields.h.

◆ RNG_INTENCLR_VALRDY_Msk

#define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos)

Bit mask of VALRDY field.

Definition at line 5589 of file nrf51_bitfields.h.

◆ RNG_INTENCLR_VALRDY_Pos

#define RNG_INTENCLR_VALRDY_Pos (0UL)

Position of VALRDY field.

Definition at line 5588 of file nrf51_bitfields.h.

◆ RNG_INTENSET_VALRDY_Disabled

#define RNG_INTENSET_VALRDY_Disabled (0UL)

Interrupt disabled.

Definition at line 5580 of file nrf51_bitfields.h.

◆ RNG_INTENSET_VALRDY_Enabled

#define RNG_INTENSET_VALRDY_Enabled (1UL)

Interrupt enabled.

Definition at line 5581 of file nrf51_bitfields.h.

◆ RNG_INTENSET_VALRDY_Msk

#define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos)

Bit mask of VALRDY field.

Definition at line 5579 of file nrf51_bitfields.h.

◆ RNG_INTENSET_VALRDY_Pos

#define RNG_INTENSET_VALRDY_Pos (0UL)

Position of VALRDY field.

Definition at line 5578 of file nrf51_bitfields.h.

◆ RNG_INTENSET_VALRDY_Set

#define RNG_INTENSET_VALRDY_Set (1UL)

Enable interrupt on write.

Definition at line 5582 of file nrf51_bitfields.h.

◆ RNG_POWER_POWER_Disabled

#define RNG_POWER_POWER_Disabled (0UL)

Module power disabled.

Definition at line 5616 of file nrf51_bitfields.h.

◆ RNG_POWER_POWER_Enabled

#define RNG_POWER_POWER_Enabled (1UL)

Module power enabled.

Definition at line 5617 of file nrf51_bitfields.h.

◆ RNG_POWER_POWER_Msk

#define RNG_POWER_POWER_Msk (0x1UL << RNG_POWER_POWER_Pos)

Bit mask of POWER field.

Definition at line 5615 of file nrf51_bitfields.h.

◆ RNG_POWER_POWER_Pos

#define RNG_POWER_POWER_Pos (0UL)

Position of POWER field.

Definition at line 5614 of file nrf51_bitfields.h.

◆ RNG_SHORTS_VALRDY_STOP_Disabled

#define RNG_SHORTS_VALRDY_STOP_Disabled (0UL)

Shortcut disabled.

Definition at line 5571 of file nrf51_bitfields.h.

◆ RNG_SHORTS_VALRDY_STOP_Enabled

#define RNG_SHORTS_VALRDY_STOP_Enabled (1UL)

Shortcut enabled.

Definition at line 5572 of file nrf51_bitfields.h.

◆ RNG_SHORTS_VALRDY_STOP_Msk

#define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos)

Bit mask of VALRDY_STOP field.

Definition at line 5570 of file nrf51_bitfields.h.

◆ RNG_SHORTS_VALRDY_STOP_Pos

#define RNG_SHORTS_VALRDY_STOP_Pos (0UL)

Position of VALRDY_STOP field.

Definition at line 5569 of file nrf51_bitfields.h.

◆ RNG_VALUE_VALUE_Msk

#define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos)

Bit mask of VALUE field.

Definition at line 5608 of file nrf51_bitfields.h.

◆ RNG_VALUE_VALUE_Pos

#define RNG_VALUE_VALUE_Pos (0UL)

Position of VALUE field.

Definition at line 5607 of file nrf51_bitfields.h.

◆ RTC_CC_COMPARE_Msk

#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos)

Bit mask of COMPARE field.

Definition at line 5861 of file nrf51_bitfields.h.

◆ RTC_CC_COMPARE_Pos

#define RTC_CC_COMPARE_Pos (0UL)

Position of COMPARE field.

Definition at line 5860 of file nrf51_bitfields.h.

◆ RTC_COUNTER_COUNTER_Msk

#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos)

Bit mask of COUNTER field.

Definition at line 5847 of file nrf51_bitfields.h.

◆ RTC_COUNTER_COUNTER_Pos

#define RTC_COUNTER_COUNTER_Pos (0UL)

Position of COUNTER field.

Definition at line 5846 of file nrf51_bitfields.h.

◆ RTC_EVTEN_COMPARE0_Disabled

#define RTC_EVTEN_COMPARE0_Disabled (0UL)

Event disabled.

Definition at line 5737 of file nrf51_bitfields.h.

◆ RTC_EVTEN_COMPARE0_Enabled

#define RTC_EVTEN_COMPARE0_Enabled (1UL)

Event enabled.

Definition at line 5738 of file nrf51_bitfields.h.

◆ RTC_EVTEN_COMPARE0_Msk

#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos)

Bit mask of COMPARE0 field.

Definition at line 5736 of file nrf51_bitfields.h.

◆ RTC_EVTEN_COMPARE0_Pos

#define RTC_EVTEN_COMPARE0_Pos (16UL)

Position of COMPARE0 field.

Definition at line 5735 of file nrf51_bitfields.h.

◆ RTC_EVTEN_COMPARE1_Disabled

#define RTC_EVTEN_COMPARE1_Disabled (0UL)

Event disabled.

Definition at line 5731 of file nrf51_bitfields.h.

◆ RTC_EVTEN_COMPARE1_Enabled

#define RTC_EVTEN_COMPARE1_Enabled (1UL)

Event enabled.

Definition at line 5732 of file nrf51_bitfields.h.

◆ RTC_EVTEN_COMPARE1_Msk

#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos)

Bit mask of COMPARE1 field.

Definition at line 5730 of file nrf51_bitfields.h.

◆ RTC_EVTEN_COMPARE1_Pos

#define RTC_EVTEN_COMPARE1_Pos (17UL)

Position of COMPARE1 field.

Definition at line 5729 of file nrf51_bitfields.h.

◆ RTC_EVTEN_COMPARE2_Disabled

#define RTC_EVTEN_COMPARE2_Disabled (0UL)

Event disabled.

Definition at line 5725 of file nrf51_bitfields.h.

◆ RTC_EVTEN_COMPARE2_Enabled

#define RTC_EVTEN_COMPARE2_Enabled (1UL)

Event enabled.

Definition at line 5726 of file nrf51_bitfields.h.

◆ RTC_EVTEN_COMPARE2_Msk

#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos)

Bit mask of COMPARE2 field.

Definition at line 5724 of file nrf51_bitfields.h.

◆ RTC_EVTEN_COMPARE2_Pos

#define RTC_EVTEN_COMPARE2_Pos (18UL)

Position of COMPARE2 field.

Definition at line 5723 of file nrf51_bitfields.h.

◆ RTC_EVTEN_COMPARE3_Disabled

#define RTC_EVTEN_COMPARE3_Disabled (0UL)

Event disabled.

Definition at line 5719 of file nrf51_bitfields.h.

◆ RTC_EVTEN_COMPARE3_Enabled

#define RTC_EVTEN_COMPARE3_Enabled (1UL)

Event enabled.

Definition at line 5720 of file nrf51_bitfields.h.

◆ RTC_EVTEN_COMPARE3_Msk

#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos)

Bit mask of COMPARE3 field.

Definition at line 5718 of file nrf51_bitfields.h.

◆ RTC_EVTEN_COMPARE3_Pos

#define RTC_EVTEN_COMPARE3_Pos (19UL)

Position of COMPARE3 field.

Definition at line 5717 of file nrf51_bitfields.h.

◆ RTC_EVTEN_OVRFLW_Disabled

#define RTC_EVTEN_OVRFLW_Disabled (0UL)

Event disabled.

Definition at line 5743 of file nrf51_bitfields.h.

◆ RTC_EVTEN_OVRFLW_Enabled

#define RTC_EVTEN_OVRFLW_Enabled (1UL)

Event enabled.

Definition at line 5744 of file nrf51_bitfields.h.

◆ RTC_EVTEN_OVRFLW_Msk

#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos)

Bit mask of OVRFLW field.

Definition at line 5742 of file nrf51_bitfields.h.

◆ RTC_EVTEN_OVRFLW_Pos

#define RTC_EVTEN_OVRFLW_Pos (1UL)

Position of OVRFLW field.

Definition at line 5741 of file nrf51_bitfields.h.

◆ RTC_EVTEN_TICK_Disabled

#define RTC_EVTEN_TICK_Disabled (0UL)

Event disabled.

Definition at line 5749 of file nrf51_bitfields.h.

◆ RTC_EVTEN_TICK_Enabled

#define RTC_EVTEN_TICK_Enabled (1UL)

Event enabled.

Definition at line 5750 of file nrf51_bitfields.h.

◆ RTC_EVTEN_TICK_Msk

#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos)

Bit mask of TICK field.

Definition at line 5748 of file nrf51_bitfields.h.

◆ RTC_EVTEN_TICK_Pos

#define RTC_EVTEN_TICK_Pos (0UL)

Position of TICK field.

Definition at line 5747 of file nrf51_bitfields.h.

◆ RTC_EVTENCLR_COMPARE0_Clear

#define RTC_EVTENCLR_COMPARE0_Clear (1UL)

Disable event on write.

Definition at line 5826 of file nrf51_bitfields.h.

◆ RTC_EVTENCLR_COMPARE0_Disabled

#define RTC_EVTENCLR_COMPARE0_Disabled (0UL)

Event disabled.

Definition at line 5824 of file nrf51_bitfields.h.

◆ RTC_EVTENCLR_COMPARE0_Enabled

#define RTC_EVTENCLR_COMPARE0_Enabled (1UL)

Event enabled.

Definition at line 5825 of file nrf51_bitfields.h.

◆ RTC_EVTENCLR_COMPARE0_Msk

#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos)

Bit mask of COMPARE0 field.

Definition at line 5823 of file nrf51_bitfields.h.

◆ RTC_EVTENCLR_COMPARE0_Pos

#define RTC_EVTENCLR_COMPARE0_Pos (16UL)

Position of COMPARE0 field.

Definition at line 5822 of file nrf51_bitfields.h.

◆ RTC_EVTENCLR_COMPARE1_Clear

#define RTC_EVTENCLR_COMPARE1_Clear (1UL)

Disable event on write.

Definition at line 5819 of file nrf51_bitfields.h.

◆ RTC_EVTENCLR_COMPARE1_Disabled

#define RTC_EVTENCLR_COMPARE1_Disabled (0UL)

Event disabled.

Definition at line 5817 of file nrf51_bitfields.h.

◆ RTC_EVTENCLR_COMPARE1_Enabled

#define RTC_EVTENCLR_COMPARE1_Enabled (1UL)

Event enabled.

Definition at line 5818 of file nrf51_bitfields.h.

◆ RTC_EVTENCLR_COMPARE1_Msk

#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos)

Bit mask of COMPARE1 field.

Definition at line 5816 of file nrf51_bitfields.h.

◆ RTC_EVTENCLR_COMPARE1_Pos

#define RTC_EVTENCLR_COMPARE1_Pos (17UL)

Position of COMPARE1 field.

Definition at line 5815 of file nrf51_bitfields.h.

◆ RTC_EVTENCLR_COMPARE2_Clear

#define RTC_EVTENCLR_COMPARE2_Clear (1UL)

Disable event on write.

Definition at line 5812 of file nrf51_bitfields.h.

◆ RTC_EVTENCLR_COMPARE2_Disabled

#define RTC_EVTENCLR_COMPARE2_Disabled (0UL)

Event disabled.

Definition at line 5810 of file nrf51_bitfields.h.

◆ RTC_EVTENCLR_COMPARE2_Enabled

#define RTC_EVTENCLR_COMPARE2_Enabled (1UL)

Event enabled.

Definition at line 5811 of file nrf51_bitfields.h.

◆ RTC_EVTENCLR_COMPARE2_Msk

#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos)

Bit mask of COMPARE2 field.

Definition at line 5809 of file nrf51_bitfields.h.

◆ RTC_EVTENCLR_COMPARE2_Pos

#define RTC_EVTENCLR_COMPARE2_Pos (18UL)

Position of COMPARE2 field.

Definition at line 5808 of file nrf51_bitfields.h.

◆ RTC_EVTENCLR_COMPARE3_Clear

#define RTC_EVTENCLR_COMPARE3_Clear (1UL)

Disable event on write.

Definition at line 5805 of file nrf51_bitfields.h.

◆ RTC_EVTENCLR_COMPARE3_Disabled

#define RTC_EVTENCLR_COMPARE3_Disabled (0UL)

Event disabled.

Definition at line 5803 of file nrf51_bitfields.h.

◆ RTC_EVTENCLR_COMPARE3_Enabled

#define RTC_EVTENCLR_COMPARE3_Enabled (1UL)

Event enabled.

Definition at line 5804 of file nrf51_bitfields.h.

◆ RTC_EVTENCLR_COMPARE3_Msk

#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos)

Bit mask of COMPARE3 field.

Definition at line 5802 of file nrf51_bitfields.h.

◆ RTC_EVTENCLR_COMPARE3_Pos

#define RTC_EVTENCLR_COMPARE3_Pos (19UL)

Position of COMPARE3 field.

Definition at line 5801 of file nrf51_bitfields.h.

◆ RTC_EVTENCLR_OVRFLW_Clear

#define RTC_EVTENCLR_OVRFLW_Clear (1UL)

Disable event on write.

Definition at line 5833 of file nrf51_bitfields.h.

◆ RTC_EVTENCLR_OVRFLW_Disabled

#define RTC_EVTENCLR_OVRFLW_Disabled (0UL)

Event disabled.

Definition at line 5831 of file nrf51_bitfields.h.

◆ RTC_EVTENCLR_OVRFLW_Enabled

#define RTC_EVTENCLR_OVRFLW_Enabled (1UL)

Event enabled.

Definition at line 5832 of file nrf51_bitfields.h.

◆ RTC_EVTENCLR_OVRFLW_Msk

#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos)

Bit mask of OVRFLW field.

Definition at line 5830 of file nrf51_bitfields.h.

◆ RTC_EVTENCLR_OVRFLW_Pos

#define RTC_EVTENCLR_OVRFLW_Pos (1UL)

Position of OVRFLW field.

Definition at line 5829 of file nrf51_bitfields.h.

◆ RTC_EVTENCLR_TICK_Clear

#define RTC_EVTENCLR_TICK_Clear (1UL)

Disable event on write.

Definition at line 5840 of file nrf51_bitfields.h.

◆ RTC_EVTENCLR_TICK_Disabled

#define RTC_EVTENCLR_TICK_Disabled (0UL)

Event disabled.

Definition at line 5838 of file nrf51_bitfields.h.

◆ RTC_EVTENCLR_TICK_Enabled

#define RTC_EVTENCLR_TICK_Enabled (1UL)

Event enabled.

Definition at line 5839 of file nrf51_bitfields.h.

◆ RTC_EVTENCLR_TICK_Msk

#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos)

Bit mask of TICK field.

Definition at line 5837 of file nrf51_bitfields.h.

◆ RTC_EVTENCLR_TICK_Pos

#define RTC_EVTENCLR_TICK_Pos (0UL)

Position of TICK field.

Definition at line 5836 of file nrf51_bitfields.h.

◆ RTC_EVTENSET_COMPARE0_Disabled

#define RTC_EVTENSET_COMPARE0_Disabled (0UL)

Event disabled.

Definition at line 5779 of file nrf51_bitfields.h.

◆ RTC_EVTENSET_COMPARE0_Enabled

#define RTC_EVTENSET_COMPARE0_Enabled (1UL)

Event enabled.

Definition at line 5780 of file nrf51_bitfields.h.

◆ RTC_EVTENSET_COMPARE0_Msk

#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos)

Bit mask of COMPARE0 field.

Definition at line 5778 of file nrf51_bitfields.h.

◆ RTC_EVTENSET_COMPARE0_Pos

#define RTC_EVTENSET_COMPARE0_Pos (16UL)

Position of COMPARE0 field.

Definition at line 5777 of file nrf51_bitfields.h.

◆ RTC_EVTENSET_COMPARE0_Set

#define RTC_EVTENSET_COMPARE0_Set (1UL)

Enable event on write.

Definition at line 5781 of file nrf51_bitfields.h.

◆ RTC_EVTENSET_COMPARE1_Disabled

#define RTC_EVTENSET_COMPARE1_Disabled (0UL)

Event disabled.

Definition at line 5772 of file nrf51_bitfields.h.

◆ RTC_EVTENSET_COMPARE1_Enabled

#define RTC_EVTENSET_COMPARE1_Enabled (1UL)

Event enabled.

Definition at line 5773 of file nrf51_bitfields.h.

◆ RTC_EVTENSET_COMPARE1_Msk

#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos)

Bit mask of COMPARE1 field.

Definition at line 5771 of file nrf51_bitfields.h.

◆ RTC_EVTENSET_COMPARE1_Pos

#define RTC_EVTENSET_COMPARE1_Pos (17UL)

Position of COMPARE1 field.

Definition at line 5770 of file nrf51_bitfields.h.

◆ RTC_EVTENSET_COMPARE1_Set

#define RTC_EVTENSET_COMPARE1_Set (1UL)

Enable event on write.

Definition at line 5774 of file nrf51_bitfields.h.

◆ RTC_EVTENSET_COMPARE2_Disabled

#define RTC_EVTENSET_COMPARE2_Disabled (0UL)

Event disabled.

Definition at line 5765 of file nrf51_bitfields.h.

◆ RTC_EVTENSET_COMPARE2_Enabled

#define RTC_EVTENSET_COMPARE2_Enabled (1UL)

Event enabled.

Definition at line 5766 of file nrf51_bitfields.h.

◆ RTC_EVTENSET_COMPARE2_Msk

#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos)

Bit mask of COMPARE2 field.

Definition at line 5764 of file nrf51_bitfields.h.

◆ RTC_EVTENSET_COMPARE2_Pos

#define RTC_EVTENSET_COMPARE2_Pos (18UL)

Position of COMPARE2 field.

Definition at line 5763 of file nrf51_bitfields.h.

◆ RTC_EVTENSET_COMPARE2_Set

#define RTC_EVTENSET_COMPARE2_Set (1UL)

Enable event on write.

Definition at line 5767 of file nrf51_bitfields.h.

◆ RTC_EVTENSET_COMPARE3_Disabled

#define RTC_EVTENSET_COMPARE3_Disabled (0UL)

Event disabled.

Definition at line 5758 of file nrf51_bitfields.h.

◆ RTC_EVTENSET_COMPARE3_Enabled

#define RTC_EVTENSET_COMPARE3_Enabled (1UL)

Event enabled.

Definition at line 5759 of file nrf51_bitfields.h.

◆ RTC_EVTENSET_COMPARE3_Msk

#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos)

Bit mask of COMPARE3 field.

Definition at line 5757 of file nrf51_bitfields.h.

◆ RTC_EVTENSET_COMPARE3_Pos

#define RTC_EVTENSET_COMPARE3_Pos (19UL)

Position of COMPARE3 field.

Definition at line 5756 of file nrf51_bitfields.h.

◆ RTC_EVTENSET_COMPARE3_Set

#define RTC_EVTENSET_COMPARE3_Set (1UL)

Enable event on write.

Definition at line 5760 of file nrf51_bitfields.h.

◆ RTC_EVTENSET_OVRFLW_Disabled

#define RTC_EVTENSET_OVRFLW_Disabled (0UL)

Event disabled.

Definition at line 5786 of file nrf51_bitfields.h.

◆ RTC_EVTENSET_OVRFLW_Enabled

#define RTC_EVTENSET_OVRFLW_Enabled (1UL)

Event enabled.

Definition at line 5787 of file nrf51_bitfields.h.

◆ RTC_EVTENSET_OVRFLW_Msk

#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos)

Bit mask of OVRFLW field.

Definition at line 5785 of file nrf51_bitfields.h.

◆ RTC_EVTENSET_OVRFLW_Pos

#define RTC_EVTENSET_OVRFLW_Pos (1UL)

Position of OVRFLW field.

Definition at line 5784 of file nrf51_bitfields.h.

◆ RTC_EVTENSET_OVRFLW_Set

#define RTC_EVTENSET_OVRFLW_Set (1UL)

Enable event on write.

Definition at line 5788 of file nrf51_bitfields.h.

◆ RTC_EVTENSET_TICK_Disabled

#define RTC_EVTENSET_TICK_Disabled (0UL)

Event disabled.

Definition at line 5793 of file nrf51_bitfields.h.

◆ RTC_EVTENSET_TICK_Enabled

#define RTC_EVTENSET_TICK_Enabled (1UL)

Event enabled.

Definition at line 5794 of file nrf51_bitfields.h.

◆ RTC_EVTENSET_TICK_Msk

#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos)

Bit mask of TICK field.

Definition at line 5792 of file nrf51_bitfields.h.

◆ RTC_EVTENSET_TICK_Pos

#define RTC_EVTENSET_TICK_Pos (0UL)

Position of TICK field.

Definition at line 5791 of file nrf51_bitfields.h.

◆ RTC_EVTENSET_TICK_Set

#define RTC_EVTENSET_TICK_Set (1UL)

Enable event on write.

Definition at line 5795 of file nrf51_bitfields.h.

◆ RTC_INTENCLR_COMPARE0_Clear

#define RTC_INTENCLR_COMPARE0_Clear (1UL)

Disable interrupt on write.

Definition at line 5697 of file nrf51_bitfields.h.

◆ RTC_INTENCLR_COMPARE0_Disabled

#define RTC_INTENCLR_COMPARE0_Disabled (0UL)

Interrupt disabled.

Definition at line 5695 of file nrf51_bitfields.h.

◆ RTC_INTENCLR_COMPARE0_Enabled

#define RTC_INTENCLR_COMPARE0_Enabled (1UL)

Interrupt enabled.

Definition at line 5696 of file nrf51_bitfields.h.

◆ RTC_INTENCLR_COMPARE0_Msk

#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos)

Bit mask of COMPARE0 field.

Definition at line 5694 of file nrf51_bitfields.h.

◆ RTC_INTENCLR_COMPARE0_Pos

#define RTC_INTENCLR_COMPARE0_Pos (16UL)

Position of COMPARE0 field.

Definition at line 5693 of file nrf51_bitfields.h.

◆ RTC_INTENCLR_COMPARE1_Clear

#define RTC_INTENCLR_COMPARE1_Clear (1UL)

Disable interrupt on write.

Definition at line 5690 of file nrf51_bitfields.h.

◆ RTC_INTENCLR_COMPARE1_Disabled

#define RTC_INTENCLR_COMPARE1_Disabled (0UL)

Interrupt disabled.

Definition at line 5688 of file nrf51_bitfields.h.

◆ RTC_INTENCLR_COMPARE1_Enabled

#define RTC_INTENCLR_COMPARE1_Enabled (1UL)

Interrupt enabled.

Definition at line 5689 of file nrf51_bitfields.h.

◆ RTC_INTENCLR_COMPARE1_Msk

#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos)

Bit mask of COMPARE1 field.

Definition at line 5687 of file nrf51_bitfields.h.

◆ RTC_INTENCLR_COMPARE1_Pos

#define RTC_INTENCLR_COMPARE1_Pos (17UL)

Position of COMPARE1 field.

Definition at line 5686 of file nrf51_bitfields.h.

◆ RTC_INTENCLR_COMPARE2_Clear

#define RTC_INTENCLR_COMPARE2_Clear (1UL)

Disable interrupt on write.

Definition at line 5683 of file nrf51_bitfields.h.

◆ RTC_INTENCLR_COMPARE2_Disabled

#define RTC_INTENCLR_COMPARE2_Disabled (0UL)

Interrupt disabled.

Definition at line 5681 of file nrf51_bitfields.h.

◆ RTC_INTENCLR_COMPARE2_Enabled

#define RTC_INTENCLR_COMPARE2_Enabled (1UL)

Interrupt enabled.

Definition at line 5682 of file nrf51_bitfields.h.

◆ RTC_INTENCLR_COMPARE2_Msk

#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos)

Bit mask of COMPARE2 field.

Definition at line 5680 of file nrf51_bitfields.h.

◆ RTC_INTENCLR_COMPARE2_Pos

#define RTC_INTENCLR_COMPARE2_Pos (18UL)

Position of COMPARE2 field.

Definition at line 5679 of file nrf51_bitfields.h.

◆ RTC_INTENCLR_COMPARE3_Clear

#define RTC_INTENCLR_COMPARE3_Clear (1UL)

Disable interrupt on write.

Definition at line 5676 of file nrf51_bitfields.h.

◆ RTC_INTENCLR_COMPARE3_Disabled

#define RTC_INTENCLR_COMPARE3_Disabled (0UL)

Interrupt disabled.

Definition at line 5674 of file nrf51_bitfields.h.

◆ RTC_INTENCLR_COMPARE3_Enabled

#define RTC_INTENCLR_COMPARE3_Enabled (1UL)

Interrupt enabled.

Definition at line 5675 of file nrf51_bitfields.h.

◆ RTC_INTENCLR_COMPARE3_Msk

#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos)

Bit mask of COMPARE3 field.

Definition at line 5673 of file nrf51_bitfields.h.

◆ RTC_INTENCLR_COMPARE3_Pos

#define RTC_INTENCLR_COMPARE3_Pos (19UL)

Position of COMPARE3 field.

Definition at line 5672 of file nrf51_bitfields.h.

◆ RTC_INTENCLR_OVRFLW_Clear

#define RTC_INTENCLR_OVRFLW_Clear (1UL)

Disable interrupt on write.

Definition at line 5704 of file nrf51_bitfields.h.

◆ RTC_INTENCLR_OVRFLW_Disabled

#define RTC_INTENCLR_OVRFLW_Disabled (0UL)

Interrupt disabled.

Definition at line 5702 of file nrf51_bitfields.h.

◆ RTC_INTENCLR_OVRFLW_Enabled

#define RTC_INTENCLR_OVRFLW_Enabled (1UL)

Interrupt enabled.

Definition at line 5703 of file nrf51_bitfields.h.

◆ RTC_INTENCLR_OVRFLW_Msk

#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos)

Bit mask of OVRFLW field.

Definition at line 5701 of file nrf51_bitfields.h.

◆ RTC_INTENCLR_OVRFLW_Pos

#define RTC_INTENCLR_OVRFLW_Pos (1UL)

Position of OVRFLW field.

Definition at line 5700 of file nrf51_bitfields.h.

◆ RTC_INTENCLR_TICK_Clear

#define RTC_INTENCLR_TICK_Clear (1UL)

Disable interrupt on write.

Definition at line 5711 of file nrf51_bitfields.h.

◆ RTC_INTENCLR_TICK_Disabled

#define RTC_INTENCLR_TICK_Disabled (0UL)

Interrupt disabled.

Definition at line 5709 of file nrf51_bitfields.h.

◆ RTC_INTENCLR_TICK_Enabled

#define RTC_INTENCLR_TICK_Enabled (1UL)

Interrupt enabled.

Definition at line 5710 of file nrf51_bitfields.h.

◆ RTC_INTENCLR_TICK_Msk

#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos)

Bit mask of TICK field.

Definition at line 5708 of file nrf51_bitfields.h.

◆ RTC_INTENCLR_TICK_Pos

#define RTC_INTENCLR_TICK_Pos (0UL)

Position of TICK field.

Definition at line 5707 of file nrf51_bitfields.h.

◆ RTC_INTENSET_COMPARE0_Disabled

#define RTC_INTENSET_COMPARE0_Disabled (0UL)

Interrupt disabled.

Definition at line 5650 of file nrf51_bitfields.h.

◆ RTC_INTENSET_COMPARE0_Enabled

#define RTC_INTENSET_COMPARE0_Enabled (1UL)

Interrupt enabled.

Definition at line 5651 of file nrf51_bitfields.h.

◆ RTC_INTENSET_COMPARE0_Msk

#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos)

Bit mask of COMPARE0 field.

Definition at line 5649 of file nrf51_bitfields.h.

◆ RTC_INTENSET_COMPARE0_Pos

#define RTC_INTENSET_COMPARE0_Pos (16UL)

Position of COMPARE0 field.

Definition at line 5648 of file nrf51_bitfields.h.

◆ RTC_INTENSET_COMPARE0_Set

#define RTC_INTENSET_COMPARE0_Set (1UL)

Enable interrupt on write.

Definition at line 5652 of file nrf51_bitfields.h.

◆ RTC_INTENSET_COMPARE1_Disabled

#define RTC_INTENSET_COMPARE1_Disabled (0UL)

Interrupt disabled.

Definition at line 5643 of file nrf51_bitfields.h.

◆ RTC_INTENSET_COMPARE1_Enabled

#define RTC_INTENSET_COMPARE1_Enabled (1UL)

Interrupt enabled.

Definition at line 5644 of file nrf51_bitfields.h.

◆ RTC_INTENSET_COMPARE1_Msk

#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos)

Bit mask of COMPARE1 field.

Definition at line 5642 of file nrf51_bitfields.h.

◆ RTC_INTENSET_COMPARE1_Pos

#define RTC_INTENSET_COMPARE1_Pos (17UL)

Position of COMPARE1 field.

Definition at line 5641 of file nrf51_bitfields.h.

◆ RTC_INTENSET_COMPARE1_Set

#define RTC_INTENSET_COMPARE1_Set (1UL)

Enable interrupt on write.

Definition at line 5645 of file nrf51_bitfields.h.

◆ RTC_INTENSET_COMPARE2_Disabled

#define RTC_INTENSET_COMPARE2_Disabled (0UL)

Interrupt disabled.

Definition at line 5636 of file nrf51_bitfields.h.

◆ RTC_INTENSET_COMPARE2_Enabled

#define RTC_INTENSET_COMPARE2_Enabled (1UL)

Interrupt enabled.

Definition at line 5637 of file nrf51_bitfields.h.

◆ RTC_INTENSET_COMPARE2_Msk

#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos)

Bit mask of COMPARE2 field.

Definition at line 5635 of file nrf51_bitfields.h.

◆ RTC_INTENSET_COMPARE2_Pos

#define RTC_INTENSET_COMPARE2_Pos (18UL)

Position of COMPARE2 field.

Definition at line 5634 of file nrf51_bitfields.h.

◆ RTC_INTENSET_COMPARE2_Set

#define RTC_INTENSET_COMPARE2_Set (1UL)

Enable interrupt on write.

Definition at line 5638 of file nrf51_bitfields.h.

◆ RTC_INTENSET_COMPARE3_Disabled

#define RTC_INTENSET_COMPARE3_Disabled (0UL)

Interrupt disabled.

Definition at line 5629 of file nrf51_bitfields.h.

◆ RTC_INTENSET_COMPARE3_Enabled

#define RTC_INTENSET_COMPARE3_Enabled (1UL)

Interrupt enabled.

Definition at line 5630 of file nrf51_bitfields.h.

◆ RTC_INTENSET_COMPARE3_Msk

#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos)

Bit mask of COMPARE3 field.

Definition at line 5628 of file nrf51_bitfields.h.

◆ RTC_INTENSET_COMPARE3_Pos

#define RTC_INTENSET_COMPARE3_Pos (19UL)

Position of COMPARE3 field.

Definition at line 5627 of file nrf51_bitfields.h.

◆ RTC_INTENSET_COMPARE3_Set

#define RTC_INTENSET_COMPARE3_Set (1UL)

Enable interrupt on write.

Definition at line 5631 of file nrf51_bitfields.h.

◆ RTC_INTENSET_OVRFLW_Disabled

#define RTC_INTENSET_OVRFLW_Disabled (0UL)

Interrupt disabled.

Definition at line 5657 of file nrf51_bitfields.h.

◆ RTC_INTENSET_OVRFLW_Enabled

#define RTC_INTENSET_OVRFLW_Enabled (1UL)

Interrupt enabled.

Definition at line 5658 of file nrf51_bitfields.h.

◆ RTC_INTENSET_OVRFLW_Msk

#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos)

Bit mask of OVRFLW field.

Definition at line 5656 of file nrf51_bitfields.h.

◆ RTC_INTENSET_OVRFLW_Pos

#define RTC_INTENSET_OVRFLW_Pos (1UL)

Position of OVRFLW field.

Definition at line 5655 of file nrf51_bitfields.h.

◆ RTC_INTENSET_OVRFLW_Set

#define RTC_INTENSET_OVRFLW_Set (1UL)

Enable interrupt on write.

Definition at line 5659 of file nrf51_bitfields.h.

◆ RTC_INTENSET_TICK_Disabled

#define RTC_INTENSET_TICK_Disabled (0UL)

Interrupt disabled.

Definition at line 5664 of file nrf51_bitfields.h.

◆ RTC_INTENSET_TICK_Enabled

#define RTC_INTENSET_TICK_Enabled (1UL)

Interrupt enabled.

Definition at line 5665 of file nrf51_bitfields.h.

◆ RTC_INTENSET_TICK_Msk

#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos)

Bit mask of TICK field.

Definition at line 5663 of file nrf51_bitfields.h.

◆ RTC_INTENSET_TICK_Pos

#define RTC_INTENSET_TICK_Pos (0UL)

Position of TICK field.

Definition at line 5662 of file nrf51_bitfields.h.

◆ RTC_INTENSET_TICK_Set

#define RTC_INTENSET_TICK_Set (1UL)

Enable interrupt on write.

Definition at line 5666 of file nrf51_bitfields.h.

◆ RTC_POWER_POWER_Disabled

#define RTC_POWER_POWER_Disabled (0UL)

Module power disabled.

Definition at line 5869 of file nrf51_bitfields.h.

◆ RTC_POWER_POWER_Enabled

#define RTC_POWER_POWER_Enabled (1UL)

Module power enabled.

Definition at line 5870 of file nrf51_bitfields.h.

◆ RTC_POWER_POWER_Msk

#define RTC_POWER_POWER_Msk (0x1UL << RTC_POWER_POWER_Pos)

Bit mask of POWER field.

Definition at line 5868 of file nrf51_bitfields.h.

◆ RTC_POWER_POWER_Pos

#define RTC_POWER_POWER_Pos (0UL)

Position of POWER field.

Definition at line 5867 of file nrf51_bitfields.h.

◆ RTC_PRESCALER_PRESCALER_Msk

#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos)

Bit mask of PRESCALER field.

Definition at line 5854 of file nrf51_bitfields.h.

◆ RTC_PRESCALER_PRESCALER_Pos

#define RTC_PRESCALER_PRESCALER_Pos (0UL)

Position of PRESCALER field.

Definition at line 5853 of file nrf51_bitfields.h.

◆ SPI_CONFIG_CPHA_Leading

#define SPI_CONFIG_CPHA_Leading (0UL)

Sample on leading edge of the clock. Shift serial data on trailing edge.

Definition at line 5945 of file nrf51_bitfields.h.

◆ SPI_CONFIG_CPHA_Msk

#define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos)

Bit mask of CPHA field.

Definition at line 5944 of file nrf51_bitfields.h.

◆ SPI_CONFIG_CPHA_Pos

#define SPI_CONFIG_CPHA_Pos (1UL)

Position of CPHA field.

Definition at line 5943 of file nrf51_bitfields.h.

◆ SPI_CONFIG_CPHA_Trailing

#define SPI_CONFIG_CPHA_Trailing (1UL)

Sample on trailing edge of the clock. Shift serial data on leading edge.

Definition at line 5946 of file nrf51_bitfields.h.

◆ SPI_CONFIG_CPOL_ActiveHigh

#define SPI_CONFIG_CPOL_ActiveHigh (0UL)

Active high.

Definition at line 5939 of file nrf51_bitfields.h.

◆ SPI_CONFIG_CPOL_ActiveLow

#define SPI_CONFIG_CPOL_ActiveLow (1UL)

Active low.

Definition at line 5940 of file nrf51_bitfields.h.

◆ SPI_CONFIG_CPOL_Msk

#define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos)

Bit mask of CPOL field.

Definition at line 5938 of file nrf51_bitfields.h.

◆ SPI_CONFIG_CPOL_Pos

#define SPI_CONFIG_CPOL_Pos (2UL)

Position of CPOL field.

Definition at line 5937 of file nrf51_bitfields.h.

◆ SPI_CONFIG_ORDER_LsbFirst

#define SPI_CONFIG_ORDER_LsbFirst (1UL)

Least significant bit transmitted out first.

Definition at line 5952 of file nrf51_bitfields.h.

◆ SPI_CONFIG_ORDER_MsbFirst

#define SPI_CONFIG_ORDER_MsbFirst (0UL)

Most significant bit transmitted out first.

Definition at line 5951 of file nrf51_bitfields.h.

◆ SPI_CONFIG_ORDER_Msk

#define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos)

Bit mask of ORDER field.

Definition at line 5950 of file nrf51_bitfields.h.

◆ SPI_CONFIG_ORDER_Pos

#define SPI_CONFIG_ORDER_Pos (0UL)

Position of ORDER field.

Definition at line 5949 of file nrf51_bitfields.h.

◆ SPI_ENABLE_ENABLE_Disabled

#define SPI_ENABLE_ENABLE_Disabled (0x00UL)

Disabled SPI.

Definition at line 5902 of file nrf51_bitfields.h.

◆ SPI_ENABLE_ENABLE_Enabled

#define SPI_ENABLE_ENABLE_Enabled (0x01UL)

Enable SPI.

Definition at line 5903 of file nrf51_bitfields.h.

◆ SPI_ENABLE_ENABLE_Msk

#define SPI_ENABLE_ENABLE_Msk (0x7UL << SPI_ENABLE_ENABLE_Pos)

Bit mask of ENABLE field.

Definition at line 5901 of file nrf51_bitfields.h.

◆ SPI_ENABLE_ENABLE_Pos

#define SPI_ENABLE_ENABLE_Pos (0UL)

Position of ENABLE field.

Definition at line 5900 of file nrf51_bitfields.h.

◆ SPI_FREQUENCY_FREQUENCY_K125

#define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL)

125kbps.

Definition at line 5925 of file nrf51_bitfields.h.

◆ SPI_FREQUENCY_FREQUENCY_K250

#define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL)

250kbps.

Definition at line 5926 of file nrf51_bitfields.h.

◆ SPI_FREQUENCY_FREQUENCY_K500

#define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL)

500kbps.

Definition at line 5927 of file nrf51_bitfields.h.

◆ SPI_FREQUENCY_FREQUENCY_M1

#define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL)

1Mbps.

Definition at line 5928 of file nrf51_bitfields.h.

◆ SPI_FREQUENCY_FREQUENCY_M2

#define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL)

2Mbps.

Definition at line 5929 of file nrf51_bitfields.h.

◆ SPI_FREQUENCY_FREQUENCY_M4

#define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL)

4Mbps.

Definition at line 5930 of file nrf51_bitfields.h.

◆ SPI_FREQUENCY_FREQUENCY_M8

#define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL)

8Mbps.

Definition at line 5931 of file nrf51_bitfields.h.

◆ SPI_FREQUENCY_FREQUENCY_Msk

#define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos)

Bit mask of FREQUENCY field.

Definition at line 5924 of file nrf51_bitfields.h.

◆ SPI_FREQUENCY_FREQUENCY_Pos

#define SPI_FREQUENCY_FREQUENCY_Pos (0UL)

Position of FREQUENCY field.

Definition at line 5923 of file nrf51_bitfields.h.

◆ SPI_INTENCLR_READY_Clear

#define SPI_INTENCLR_READY_Clear (1UL)

Disable interrupt on write.

Definition at line 5894 of file nrf51_bitfields.h.

◆ SPI_INTENCLR_READY_Disabled

#define SPI_INTENCLR_READY_Disabled (0UL)

Interrupt disabled.

Definition at line 5892 of file nrf51_bitfields.h.

◆ SPI_INTENCLR_READY_Enabled

#define SPI_INTENCLR_READY_Enabled (1UL)

Interrupt enabled.

Definition at line 5893 of file nrf51_bitfields.h.

◆ SPI_INTENCLR_READY_Msk

#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos)

Bit mask of READY field.

Definition at line 5891 of file nrf51_bitfields.h.

◆ SPI_INTENCLR_READY_Pos

#define SPI_INTENCLR_READY_Pos (2UL)

Position of READY field.

Definition at line 5890 of file nrf51_bitfields.h.

◆ SPI_INTENSET_READY_Disabled

#define SPI_INTENSET_READY_Disabled (0UL)

Interrupt disabled.

Definition at line 5882 of file nrf51_bitfields.h.

◆ SPI_INTENSET_READY_Enabled

#define SPI_INTENSET_READY_Enabled (1UL)

Interrupt enabled.

Definition at line 5883 of file nrf51_bitfields.h.

◆ SPI_INTENSET_READY_Msk

#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos)

Bit mask of READY field.

Definition at line 5881 of file nrf51_bitfields.h.

◆ SPI_INTENSET_READY_Pos

#define SPI_INTENSET_READY_Pos (2UL)

Position of READY field.

Definition at line 5880 of file nrf51_bitfields.h.

◆ SPI_INTENSET_READY_Set

#define SPI_INTENSET_READY_Set (1UL)

Enable interrupt on write.

Definition at line 5884 of file nrf51_bitfields.h.

◆ SPI_POWER_POWER_Disabled

#define SPI_POWER_POWER_Disabled (0UL)

Module power disabled.

Definition at line 5960 of file nrf51_bitfields.h.

◆ SPI_POWER_POWER_Enabled

#define SPI_POWER_POWER_Enabled (1UL)

Module power enabled.

Definition at line 5961 of file nrf51_bitfields.h.

◆ SPI_POWER_POWER_Msk

#define SPI_POWER_POWER_Msk (0x1UL << SPI_POWER_POWER_Pos)

Bit mask of POWER field.

Definition at line 5959 of file nrf51_bitfields.h.

◆ SPI_POWER_POWER_Pos

#define SPI_POWER_POWER_Pos (0UL)

Position of POWER field.

Definition at line 5958 of file nrf51_bitfields.h.

◆ SPI_RXD_RXD_Msk

#define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos)

Bit mask of RXD field.

Definition at line 5910 of file nrf51_bitfields.h.

◆ SPI_RXD_RXD_Pos

#define SPI_RXD_RXD_Pos (0UL)

Position of RXD field.

Definition at line 5909 of file nrf51_bitfields.h.

◆ SPI_TXD_TXD_Msk

#define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos)

Bit mask of TXD field.

Definition at line 5917 of file nrf51_bitfields.h.

◆ SPI_TXD_TXD_Pos

#define SPI_TXD_TXD_Pos (0UL)

Position of TXD field.

Definition at line 5916 of file nrf51_bitfields.h.

◆ SPIM_CONFIG_CPHA_Leading

#define SPIM_CONFIG_CPHA_Leading (0UL)

Sample on leading edge of the clock. Shift serial data on trailing edge.

Definition at line 6129 of file nrf51_bitfields.h.

◆ SPIM_CONFIG_CPHA_Msk

#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos)

Bit mask of CPHA field.

Definition at line 6128 of file nrf51_bitfields.h.

◆ SPIM_CONFIG_CPHA_Pos

#define SPIM_CONFIG_CPHA_Pos (1UL)

Position of CPHA field.

Definition at line 6127 of file nrf51_bitfields.h.

◆ SPIM_CONFIG_CPHA_Trailing

#define SPIM_CONFIG_CPHA_Trailing (1UL)

Sample on trailing edge of the clock. Shift serial data on leading edge.

Definition at line 6130 of file nrf51_bitfields.h.

◆ SPIM_CONFIG_CPOL_ActiveHigh

#define SPIM_CONFIG_CPOL_ActiveHigh (0UL)

Active high.

Definition at line 6123 of file nrf51_bitfields.h.

◆ SPIM_CONFIG_CPOL_ActiveLow

#define SPIM_CONFIG_CPOL_ActiveLow (1UL)

Active low.

Definition at line 6124 of file nrf51_bitfields.h.

◆ SPIM_CONFIG_CPOL_Msk

#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos)

Bit mask of CPOL field.

Definition at line 6122 of file nrf51_bitfields.h.

◆ SPIM_CONFIG_CPOL_Pos

#define SPIM_CONFIG_CPOL_Pos (2UL)

Position of CPOL field.

Definition at line 6121 of file nrf51_bitfields.h.

◆ SPIM_CONFIG_ORDER_LsbFirst

#define SPIM_CONFIG_ORDER_LsbFirst (1UL)

Least significant bit transmitted out first.

Definition at line 6136 of file nrf51_bitfields.h.

◆ SPIM_CONFIG_ORDER_MsbFirst

#define SPIM_CONFIG_ORDER_MsbFirst (0UL)

Most significant bit transmitted out first.

Definition at line 6135 of file nrf51_bitfields.h.

◆ SPIM_CONFIG_ORDER_Msk

#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos)

Bit mask of ORDER field.

Definition at line 6134 of file nrf51_bitfields.h.

◆ SPIM_CONFIG_ORDER_Pos

#define SPIM_CONFIG_ORDER_Pos (0UL)

Position of ORDER field.

Definition at line 6133 of file nrf51_bitfields.h.

◆ SPIM_ENABLE_ENABLE_Disabled

#define SPIM_ENABLE_ENABLE_Disabled (0x00UL)

Disabled SPIM.

Definition at line 6058 of file nrf51_bitfields.h.

◆ SPIM_ENABLE_ENABLE_Enabled

#define SPIM_ENABLE_ENABLE_Enabled (0x07UL)

Enable SPIM.

Definition at line 6059 of file nrf51_bitfields.h.

◆ SPIM_ENABLE_ENABLE_Msk

#define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos)

Bit mask of ENABLE field.

Definition at line 6057 of file nrf51_bitfields.h.

◆ SPIM_ENABLE_ENABLE_Pos

#define SPIM_ENABLE_ENABLE_Pos (0UL)

Position of ENABLE field.

Definition at line 6056 of file nrf51_bitfields.h.

◆ SPIM_FREQUENCY_FREQUENCY_K125

#define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL)

125 kbps.

Definition at line 6067 of file nrf51_bitfields.h.

◆ SPIM_FREQUENCY_FREQUENCY_K250

#define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL)

250 kbps.

Definition at line 6068 of file nrf51_bitfields.h.

◆ SPIM_FREQUENCY_FREQUENCY_K500

#define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL)

500 kbps.

Definition at line 6069 of file nrf51_bitfields.h.

◆ SPIM_FREQUENCY_FREQUENCY_M1

#define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL)

1 Mbps.

Definition at line 6070 of file nrf51_bitfields.h.

◆ SPIM_FREQUENCY_FREQUENCY_M2

#define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL)

2 Mbps.

Definition at line 6071 of file nrf51_bitfields.h.

◆ SPIM_FREQUENCY_FREQUENCY_M4

#define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL)

4 Mbps.

Definition at line 6072 of file nrf51_bitfields.h.

◆ SPIM_FREQUENCY_FREQUENCY_M8

#define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL)

8 Mbps.

Definition at line 6073 of file nrf51_bitfields.h.

◆ SPIM_FREQUENCY_FREQUENCY_Msk

#define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos)

Bit mask of FREQUENCY field.

Definition at line 6066 of file nrf51_bitfields.h.

◆ SPIM_FREQUENCY_FREQUENCY_Pos

#define SPIM_FREQUENCY_FREQUENCY_Pos (0UL)

Position of FREQUENCY field.

Definition at line 6065 of file nrf51_bitfields.h.

◆ SPIM_INTENCLR_END_Clear

#define SPIM_INTENCLR_END_Clear (1UL)

Disable interrupt on write.

Definition at line 6036 of file nrf51_bitfields.h.

◆ SPIM_INTENCLR_END_Disabled

#define SPIM_INTENCLR_END_Disabled (0UL)

Interrupt disabled.

Definition at line 6034 of file nrf51_bitfields.h.

◆ SPIM_INTENCLR_END_Enabled

#define SPIM_INTENCLR_END_Enabled (1UL)

Interrupt enabled.

Definition at line 6035 of file nrf51_bitfields.h.

◆ SPIM_INTENCLR_END_Msk

#define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos)

Bit mask of END field.

Definition at line 6033 of file nrf51_bitfields.h.

◆ SPIM_INTENCLR_END_Pos

#define SPIM_INTENCLR_END_Pos (6UL)

Position of END field.

Definition at line 6032 of file nrf51_bitfields.h.

◆ SPIM_INTENCLR_ENDRX_Clear

#define SPIM_INTENCLR_ENDRX_Clear (1UL)

Disable interrupt on write.

Definition at line 6043 of file nrf51_bitfields.h.

◆ SPIM_INTENCLR_ENDRX_Disabled

#define SPIM_INTENCLR_ENDRX_Disabled (0UL)

Interrupt disabled.

Definition at line 6041 of file nrf51_bitfields.h.

◆ SPIM_INTENCLR_ENDRX_Enabled

#define SPIM_INTENCLR_ENDRX_Enabled (1UL)

Interrupt enabled.

Definition at line 6042 of file nrf51_bitfields.h.

◆ SPIM_INTENCLR_ENDRX_Msk

#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos)

Bit mask of ENDRX field.

Definition at line 6040 of file nrf51_bitfields.h.

◆ SPIM_INTENCLR_ENDRX_Pos

#define SPIM_INTENCLR_ENDRX_Pos (4UL)

Position of ENDRX field.

Definition at line 6039 of file nrf51_bitfields.h.

◆ SPIM_INTENCLR_ENDTX_Clear

#define SPIM_INTENCLR_ENDTX_Clear (1UL)

Disable interrupt on write.

Definition at line 6029 of file nrf51_bitfields.h.

◆ SPIM_INTENCLR_ENDTX_Disabled

#define SPIM_INTENCLR_ENDTX_Disabled (0UL)

Interrupt disabled.

Definition at line 6027 of file nrf51_bitfields.h.

◆ SPIM_INTENCLR_ENDTX_Enabled

#define SPIM_INTENCLR_ENDTX_Enabled (1UL)

Interrupt enabled.

Definition at line 6028 of file nrf51_bitfields.h.

◆ SPIM_INTENCLR_ENDTX_Msk

#define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos)

Bit mask of ENDTX field.

Definition at line 6026 of file nrf51_bitfields.h.

◆ SPIM_INTENCLR_ENDTX_Pos

#define SPIM_INTENCLR_ENDTX_Pos (8UL)

Position of ENDTX field.

Definition at line 6025 of file nrf51_bitfields.h.

◆ SPIM_INTENCLR_STARTED_Clear

#define SPIM_INTENCLR_STARTED_Clear (1UL)

Disable interrupt on write.

Definition at line 6022 of file nrf51_bitfields.h.

◆ SPIM_INTENCLR_STARTED_Disabled

#define SPIM_INTENCLR_STARTED_Disabled (0UL)

Interrupt disabled.

Definition at line 6020 of file nrf51_bitfields.h.

◆ SPIM_INTENCLR_STARTED_Enabled

#define SPIM_INTENCLR_STARTED_Enabled (1UL)

Interrupt enabled.

Definition at line 6021 of file nrf51_bitfields.h.

◆ SPIM_INTENCLR_STARTED_Msk

#define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos)

Bit mask of STARTED field.

Definition at line 6019 of file nrf51_bitfields.h.

◆ SPIM_INTENCLR_STARTED_Pos

#define SPIM_INTENCLR_STARTED_Pos (19UL)

Position of STARTED field.

Definition at line 6018 of file nrf51_bitfields.h.

◆ SPIM_INTENCLR_STOPPED_Clear

#define SPIM_INTENCLR_STOPPED_Clear (1UL)

Disable interrupt on write.

Definition at line 6050 of file nrf51_bitfields.h.

◆ SPIM_INTENCLR_STOPPED_Disabled

#define SPIM_INTENCLR_STOPPED_Disabled (0UL)

Interrupt disabled.

Definition at line 6048 of file nrf51_bitfields.h.

◆ SPIM_INTENCLR_STOPPED_Enabled

#define SPIM_INTENCLR_STOPPED_Enabled (1UL)

Interrupt enabled.

Definition at line 6049 of file nrf51_bitfields.h.

◆ SPIM_INTENCLR_STOPPED_Msk

#define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos)

Bit mask of STOPPED field.

Definition at line 6047 of file nrf51_bitfields.h.

◆ SPIM_INTENCLR_STOPPED_Pos

#define SPIM_INTENCLR_STOPPED_Pos (1UL)

Position of STOPPED field.

Definition at line 6046 of file nrf51_bitfields.h.

◆ SPIM_INTENSET_END_Disabled

#define SPIM_INTENSET_END_Disabled (0UL)

Interrupt disabled.

Definition at line 5996 of file nrf51_bitfields.h.

◆ SPIM_INTENSET_END_Enabled

#define SPIM_INTENSET_END_Enabled (1UL)

Interrupt enabled.

Definition at line 5997 of file nrf51_bitfields.h.

◆ SPIM_INTENSET_END_Msk

#define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos)

Bit mask of END field.

Definition at line 5995 of file nrf51_bitfields.h.

◆ SPIM_INTENSET_END_Pos

#define SPIM_INTENSET_END_Pos (6UL)

Position of END field.

Definition at line 5994 of file nrf51_bitfields.h.

◆ SPIM_INTENSET_END_Set

#define SPIM_INTENSET_END_Set (1UL)

Enable interrupt on write.

Definition at line 5998 of file nrf51_bitfields.h.

◆ SPIM_INTENSET_ENDRX_Disabled

#define SPIM_INTENSET_ENDRX_Disabled (0UL)

Interrupt disabled.

Definition at line 6003 of file nrf51_bitfields.h.

◆ SPIM_INTENSET_ENDRX_Enabled

#define SPIM_INTENSET_ENDRX_Enabled (1UL)

Interrupt enabled.

Definition at line 6004 of file nrf51_bitfields.h.

◆ SPIM_INTENSET_ENDRX_Msk

#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos)

Bit mask of ENDRX field.

Definition at line 6002 of file nrf51_bitfields.h.

◆ SPIM_INTENSET_ENDRX_Pos

#define SPIM_INTENSET_ENDRX_Pos (4UL)

Position of ENDRX field.

Definition at line 6001 of file nrf51_bitfields.h.

◆ SPIM_INTENSET_ENDRX_Set

#define SPIM_INTENSET_ENDRX_Set (1UL)

Enable interrupt on write.

Definition at line 6005 of file nrf51_bitfields.h.

◆ SPIM_INTENSET_ENDTX_Disabled

#define SPIM_INTENSET_ENDTX_Disabled (0UL)

Interrupt disabled.

Definition at line 5989 of file nrf51_bitfields.h.

◆ SPIM_INTENSET_ENDTX_Enabled

#define SPIM_INTENSET_ENDTX_Enabled (1UL)

Interrupt enabled.

Definition at line 5990 of file nrf51_bitfields.h.

◆ SPIM_INTENSET_ENDTX_Msk

#define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos)

Bit mask of ENDTX field.

Definition at line 5988 of file nrf51_bitfields.h.

◆ SPIM_INTENSET_ENDTX_Pos

#define SPIM_INTENSET_ENDTX_Pos (8UL)

Position of ENDTX field.

Definition at line 5987 of file nrf51_bitfields.h.

◆ SPIM_INTENSET_ENDTX_Set

#define SPIM_INTENSET_ENDTX_Set (1UL)

Enable interrupt on write.

Definition at line 5991 of file nrf51_bitfields.h.

◆ SPIM_INTENSET_STARTED_Disabled

#define SPIM_INTENSET_STARTED_Disabled (0UL)

Interrupt disabled.

Definition at line 5982 of file nrf51_bitfields.h.

◆ SPIM_INTENSET_STARTED_Enabled

#define SPIM_INTENSET_STARTED_Enabled (1UL)

Interrupt enabled.

Definition at line 5983 of file nrf51_bitfields.h.

◆ SPIM_INTENSET_STARTED_Msk

#define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos)

Bit mask of STARTED field.

Definition at line 5981 of file nrf51_bitfields.h.

◆ SPIM_INTENSET_STARTED_Pos

#define SPIM_INTENSET_STARTED_Pos (19UL)

Position of STARTED field.

Definition at line 5980 of file nrf51_bitfields.h.

◆ SPIM_INTENSET_STARTED_Set

#define SPIM_INTENSET_STARTED_Set (1UL)

Enable interrupt on write.

Definition at line 5984 of file nrf51_bitfields.h.

◆ SPIM_INTENSET_STOPPED_Disabled

#define SPIM_INTENSET_STOPPED_Disabled (0UL)

Interrupt disabled.

Definition at line 6010 of file nrf51_bitfields.h.

◆ SPIM_INTENSET_STOPPED_Enabled

#define SPIM_INTENSET_STOPPED_Enabled (1UL)

Interrupt enabled.

Definition at line 6011 of file nrf51_bitfields.h.

◆ SPIM_INTENSET_STOPPED_Msk

#define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos)

Bit mask of STOPPED field.

Definition at line 6009 of file nrf51_bitfields.h.

◆ SPIM_INTENSET_STOPPED_Pos

#define SPIM_INTENSET_STOPPED_Pos (1UL)

Position of STOPPED field.

Definition at line 6008 of file nrf51_bitfields.h.

◆ SPIM_INTENSET_STOPPED_Set

#define SPIM_INTENSET_STOPPED_Set (1UL)

Enable interrupt on write.

Definition at line 6012 of file nrf51_bitfields.h.

◆ SPIM_ORC_ORC_Msk

#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos)

Bit mask of ORC field.

Definition at line 6143 of file nrf51_bitfields.h.

◆ SPIM_ORC_ORC_Pos

#define SPIM_ORC_ORC_Pos (0UL)

Position of ORC field.

Definition at line 6142 of file nrf51_bitfields.h.

◆ SPIM_POWER_POWER_Disabled

#define SPIM_POWER_POWER_Disabled (0UL)

Module power disabled.

Definition at line 6151 of file nrf51_bitfields.h.

◆ SPIM_POWER_POWER_Enabled

#define SPIM_POWER_POWER_Enabled (1UL)

Module power enabled.

Definition at line 6152 of file nrf51_bitfields.h.

◆ SPIM_POWER_POWER_Msk

#define SPIM_POWER_POWER_Msk (0x1UL << SPIM_POWER_POWER_Pos)

Bit mask of POWER field.

Definition at line 6150 of file nrf51_bitfields.h.

◆ SPIM_POWER_POWER_Pos

#define SPIM_POWER_POWER_Pos (0UL)

Position of POWER field.

Definition at line 6149 of file nrf51_bitfields.h.

◆ SPIM_RXD_AMOUNT_AMOUNT_Msk

#define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos)

Bit mask of AMOUNT field.

Definition at line 6094 of file nrf51_bitfields.h.

◆ SPIM_RXD_AMOUNT_AMOUNT_Pos

#define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL)

Position of AMOUNT field.

Definition at line 6093 of file nrf51_bitfields.h.

◆ SPIM_RXD_MAXCNT_MAXCNT_Msk

#define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos)

Bit mask of MAXCNT field.

Definition at line 6087 of file nrf51_bitfields.h.

◆ SPIM_RXD_MAXCNT_MAXCNT_Pos

#define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL)

Position of MAXCNT field.

Definition at line 6086 of file nrf51_bitfields.h.

◆ SPIM_RXD_PTR_PTR_Msk

#define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos)

Bit mask of PTR field.

Definition at line 6080 of file nrf51_bitfields.h.

◆ SPIM_RXD_PTR_PTR_Pos

#define SPIM_RXD_PTR_PTR_Pos (0UL)

Position of PTR field.

Definition at line 6079 of file nrf51_bitfields.h.

◆ SPIM_SHORTS_END_START_Disabled

#define SPIM_SHORTS_END_START_Disabled (0UL)

Shortcut disabled.

Definition at line 5973 of file nrf51_bitfields.h.

◆ SPIM_SHORTS_END_START_Enabled

#define SPIM_SHORTS_END_START_Enabled (1UL)

Shortcut enabled.

Definition at line 5974 of file nrf51_bitfields.h.

◆ SPIM_SHORTS_END_START_Msk

#define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos)

Bit mask of END_START field.

Definition at line 5972 of file nrf51_bitfields.h.

◆ SPIM_SHORTS_END_START_Pos

#define SPIM_SHORTS_END_START_Pos (17UL)

Position of END_START field.

Definition at line 5971 of file nrf51_bitfields.h.

◆ SPIM_TXD_AMOUNT_AMOUNT_Msk

#define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos)

Bit mask of AMOUNT field.

Definition at line 6115 of file nrf51_bitfields.h.

◆ SPIM_TXD_AMOUNT_AMOUNT_Pos

#define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL)

Position of AMOUNT field.

Definition at line 6114 of file nrf51_bitfields.h.

◆ SPIM_TXD_MAXCNT_MAXCNT_Msk

#define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos)

Bit mask of MAXCNT field.

Definition at line 6108 of file nrf51_bitfields.h.

◆ SPIM_TXD_MAXCNT_MAXCNT_Pos

#define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL)

Position of MAXCNT field.

Definition at line 6107 of file nrf51_bitfields.h.

◆ SPIM_TXD_PTR_PTR_Msk

#define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos)

Bit mask of PTR field.

Definition at line 6101 of file nrf51_bitfields.h.

◆ SPIM_TXD_PTR_PTR_Pos

#define SPIM_TXD_PTR_PTR_Pos (0UL)

Position of PTR field.

Definition at line 6100 of file nrf51_bitfields.h.

◆ SPIS_AMOUNTRX_AMOUNTRX_Msk

#define SPIS_AMOUNTRX_AMOUNTRX_Msk (0xFFUL << SPIS_AMOUNTRX_AMOUNTRX_Pos)

Bit mask of AMOUNTRX field.

Definition at line 6250 of file nrf51_bitfields.h.

◆ SPIS_AMOUNTRX_AMOUNTRX_Pos

#define SPIS_AMOUNTRX_AMOUNTRX_Pos (0UL)

Position of AMOUNTRX field.

Definition at line 6249 of file nrf51_bitfields.h.

◆ SPIS_AMOUNTTX_AMOUNTTX_Msk

#define SPIS_AMOUNTTX_AMOUNTTX_Msk (0xFFUL << SPIS_AMOUNTTX_AMOUNTTX_Pos)

Bit mask of AMOUNTTX field.

Definition at line 6264 of file nrf51_bitfields.h.

◆ SPIS_AMOUNTTX_AMOUNTTX_Pos

#define SPIS_AMOUNTTX_AMOUNTTX_Pos (0UL)

Position of AMOUNTTX field.

Definition at line 6263 of file nrf51_bitfields.h.

◆ SPIS_CONFIG_CPHA_Leading

#define SPIS_CONFIG_CPHA_Leading (0UL)

Sample on leading edge of the clock. Shift serial data on trailing edge.

Definition at line 6278 of file nrf51_bitfields.h.

◆ SPIS_CONFIG_CPHA_Msk

#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos)

Bit mask of CPHA field.

Definition at line 6277 of file nrf51_bitfields.h.

◆ SPIS_CONFIG_CPHA_Pos

#define SPIS_CONFIG_CPHA_Pos (1UL)

Position of CPHA field.

Definition at line 6276 of file nrf51_bitfields.h.

◆ SPIS_CONFIG_CPHA_Trailing

#define SPIS_CONFIG_CPHA_Trailing (1UL)

Sample on trailing edge of the clock. Shift serial data on leading edge.

Definition at line 6279 of file nrf51_bitfields.h.

◆ SPIS_CONFIG_CPOL_ActiveHigh

#define SPIS_CONFIG_CPOL_ActiveHigh (0UL)

Active high.

Definition at line 6272 of file nrf51_bitfields.h.

◆ SPIS_CONFIG_CPOL_ActiveLow

#define SPIS_CONFIG_CPOL_ActiveLow (1UL)

Active low.

Definition at line 6273 of file nrf51_bitfields.h.

◆ SPIS_CONFIG_CPOL_Msk

#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos)

Bit mask of CPOL field.

Definition at line 6271 of file nrf51_bitfields.h.

◆ SPIS_CONFIG_CPOL_Pos

#define SPIS_CONFIG_CPOL_Pos (2UL)

Position of CPOL field.

Definition at line 6270 of file nrf51_bitfields.h.

◆ SPIS_CONFIG_ORDER_LsbFirst

#define SPIS_CONFIG_ORDER_LsbFirst (1UL)

Least significant bit transmitted out first.

Definition at line 6285 of file nrf51_bitfields.h.

◆ SPIS_CONFIG_ORDER_MsbFirst

#define SPIS_CONFIG_ORDER_MsbFirst (0UL)

Most significant bit transmitted out first.

Definition at line 6284 of file nrf51_bitfields.h.

◆ SPIS_CONFIG_ORDER_Msk

#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos)

Bit mask of ORDER field.

Definition at line 6283 of file nrf51_bitfields.h.

◆ SPIS_CONFIG_ORDER_Pos

#define SPIS_CONFIG_ORDER_Pos (0UL)

Position of ORDER field.

Definition at line 6282 of file nrf51_bitfields.h.

◆ SPIS_DEF_DEF_Msk

#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos)

Bit mask of DEF field.

Definition at line 6292 of file nrf51_bitfields.h.

◆ SPIS_DEF_DEF_Pos

#define SPIS_DEF_DEF_Pos (0UL)

Position of DEF field.

Definition at line 6291 of file nrf51_bitfields.h.

◆ SPIS_ENABLE_ENABLE_Disabled

#define SPIS_ENABLE_ENABLE_Disabled (0x00UL)

Disabled SPIS.

Definition at line 6235 of file nrf51_bitfields.h.

◆ SPIS_ENABLE_ENABLE_Enabled

#define SPIS_ENABLE_ENABLE_Enabled (0x02UL)

Enable SPIS.

Definition at line 6236 of file nrf51_bitfields.h.

◆ SPIS_ENABLE_ENABLE_Msk

#define SPIS_ENABLE_ENABLE_Msk (0x7UL << SPIS_ENABLE_ENABLE_Pos)

Bit mask of ENABLE field.

Definition at line 6234 of file nrf51_bitfields.h.

◆ SPIS_ENABLE_ENABLE_Pos

#define SPIS_ENABLE_ENABLE_Pos (0UL)

Position of ENABLE field.

Definition at line 6233 of file nrf51_bitfields.h.

◆ SPIS_INTENCLR_ACQUIRED_Clear

#define SPIS_INTENCLR_ACQUIRED_Clear (1UL)

Disable interrupt on write.

Definition at line 6192 of file nrf51_bitfields.h.

◆ SPIS_INTENCLR_ACQUIRED_Disabled

#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL)

Interrupt disabled.

Definition at line 6190 of file nrf51_bitfields.h.

◆ SPIS_INTENCLR_ACQUIRED_Enabled

#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL)

Interrupt enabled.

Definition at line 6191 of file nrf51_bitfields.h.

◆ SPIS_INTENCLR_ACQUIRED_Msk

#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos)

Bit mask of ACQUIRED field.

Definition at line 6189 of file nrf51_bitfields.h.

◆ SPIS_INTENCLR_ACQUIRED_Pos

#define SPIS_INTENCLR_ACQUIRED_Pos (10UL)

Position of ACQUIRED field.

Definition at line 6188 of file nrf51_bitfields.h.

◆ SPIS_INTENCLR_END_Clear

#define SPIS_INTENCLR_END_Clear (1UL)

Disable interrupt on write.

Definition at line 6199 of file nrf51_bitfields.h.

◆ SPIS_INTENCLR_END_Disabled

#define SPIS_INTENCLR_END_Disabled (0UL)

Interrupt disabled.

Definition at line 6197 of file nrf51_bitfields.h.

◆ SPIS_INTENCLR_END_Enabled

#define SPIS_INTENCLR_END_Enabled (1UL)

Interrupt enabled.

Definition at line 6198 of file nrf51_bitfields.h.

◆ SPIS_INTENCLR_END_Msk

#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos)

Bit mask of END field.

Definition at line 6196 of file nrf51_bitfields.h.

◆ SPIS_INTENCLR_END_Pos

#define SPIS_INTENCLR_END_Pos (1UL)

Position of END field.

Definition at line 6195 of file nrf51_bitfields.h.

◆ SPIS_INTENSET_ACQUIRED_Disabled

#define SPIS_INTENSET_ACQUIRED_Disabled (0UL)

Interrupt disabled.

Definition at line 6173 of file nrf51_bitfields.h.

◆ SPIS_INTENSET_ACQUIRED_Enabled

#define SPIS_INTENSET_ACQUIRED_Enabled (1UL)

Interrupt enabled.

Definition at line 6174 of file nrf51_bitfields.h.

◆ SPIS_INTENSET_ACQUIRED_Msk

#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos)

Bit mask of ACQUIRED field.

Definition at line 6172 of file nrf51_bitfields.h.

◆ SPIS_INTENSET_ACQUIRED_Pos

#define SPIS_INTENSET_ACQUIRED_Pos (10UL)

Position of ACQUIRED field.

Definition at line 6171 of file nrf51_bitfields.h.

◆ SPIS_INTENSET_ACQUIRED_Set

#define SPIS_INTENSET_ACQUIRED_Set (1UL)

Enable interrupt on write.

Definition at line 6175 of file nrf51_bitfields.h.

◆ SPIS_INTENSET_END_Disabled

#define SPIS_INTENSET_END_Disabled (0UL)

Interrupt disabled.

Definition at line 6180 of file nrf51_bitfields.h.

◆ SPIS_INTENSET_END_Enabled

#define SPIS_INTENSET_END_Enabled (1UL)

Interrupt enabled.

Definition at line 6181 of file nrf51_bitfields.h.

◆ SPIS_INTENSET_END_Msk

#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos)

Bit mask of END field.

Definition at line 6179 of file nrf51_bitfields.h.

◆ SPIS_INTENSET_END_Pos

#define SPIS_INTENSET_END_Pos (1UL)

Position of END field.

Definition at line 6178 of file nrf51_bitfields.h.

◆ SPIS_INTENSET_END_Set

#define SPIS_INTENSET_END_Set (1UL)

Enable interrupt on write.

Definition at line 6182 of file nrf51_bitfields.h.

◆ SPIS_MAXRX_MAXRX_Msk

#define SPIS_MAXRX_MAXRX_Msk (0xFFUL << SPIS_MAXRX_MAXRX_Pos)

Bit mask of MAXRX field.

Definition at line 6243 of file nrf51_bitfields.h.

◆ SPIS_MAXRX_MAXRX_Pos

#define SPIS_MAXRX_MAXRX_Pos (0UL)

Position of MAXRX field.

Definition at line 6242 of file nrf51_bitfields.h.

◆ SPIS_MAXTX_MAXTX_Msk

#define SPIS_MAXTX_MAXTX_Msk (0xFFUL << SPIS_MAXTX_MAXTX_Pos)

Bit mask of MAXTX field.

Definition at line 6257 of file nrf51_bitfields.h.

◆ SPIS_MAXTX_MAXTX_Pos

#define SPIS_MAXTX_MAXTX_Pos (0UL)

Position of MAXTX field.

Definition at line 6256 of file nrf51_bitfields.h.

◆ SPIS_ORC_ORC_Msk

#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos)

Bit mask of ORC field.

Definition at line 6299 of file nrf51_bitfields.h.

◆ SPIS_ORC_ORC_Pos

#define SPIS_ORC_ORC_Pos (0UL)

Position of ORC field.

Definition at line 6298 of file nrf51_bitfields.h.

◆ SPIS_POWER_POWER_Disabled

#define SPIS_POWER_POWER_Disabled (0UL)

Module power disabled.

Definition at line 6307 of file nrf51_bitfields.h.

◆ SPIS_POWER_POWER_Enabled

#define SPIS_POWER_POWER_Enabled (1UL)

Module power enabled.

Definition at line 6308 of file nrf51_bitfields.h.

◆ SPIS_POWER_POWER_Msk

#define SPIS_POWER_POWER_Msk (0x1UL << SPIS_POWER_POWER_Pos)

Bit mask of POWER field.

Definition at line 6306 of file nrf51_bitfields.h.

◆ SPIS_POWER_POWER_Pos

#define SPIS_POWER_POWER_Pos (0UL)

Position of POWER field.

Definition at line 6305 of file nrf51_bitfields.h.

◆ SPIS_SEMSTAT_SEMSTAT_CPU

#define SPIS_SEMSTAT_SEMSTAT_CPU (0x01UL)

Semaphore is assigned to the CPU.

Definition at line 6208 of file nrf51_bitfields.h.

◆ SPIS_SEMSTAT_SEMSTAT_CPUPending

#define SPIS_SEMSTAT_SEMSTAT_CPUPending (0x03UL)

Semaphore is assigned to the SPIS, but a handover to the CPU is pending.

Definition at line 6210 of file nrf51_bitfields.h.

◆ SPIS_SEMSTAT_SEMSTAT_Free

#define SPIS_SEMSTAT_SEMSTAT_Free (0x00UL)

Semaphore is free.

Definition at line 6207 of file nrf51_bitfields.h.

◆ SPIS_SEMSTAT_SEMSTAT_Msk

#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos)

Bit mask of SEMSTAT field.

Definition at line 6206 of file nrf51_bitfields.h.

◆ SPIS_SEMSTAT_SEMSTAT_Pos

#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL)

Position of SEMSTAT field.

Definition at line 6205 of file nrf51_bitfields.h.

◆ SPIS_SEMSTAT_SEMSTAT_SPIS

#define SPIS_SEMSTAT_SEMSTAT_SPIS (0x02UL)

Semaphore is assigned to the SPIS.

Definition at line 6209 of file nrf51_bitfields.h.

◆ SPIS_SHORTS_END_ACQUIRE_Disabled

#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL)

Shortcut disabled.

Definition at line 6164 of file nrf51_bitfields.h.

◆ SPIS_SHORTS_END_ACQUIRE_Enabled

#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL)

Shortcut enabled.

Definition at line 6165 of file nrf51_bitfields.h.

◆ SPIS_SHORTS_END_ACQUIRE_Msk

#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos)

Bit mask of END_ACQUIRE field.

Definition at line 6163 of file nrf51_bitfields.h.

◆ SPIS_SHORTS_END_ACQUIRE_Pos

#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL)

Position of END_ACQUIRE field.

Definition at line 6162 of file nrf51_bitfields.h.

◆ SPIS_STATUS_OVERFLOW_Clear

#define SPIS_STATUS_OVERFLOW_Clear (1UL)

Clear on write.

Definition at line 6220 of file nrf51_bitfields.h.

◆ SPIS_STATUS_OVERFLOW_Msk

#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos)

Bit mask of OVERFLOW field.

Definition at line 6217 of file nrf51_bitfields.h.

◆ SPIS_STATUS_OVERFLOW_NotPresent

#define SPIS_STATUS_OVERFLOW_NotPresent (0UL)

Error not present.

Definition at line 6218 of file nrf51_bitfields.h.

◆ SPIS_STATUS_OVERFLOW_Pos

#define SPIS_STATUS_OVERFLOW_Pos (1UL)

Position of OVERFLOW field.

Definition at line 6216 of file nrf51_bitfields.h.

◆ SPIS_STATUS_OVERFLOW_Present

#define SPIS_STATUS_OVERFLOW_Present (1UL)

Error present.

Definition at line 6219 of file nrf51_bitfields.h.

◆ SPIS_STATUS_OVERREAD_Clear

#define SPIS_STATUS_OVERREAD_Clear (1UL)

Clear on write.

Definition at line 6227 of file nrf51_bitfields.h.

◆ SPIS_STATUS_OVERREAD_Msk

#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos)

Bit mask of OVERREAD field.

Definition at line 6224 of file nrf51_bitfields.h.

◆ SPIS_STATUS_OVERREAD_NotPresent

#define SPIS_STATUS_OVERREAD_NotPresent (0UL)

Error not present.

Definition at line 6225 of file nrf51_bitfields.h.

◆ SPIS_STATUS_OVERREAD_Pos

#define SPIS_STATUS_OVERREAD_Pos (0UL)

Position of OVERREAD field.

Definition at line 6223 of file nrf51_bitfields.h.

◆ SPIS_STATUS_OVERREAD_Present

#define SPIS_STATUS_OVERREAD_Present (1UL)

Error present.

Definition at line 6226 of file nrf51_bitfields.h.

◆ TEMP_INTENCLR_DATARDY_Clear

#define TEMP_INTENCLR_DATARDY_Clear (1UL)

Disable interrupt on write.

Definition at line 6332 of file nrf51_bitfields.h.

◆ TEMP_INTENCLR_DATARDY_Disabled

#define TEMP_INTENCLR_DATARDY_Disabled (0UL)

Interrupt disabled.

Definition at line 6330 of file nrf51_bitfields.h.

◆ TEMP_INTENCLR_DATARDY_Enabled

#define TEMP_INTENCLR_DATARDY_Enabled (1UL)

Interrupt enabled.

Definition at line 6331 of file nrf51_bitfields.h.

◆ TEMP_INTENCLR_DATARDY_Msk

#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos)

Bit mask of DATARDY field.

Definition at line 6329 of file nrf51_bitfields.h.

◆ TEMP_INTENCLR_DATARDY_Pos

#define TEMP_INTENCLR_DATARDY_Pos (0UL)

Position of DATARDY field.

Definition at line 6328 of file nrf51_bitfields.h.

◆ TEMP_INTENSET_DATARDY_Disabled

#define TEMP_INTENSET_DATARDY_Disabled (0UL)

Interrupt disabled.

Definition at line 6320 of file nrf51_bitfields.h.

◆ TEMP_INTENSET_DATARDY_Enabled

#define TEMP_INTENSET_DATARDY_Enabled (1UL)

Interrupt enabled.

Definition at line 6321 of file nrf51_bitfields.h.

◆ TEMP_INTENSET_DATARDY_Msk

#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos)

Bit mask of DATARDY field.

Definition at line 6319 of file nrf51_bitfields.h.

◆ TEMP_INTENSET_DATARDY_Pos

#define TEMP_INTENSET_DATARDY_Pos (0UL)

Position of DATARDY field.

Definition at line 6318 of file nrf51_bitfields.h.

◆ TEMP_INTENSET_DATARDY_Set

#define TEMP_INTENSET_DATARDY_Set (1UL)

Enable interrupt on write.

Definition at line 6322 of file nrf51_bitfields.h.

◆ TEMP_POWER_POWER_Disabled

#define TEMP_POWER_POWER_Disabled (0UL)

Module power disabled.

Definition at line 6340 of file nrf51_bitfields.h.

◆ TEMP_POWER_POWER_Enabled

#define TEMP_POWER_POWER_Enabled (1UL)

Module power enabled.

Definition at line 6341 of file nrf51_bitfields.h.

◆ TEMP_POWER_POWER_Msk

#define TEMP_POWER_POWER_Msk (0x1UL << TEMP_POWER_POWER_Pos)

Bit mask of POWER field.

Definition at line 6339 of file nrf51_bitfields.h.

◆ TEMP_POWER_POWER_Pos

#define TEMP_POWER_POWER_Pos (0UL)

Position of POWER field.

Definition at line 6338 of file nrf51_bitfields.h.

◆ TIMER_BITMODE_BITMODE_08Bit

#define TIMER_BITMODE_BITMODE_08Bit (0x01UL)

8-bit timer behaviour.

Definition at line 6476 of file nrf51_bitfields.h.

◆ TIMER_BITMODE_BITMODE_16Bit

#define TIMER_BITMODE_BITMODE_16Bit (0x00UL)

16-bit timer behaviour.

Definition at line 6475 of file nrf51_bitfields.h.

◆ TIMER_BITMODE_BITMODE_24Bit

#define TIMER_BITMODE_BITMODE_24Bit (0x02UL)

24-bit timer behaviour.

Definition at line 6477 of file nrf51_bitfields.h.

◆ TIMER_BITMODE_BITMODE_32Bit

#define TIMER_BITMODE_BITMODE_32Bit (0x03UL)

32-bit timer behaviour.

Definition at line 6478 of file nrf51_bitfields.h.

◆ TIMER_BITMODE_BITMODE_Msk

#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos)

Bit mask of BITMODE field.

Definition at line 6474 of file nrf51_bitfields.h.

◆ TIMER_BITMODE_BITMODE_Pos

#define TIMER_BITMODE_BITMODE_Pos (0UL)

Position of BITMODE field.

Definition at line 6473 of file nrf51_bitfields.h.

◆ TIMER_INTENCLR_COMPARE0_Clear

#define TIMER_INTENCLR_COMPARE0_Clear (1UL)

Disable interrupt on write.

Definition at line 6458 of file nrf51_bitfields.h.

◆ TIMER_INTENCLR_COMPARE0_Disabled

#define TIMER_INTENCLR_COMPARE0_Disabled (0UL)

Interrupt disabled.

Definition at line 6456 of file nrf51_bitfields.h.

◆ TIMER_INTENCLR_COMPARE0_Enabled

#define TIMER_INTENCLR_COMPARE0_Enabled (1UL)

Interrupt enabled.

Definition at line 6457 of file nrf51_bitfields.h.

◆ TIMER_INTENCLR_COMPARE0_Msk

#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos)

Bit mask of COMPARE0 field.

Definition at line 6455 of file nrf51_bitfields.h.

◆ TIMER_INTENCLR_COMPARE0_Pos

#define TIMER_INTENCLR_COMPARE0_Pos (16UL)

Position of COMPARE0 field.

Definition at line 6454 of file nrf51_bitfields.h.

◆ TIMER_INTENCLR_COMPARE1_Clear

#define TIMER_INTENCLR_COMPARE1_Clear (1UL)

Disable interrupt on write.

Definition at line 6451 of file nrf51_bitfields.h.

◆ TIMER_INTENCLR_COMPARE1_Disabled

#define TIMER_INTENCLR_COMPARE1_Disabled (0UL)

Interrupt disabled.

Definition at line 6449 of file nrf51_bitfields.h.

◆ TIMER_INTENCLR_COMPARE1_Enabled

#define TIMER_INTENCLR_COMPARE1_Enabled (1UL)

Interrupt enabled.

Definition at line 6450 of file nrf51_bitfields.h.

◆ TIMER_INTENCLR_COMPARE1_Msk

#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos)

Bit mask of COMPARE1 field.

Definition at line 6448 of file nrf51_bitfields.h.

◆ TIMER_INTENCLR_COMPARE1_Pos

#define TIMER_INTENCLR_COMPARE1_Pos (17UL)

Position of COMPARE1 field.

Definition at line 6447 of file nrf51_bitfields.h.

◆ TIMER_INTENCLR_COMPARE2_Clear

#define TIMER_INTENCLR_COMPARE2_Clear (1UL)

Disable interrupt on write.

Definition at line 6444 of file nrf51_bitfields.h.

◆ TIMER_INTENCLR_COMPARE2_Disabled

#define TIMER_INTENCLR_COMPARE2_Disabled (0UL)

Interrupt disabled.

Definition at line 6442 of file nrf51_bitfields.h.

◆ TIMER_INTENCLR_COMPARE2_Enabled

#define TIMER_INTENCLR_COMPARE2_Enabled (1UL)

Interrupt enabled.

Definition at line 6443 of file nrf51_bitfields.h.

◆ TIMER_INTENCLR_COMPARE2_Msk

#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos)

Bit mask of COMPARE2 field.

Definition at line 6441 of file nrf51_bitfields.h.

◆ TIMER_INTENCLR_COMPARE2_Pos

#define TIMER_INTENCLR_COMPARE2_Pos (18UL)

Position of COMPARE2 field.

Definition at line 6440 of file nrf51_bitfields.h.

◆ TIMER_INTENCLR_COMPARE3_Clear

#define TIMER_INTENCLR_COMPARE3_Clear (1UL)

Disable interrupt on write.

Definition at line 6437 of file nrf51_bitfields.h.

◆ TIMER_INTENCLR_COMPARE3_Disabled

#define TIMER_INTENCLR_COMPARE3_Disabled (0UL)

Interrupt disabled.

Definition at line 6435 of file nrf51_bitfields.h.

◆ TIMER_INTENCLR_COMPARE3_Enabled

#define TIMER_INTENCLR_COMPARE3_Enabled (1UL)

Interrupt enabled.

Definition at line 6436 of file nrf51_bitfields.h.

◆ TIMER_INTENCLR_COMPARE3_Msk

#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos)

Bit mask of COMPARE3 field.

Definition at line 6434 of file nrf51_bitfields.h.

◆ TIMER_INTENCLR_COMPARE3_Pos

#define TIMER_INTENCLR_COMPARE3_Pos (19UL)

Position of COMPARE3 field.

Definition at line 6433 of file nrf51_bitfields.h.

◆ TIMER_INTENSET_COMPARE0_Disabled

#define TIMER_INTENSET_COMPARE0_Disabled (0UL)

Interrupt disabled.

Definition at line 6425 of file nrf51_bitfields.h.

◆ TIMER_INTENSET_COMPARE0_Enabled

#define TIMER_INTENSET_COMPARE0_Enabled (1UL)

Interrupt enabled.

Definition at line 6426 of file nrf51_bitfields.h.

◆ TIMER_INTENSET_COMPARE0_Msk

#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos)

Bit mask of COMPARE0 field.

Definition at line 6424 of file nrf51_bitfields.h.

◆ TIMER_INTENSET_COMPARE0_Pos

#define TIMER_INTENSET_COMPARE0_Pos (16UL)

Position of COMPARE0 field.

Definition at line 6423 of file nrf51_bitfields.h.

◆ TIMER_INTENSET_COMPARE0_Set

#define TIMER_INTENSET_COMPARE0_Set (1UL)

Enable interrupt on write.

Definition at line 6427 of file nrf51_bitfields.h.

◆ TIMER_INTENSET_COMPARE1_Disabled

#define TIMER_INTENSET_COMPARE1_Disabled (0UL)

Interrupt disabled.

Definition at line 6418 of file nrf51_bitfields.h.

◆ TIMER_INTENSET_COMPARE1_Enabled

#define TIMER_INTENSET_COMPARE1_Enabled (1UL)

Interrupt enabled.

Definition at line 6419 of file nrf51_bitfields.h.

◆ TIMER_INTENSET_COMPARE1_Msk

#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos)

Bit mask of COMPARE1 field.

Definition at line 6417 of file nrf51_bitfields.h.

◆ TIMER_INTENSET_COMPARE1_Pos

#define TIMER_INTENSET_COMPARE1_Pos (17UL)

Position of COMPARE1 field.

Definition at line 6416 of file nrf51_bitfields.h.

◆ TIMER_INTENSET_COMPARE1_Set

#define TIMER_INTENSET_COMPARE1_Set (1UL)

Enable interrupt on write.

Definition at line 6420 of file nrf51_bitfields.h.

◆ TIMER_INTENSET_COMPARE2_Disabled

#define TIMER_INTENSET_COMPARE2_Disabled (0UL)

Interrupt disabled.

Definition at line 6411 of file nrf51_bitfields.h.

◆ TIMER_INTENSET_COMPARE2_Enabled

#define TIMER_INTENSET_COMPARE2_Enabled (1UL)

Interrupt enabled.

Definition at line 6412 of file nrf51_bitfields.h.

◆ TIMER_INTENSET_COMPARE2_Msk

#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos)

Bit mask of COMPARE2 field.

Definition at line 6410 of file nrf51_bitfields.h.

◆ TIMER_INTENSET_COMPARE2_Pos

#define TIMER_INTENSET_COMPARE2_Pos (18UL)

Position of COMPARE2 field.

Definition at line 6409 of file nrf51_bitfields.h.

◆ TIMER_INTENSET_COMPARE2_Set

#define TIMER_INTENSET_COMPARE2_Set (1UL)

Enable interrupt on write.

Definition at line 6413 of file nrf51_bitfields.h.

◆ TIMER_INTENSET_COMPARE3_Disabled

#define TIMER_INTENSET_COMPARE3_Disabled (0UL)

Interrupt disabled.

Definition at line 6404 of file nrf51_bitfields.h.

◆ TIMER_INTENSET_COMPARE3_Enabled

#define TIMER_INTENSET_COMPARE3_Enabled (1UL)

Interrupt enabled.

Definition at line 6405 of file nrf51_bitfields.h.

◆ TIMER_INTENSET_COMPARE3_Msk

#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos)

Bit mask of COMPARE3 field.

Definition at line 6403 of file nrf51_bitfields.h.

◆ TIMER_INTENSET_COMPARE3_Pos

#define TIMER_INTENSET_COMPARE3_Pos (19UL)

Position of COMPARE3 field.

Definition at line 6402 of file nrf51_bitfields.h.

◆ TIMER_INTENSET_COMPARE3_Set

#define TIMER_INTENSET_COMPARE3_Set (1UL)

Enable interrupt on write.

Definition at line 6406 of file nrf51_bitfields.h.

◆ TIMER_MODE_MODE_Counter

#define TIMER_MODE_MODE_Counter (1UL)

Timer in Counter mode.

Definition at line 6467 of file nrf51_bitfields.h.

◆ TIMER_MODE_MODE_Msk

#define TIMER_MODE_MODE_Msk (0x1UL << TIMER_MODE_MODE_Pos)

Bit mask of MODE field.

Definition at line 6465 of file nrf51_bitfields.h.

◆ TIMER_MODE_MODE_Pos

#define TIMER_MODE_MODE_Pos (0UL)

Position of MODE field.

Definition at line 6464 of file nrf51_bitfields.h.

◆ TIMER_MODE_MODE_Timer

#define TIMER_MODE_MODE_Timer (0UL)

Timer in Normal mode.

Definition at line 6466 of file nrf51_bitfields.h.

◆ TIMER_POWER_POWER_Disabled

#define TIMER_POWER_POWER_Disabled (0UL)

Module power disabled.

Definition at line 6493 of file nrf51_bitfields.h.

◆ TIMER_POWER_POWER_Enabled

#define TIMER_POWER_POWER_Enabled (1UL)

Module power enabled.

Definition at line 6494 of file nrf51_bitfields.h.

◆ TIMER_POWER_POWER_Msk

#define TIMER_POWER_POWER_Msk (0x1UL << TIMER_POWER_POWER_Pos)

Bit mask of POWER field.

Definition at line 6492 of file nrf51_bitfields.h.

◆ TIMER_POWER_POWER_Pos

#define TIMER_POWER_POWER_Pos (0UL)

Position of POWER field.

Definition at line 6491 of file nrf51_bitfields.h.

◆ TIMER_PRESCALER_PRESCALER_Msk

#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos)

Bit mask of PRESCALER field.

Definition at line 6485 of file nrf51_bitfields.h.

◆ TIMER_PRESCALER_PRESCALER_Pos

#define TIMER_PRESCALER_PRESCALER_Pos (0UL)

Position of PRESCALER field.

Definition at line 6484 of file nrf51_bitfields.h.

◆ TIMER_SHORTS_COMPARE0_CLEAR_Disabled

#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL)

Shortcut disabled.

Definition at line 6395 of file nrf51_bitfields.h.

◆ TIMER_SHORTS_COMPARE0_CLEAR_Enabled

#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL)

Shortcut enabled.

Definition at line 6396 of file nrf51_bitfields.h.

◆ TIMER_SHORTS_COMPARE0_CLEAR_Msk

#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos)

Bit mask of COMPARE0_CLEAR field.

Definition at line 6394 of file nrf51_bitfields.h.

◆ TIMER_SHORTS_COMPARE0_CLEAR_Pos

#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL)

Position of COMPARE0_CLEAR field.

Definition at line 6393 of file nrf51_bitfields.h.

◆ TIMER_SHORTS_COMPARE0_STOP_Disabled

#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL)

Shortcut disabled.

Definition at line 6371 of file nrf51_bitfields.h.

◆ TIMER_SHORTS_COMPARE0_STOP_Enabled

#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL)

Shortcut enabled.

Definition at line 6372 of file nrf51_bitfields.h.

◆ TIMER_SHORTS_COMPARE0_STOP_Msk

#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos)

Bit mask of COMPARE0_STOP field.

Definition at line 6370 of file nrf51_bitfields.h.

◆ TIMER_SHORTS_COMPARE0_STOP_Pos

#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL)

Position of COMPARE0_STOP field.

Definition at line 6369 of file nrf51_bitfields.h.

◆ TIMER_SHORTS_COMPARE1_CLEAR_Disabled

#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL)

Shortcut disabled.

Definition at line 6389 of file nrf51_bitfields.h.

◆ TIMER_SHORTS_COMPARE1_CLEAR_Enabled

#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL)

Shortcut enabled.

Definition at line 6390 of file nrf51_bitfields.h.

◆ TIMER_SHORTS_COMPARE1_CLEAR_Msk

#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos)

Bit mask of COMPARE1_CLEAR field.

Definition at line 6388 of file nrf51_bitfields.h.

◆ TIMER_SHORTS_COMPARE1_CLEAR_Pos

#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL)

Position of COMPARE1_CLEAR field.

Definition at line 6387 of file nrf51_bitfields.h.

◆ TIMER_SHORTS_COMPARE1_STOP_Disabled

#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL)

Shortcut disabled.

Definition at line 6365 of file nrf51_bitfields.h.

◆ TIMER_SHORTS_COMPARE1_STOP_Enabled

#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL)

Shortcut enabled.

Definition at line 6366 of file nrf51_bitfields.h.

◆ TIMER_SHORTS_COMPARE1_STOP_Msk

#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos)

Bit mask of COMPARE1_STOP field.

Definition at line 6364 of file nrf51_bitfields.h.

◆ TIMER_SHORTS_COMPARE1_STOP_Pos

#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL)

Position of COMPARE1_STOP field.

Definition at line 6363 of file nrf51_bitfields.h.

◆ TIMER_SHORTS_COMPARE2_CLEAR_Disabled

#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL)

Shortcut disabled.

Definition at line 6383 of file nrf51_bitfields.h.

◆ TIMER_SHORTS_COMPARE2_CLEAR_Enabled

#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL)

Shortcut enabled.

Definition at line 6384 of file nrf51_bitfields.h.

◆ TIMER_SHORTS_COMPARE2_CLEAR_Msk

#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos)

Bit mask of COMPARE2_CLEAR field.

Definition at line 6382 of file nrf51_bitfields.h.

◆ TIMER_SHORTS_COMPARE2_CLEAR_Pos

#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL)

Position of COMPARE2_CLEAR field.

Definition at line 6381 of file nrf51_bitfields.h.

◆ TIMER_SHORTS_COMPARE2_STOP_Disabled

#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL)

Shortcut disabled.

Definition at line 6359 of file nrf51_bitfields.h.

◆ TIMER_SHORTS_COMPARE2_STOP_Enabled

#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL)

Shortcut enabled.

Definition at line 6360 of file nrf51_bitfields.h.

◆ TIMER_SHORTS_COMPARE2_STOP_Msk

#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos)

Bit mask of COMPARE2_STOP field.

Definition at line 6358 of file nrf51_bitfields.h.

◆ TIMER_SHORTS_COMPARE2_STOP_Pos

#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL)

Position of COMPARE2_STOP field.

Definition at line 6357 of file nrf51_bitfields.h.

◆ TIMER_SHORTS_COMPARE3_CLEAR_Disabled

#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL)

Shortcut disabled.

Definition at line 6377 of file nrf51_bitfields.h.

◆ TIMER_SHORTS_COMPARE3_CLEAR_Enabled

#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL)

Shortcut enabled.

Definition at line 6378 of file nrf51_bitfields.h.

◆ TIMER_SHORTS_COMPARE3_CLEAR_Msk

#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos)

Bit mask of COMPARE3_CLEAR field.

Definition at line 6376 of file nrf51_bitfields.h.

◆ TIMER_SHORTS_COMPARE3_CLEAR_Pos

#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL)

Position of COMPARE3_CLEAR field.

Definition at line 6375 of file nrf51_bitfields.h.

◆ TIMER_SHORTS_COMPARE3_STOP_Disabled

#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL)

Shortcut disabled.

Definition at line 6353 of file nrf51_bitfields.h.

◆ TIMER_SHORTS_COMPARE3_STOP_Enabled

#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL)

Shortcut enabled.

Definition at line 6354 of file nrf51_bitfields.h.

◆ TIMER_SHORTS_COMPARE3_STOP_Msk

#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos)

Bit mask of COMPARE3_STOP field.

Definition at line 6352 of file nrf51_bitfields.h.

◆ TIMER_SHORTS_COMPARE3_STOP_Pos

#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL)

Position of COMPARE3_STOP field.

Definition at line 6351 of file nrf51_bitfields.h.

◆ TWI_ADDRESS_ADDRESS_Msk

#define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos)

Bit mask of ADDRESS field.

Definition at line 6667 of file nrf51_bitfields.h.

◆ TWI_ADDRESS_ADDRESS_Pos

#define TWI_ADDRESS_ADDRESS_Pos (0UL)

Position of ADDRESS field.

Definition at line 6666 of file nrf51_bitfields.h.

◆ TWI_ENABLE_ENABLE_Disabled

#define TWI_ENABLE_ENABLE_Disabled (0x00UL)

Disabled.

Definition at line 6635 of file nrf51_bitfields.h.

◆ TWI_ENABLE_ENABLE_Enabled

#define TWI_ENABLE_ENABLE_Enabled (0x05UL)

Enabled.

Definition at line 6636 of file nrf51_bitfields.h.

◆ TWI_ENABLE_ENABLE_Msk

#define TWI_ENABLE_ENABLE_Msk (0x7UL << TWI_ENABLE_ENABLE_Pos)

Bit mask of ENABLE field.

Definition at line 6634 of file nrf51_bitfields.h.

◆ TWI_ENABLE_ENABLE_Pos

#define TWI_ENABLE_ENABLE_Pos (0UL)

Position of ENABLE field.

Definition at line 6633 of file nrf51_bitfields.h.

◆ TWI_ERRORSRC_ANACK_Clear

#define TWI_ERRORSRC_ANACK_Clear (1UL)

Clear error on write.

Definition at line 6620 of file nrf51_bitfields.h.

◆ TWI_ERRORSRC_ANACK_Msk

#define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos)

Bit mask of ANACK field.

Definition at line 6617 of file nrf51_bitfields.h.

◆ TWI_ERRORSRC_ANACK_NotPresent

#define TWI_ERRORSRC_ANACK_NotPresent (0UL)

Error not present.

Definition at line 6618 of file nrf51_bitfields.h.

◆ TWI_ERRORSRC_ANACK_Pos

#define TWI_ERRORSRC_ANACK_Pos (1UL)

Position of ANACK field.

Definition at line 6616 of file nrf51_bitfields.h.

◆ TWI_ERRORSRC_ANACK_Present

#define TWI_ERRORSRC_ANACK_Present (1UL)

Error present.

Definition at line 6619 of file nrf51_bitfields.h.

◆ TWI_ERRORSRC_DNACK_Clear

#define TWI_ERRORSRC_DNACK_Clear (1UL)

Clear error on write.

Definition at line 6613 of file nrf51_bitfields.h.

◆ TWI_ERRORSRC_DNACK_Msk

#define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos)

Bit mask of DNACK field.

Definition at line 6610 of file nrf51_bitfields.h.

◆ TWI_ERRORSRC_DNACK_NotPresent

#define TWI_ERRORSRC_DNACK_NotPresent (0UL)

Error not present.

Definition at line 6611 of file nrf51_bitfields.h.

◆ TWI_ERRORSRC_DNACK_Pos

#define TWI_ERRORSRC_DNACK_Pos (2UL)

Position of DNACK field.

Definition at line 6609 of file nrf51_bitfields.h.

◆ TWI_ERRORSRC_DNACK_Present

#define TWI_ERRORSRC_DNACK_Present (1UL)

Error present.

Definition at line 6612 of file nrf51_bitfields.h.

◆ TWI_ERRORSRC_OVERRUN_Clear

#define TWI_ERRORSRC_OVERRUN_Clear (1UL)

Clear error on write.

Definition at line 6627 of file nrf51_bitfields.h.

◆ TWI_ERRORSRC_OVERRUN_Msk

#define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos)

Bit mask of OVERRUN field.

Definition at line 6624 of file nrf51_bitfields.h.

◆ TWI_ERRORSRC_OVERRUN_NotPresent

#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL)

Error not present.

Definition at line 6625 of file nrf51_bitfields.h.

◆ TWI_ERRORSRC_OVERRUN_Pos

#define TWI_ERRORSRC_OVERRUN_Pos (0UL)

Position of OVERRUN field.

Definition at line 6623 of file nrf51_bitfields.h.

◆ TWI_ERRORSRC_OVERRUN_Present

#define TWI_ERRORSRC_OVERRUN_Present (1UL)

Error present.

Definition at line 6626 of file nrf51_bitfields.h.

◆ TWI_FREQUENCY_FREQUENCY_K100

#define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL)

100 kbps.

Definition at line 6658 of file nrf51_bitfields.h.

◆ TWI_FREQUENCY_FREQUENCY_K250

#define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL)

250 kbps.

Definition at line 6659 of file nrf51_bitfields.h.

◆ TWI_FREQUENCY_FREQUENCY_K400

#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL)

400 kbps.

Definition at line 6660 of file nrf51_bitfields.h.

◆ TWI_FREQUENCY_FREQUENCY_Msk

#define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos)

Bit mask of FREQUENCY field.

Definition at line 6657 of file nrf51_bitfields.h.

◆ TWI_FREQUENCY_FREQUENCY_Pos

#define TWI_FREQUENCY_FREQUENCY_Pos (0UL)

Position of FREQUENCY field.

Definition at line 6656 of file nrf51_bitfields.h.

◆ TWI_INTENCLR_BB_Clear

#define TWI_INTENCLR_BB_Clear (1UL)

Disable interrupt on write.

Definition at line 6575 of file nrf51_bitfields.h.

◆ TWI_INTENCLR_BB_Disabled

#define TWI_INTENCLR_BB_Disabled (0UL)

Interrupt disabled.

Definition at line 6573 of file nrf51_bitfields.h.

◆ TWI_INTENCLR_BB_Enabled

#define TWI_INTENCLR_BB_Enabled (1UL)

Interrupt enabled.

Definition at line 6574 of file nrf51_bitfields.h.

◆ TWI_INTENCLR_BB_Msk

#define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos)

Bit mask of BB field.

Definition at line 6572 of file nrf51_bitfields.h.

◆ TWI_INTENCLR_BB_Pos

#define TWI_INTENCLR_BB_Pos (14UL)

Position of BB field.

Definition at line 6571 of file nrf51_bitfields.h.

◆ TWI_INTENCLR_ERROR_Clear

#define TWI_INTENCLR_ERROR_Clear (1UL)

Disable interrupt on write.

Definition at line 6582 of file nrf51_bitfields.h.

◆ TWI_INTENCLR_ERROR_Disabled

#define TWI_INTENCLR_ERROR_Disabled (0UL)

Interrupt disabled.

Definition at line 6580 of file nrf51_bitfields.h.

◆ TWI_INTENCLR_ERROR_Enabled

#define TWI_INTENCLR_ERROR_Enabled (1UL)

Interrupt enabled.

Definition at line 6581 of file nrf51_bitfields.h.

◆ TWI_INTENCLR_ERROR_Msk

#define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos)

Bit mask of ERROR field.

Definition at line 6579 of file nrf51_bitfields.h.

◆ TWI_INTENCLR_ERROR_Pos

#define TWI_INTENCLR_ERROR_Pos (9UL)

Position of ERROR field.

Definition at line 6578 of file nrf51_bitfields.h.

◆ TWI_INTENCLR_RXDREADY_Clear

#define TWI_INTENCLR_RXDREADY_Clear (1UL)

Disable interrupt on write.

Definition at line 6596 of file nrf51_bitfields.h.

◆ TWI_INTENCLR_RXDREADY_Disabled

#define TWI_INTENCLR_RXDREADY_Disabled (0UL)

Interrupt disabled.

Definition at line 6594 of file nrf51_bitfields.h.

◆ TWI_INTENCLR_RXDREADY_Enabled

#define TWI_INTENCLR_RXDREADY_Enabled (1UL)

Interrupt enabled.

Definition at line 6595 of file nrf51_bitfields.h.

◆ TWI_INTENCLR_RXDREADY_Msk

#define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos)

Bit mask of RXDREADY field.

Definition at line 6593 of file nrf51_bitfields.h.

◆ TWI_INTENCLR_RXDREADY_Pos

#define TWI_INTENCLR_RXDREADY_Pos (2UL)

Position of RXDREADY field.

Definition at line 6592 of file nrf51_bitfields.h.

◆ TWI_INTENCLR_STOPPED_Clear

#define TWI_INTENCLR_STOPPED_Clear (1UL)

Disable interrupt on write.

Definition at line 6603 of file nrf51_bitfields.h.

◆ TWI_INTENCLR_STOPPED_Disabled

#define TWI_INTENCLR_STOPPED_Disabled (0UL)

Interrupt disabled.

Definition at line 6601 of file nrf51_bitfields.h.

◆ TWI_INTENCLR_STOPPED_Enabled

#define TWI_INTENCLR_STOPPED_Enabled (1UL)

Interrupt enabled.

Definition at line 6602 of file nrf51_bitfields.h.

◆ TWI_INTENCLR_STOPPED_Msk

#define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos)

Bit mask of STOPPED field.

Definition at line 6600 of file nrf51_bitfields.h.

◆ TWI_INTENCLR_STOPPED_Pos

#define TWI_INTENCLR_STOPPED_Pos (1UL)

Position of STOPPED field.

Definition at line 6599 of file nrf51_bitfields.h.

◆ TWI_INTENCLR_SUSPENDED_Clear

#define TWI_INTENCLR_SUSPENDED_Clear (1UL)

Disable interrupt on write.

Definition at line 6568 of file nrf51_bitfields.h.

◆ TWI_INTENCLR_SUSPENDED_Disabled

#define TWI_INTENCLR_SUSPENDED_Disabled (0UL)

Interrupt disabled.

Definition at line 6566 of file nrf51_bitfields.h.

◆ TWI_INTENCLR_SUSPENDED_Enabled

#define TWI_INTENCLR_SUSPENDED_Enabled (1UL)

Interrupt enabled.

Definition at line 6567 of file nrf51_bitfields.h.

◆ TWI_INTENCLR_SUSPENDED_Msk

#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos)

Bit mask of SUSPENDED field.

Definition at line 6565 of file nrf51_bitfields.h.

◆ TWI_INTENCLR_SUSPENDED_Pos

#define TWI_INTENCLR_SUSPENDED_Pos (18UL)

Position of SUSPENDED field.

Definition at line 6564 of file nrf51_bitfields.h.

◆ TWI_INTENCLR_TXDSENT_Clear

#define TWI_INTENCLR_TXDSENT_Clear (1UL)

Disable interrupt on write.

Definition at line 6589 of file nrf51_bitfields.h.

◆ TWI_INTENCLR_TXDSENT_Disabled

#define TWI_INTENCLR_TXDSENT_Disabled (0UL)

Interrupt disabled.

Definition at line 6587 of file nrf51_bitfields.h.

◆ TWI_INTENCLR_TXDSENT_Enabled

#define TWI_INTENCLR_TXDSENT_Enabled (1UL)

Interrupt enabled.

Definition at line 6588 of file nrf51_bitfields.h.

◆ TWI_INTENCLR_TXDSENT_Msk

#define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos)

Bit mask of TXDSENT field.

Definition at line 6586 of file nrf51_bitfields.h.

◆ TWI_INTENCLR_TXDSENT_Pos

#define TWI_INTENCLR_TXDSENT_Pos (7UL)

Position of TXDSENT field.

Definition at line 6585 of file nrf51_bitfields.h.

◆ TWI_INTENSET_BB_Disabled

#define TWI_INTENSET_BB_Disabled (0UL)

Interrupt disabled.

Definition at line 6528 of file nrf51_bitfields.h.

◆ TWI_INTENSET_BB_Enabled

#define TWI_INTENSET_BB_Enabled (1UL)

Interrupt enabled.

Definition at line 6529 of file nrf51_bitfields.h.

◆ TWI_INTENSET_BB_Msk

#define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos)

Bit mask of BB field.

Definition at line 6527 of file nrf51_bitfields.h.

◆ TWI_INTENSET_BB_Pos

#define TWI_INTENSET_BB_Pos (14UL)

Position of BB field.

Definition at line 6526 of file nrf51_bitfields.h.

◆ TWI_INTENSET_BB_Set

#define TWI_INTENSET_BB_Set (1UL)

Enable interrupt on write.

Definition at line 6530 of file nrf51_bitfields.h.

◆ TWI_INTENSET_ERROR_Disabled

#define TWI_INTENSET_ERROR_Disabled (0UL)

Interrupt disabled.

Definition at line 6535 of file nrf51_bitfields.h.

◆ TWI_INTENSET_ERROR_Enabled

#define TWI_INTENSET_ERROR_Enabled (1UL)

Interrupt enabled.

Definition at line 6536 of file nrf51_bitfields.h.

◆ TWI_INTENSET_ERROR_Msk

#define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos)

Bit mask of ERROR field.

Definition at line 6534 of file nrf51_bitfields.h.

◆ TWI_INTENSET_ERROR_Pos

#define TWI_INTENSET_ERROR_Pos (9UL)

Position of ERROR field.

Definition at line 6533 of file nrf51_bitfields.h.

◆ TWI_INTENSET_ERROR_Set

#define TWI_INTENSET_ERROR_Set (1UL)

Enable interrupt on write.

Definition at line 6537 of file nrf51_bitfields.h.

◆ TWI_INTENSET_RXDREADY_Disabled

#define TWI_INTENSET_RXDREADY_Disabled (0UL)

Interrupt disabled.

Definition at line 6549 of file nrf51_bitfields.h.

◆ TWI_INTENSET_RXDREADY_Enabled

#define TWI_INTENSET_RXDREADY_Enabled (1UL)

Interrupt enabled.

Definition at line 6550 of file nrf51_bitfields.h.

◆ TWI_INTENSET_RXDREADY_Msk

#define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos)

Bit mask of RXDREADY field.

Definition at line 6548 of file nrf51_bitfields.h.

◆ TWI_INTENSET_RXDREADY_Pos

#define TWI_INTENSET_RXDREADY_Pos (2UL)

Position of RXDREADY field.

Definition at line 6547 of file nrf51_bitfields.h.

◆ TWI_INTENSET_RXDREADY_Set

#define TWI_INTENSET_RXDREADY_Set (1UL)

Enable interrupt on write.

Definition at line 6551 of file nrf51_bitfields.h.

◆ TWI_INTENSET_STOPPED_Disabled

#define TWI_INTENSET_STOPPED_Disabled (0UL)

Interrupt disabled.

Definition at line 6556 of file nrf51_bitfields.h.

◆ TWI_INTENSET_STOPPED_Enabled

#define TWI_INTENSET_STOPPED_Enabled (1UL)

Interrupt enabled.

Definition at line 6557 of file nrf51_bitfields.h.

◆ TWI_INTENSET_STOPPED_Msk

#define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos)

Bit mask of STOPPED field.

Definition at line 6555 of file nrf51_bitfields.h.

◆ TWI_INTENSET_STOPPED_Pos

#define TWI_INTENSET_STOPPED_Pos (1UL)

Position of STOPPED field.

Definition at line 6554 of file nrf51_bitfields.h.

◆ TWI_INTENSET_STOPPED_Set

#define TWI_INTENSET_STOPPED_Set (1UL)

Enable interrupt on write.

Definition at line 6558 of file nrf51_bitfields.h.

◆ TWI_INTENSET_SUSPENDED_Disabled

#define TWI_INTENSET_SUSPENDED_Disabled (0UL)

Interrupt disabled.

Definition at line 6521 of file nrf51_bitfields.h.

◆ TWI_INTENSET_SUSPENDED_Enabled

#define TWI_INTENSET_SUSPENDED_Enabled (1UL)

Interrupt enabled.

Definition at line 6522 of file nrf51_bitfields.h.

◆ TWI_INTENSET_SUSPENDED_Msk

#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos)

Bit mask of SUSPENDED field.

Definition at line 6520 of file nrf51_bitfields.h.

◆ TWI_INTENSET_SUSPENDED_Pos

#define TWI_INTENSET_SUSPENDED_Pos (18UL)

Position of SUSPENDED field.

Definition at line 6519 of file nrf51_bitfields.h.

◆ TWI_INTENSET_SUSPENDED_Set

#define TWI_INTENSET_SUSPENDED_Set (1UL)

Enable interrupt on write.

Definition at line 6523 of file nrf51_bitfields.h.

◆ TWI_INTENSET_TXDSENT_Disabled

#define TWI_INTENSET_TXDSENT_Disabled (0UL)

Interrupt disabled.

Definition at line 6542 of file nrf51_bitfields.h.

◆ TWI_INTENSET_TXDSENT_Enabled

#define TWI_INTENSET_TXDSENT_Enabled (1UL)

Interrupt enabled.

Definition at line 6543 of file nrf51_bitfields.h.

◆ TWI_INTENSET_TXDSENT_Msk

#define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos)

Bit mask of TXDSENT field.

Definition at line 6541 of file nrf51_bitfields.h.

◆ TWI_INTENSET_TXDSENT_Pos

#define TWI_INTENSET_TXDSENT_Pos (7UL)

Position of TXDSENT field.

Definition at line 6540 of file nrf51_bitfields.h.

◆ TWI_INTENSET_TXDSENT_Set

#define TWI_INTENSET_TXDSENT_Set (1UL)

Enable interrupt on write.

Definition at line 6544 of file nrf51_bitfields.h.

◆ TWI_POWER_POWER_Disabled

#define TWI_POWER_POWER_Disabled (0UL)

Module power disabled.

Definition at line 6675 of file nrf51_bitfields.h.

◆ TWI_POWER_POWER_Enabled

#define TWI_POWER_POWER_Enabled (1UL)

Module power enabled.

Definition at line 6676 of file nrf51_bitfields.h.

◆ TWI_POWER_POWER_Msk

#define TWI_POWER_POWER_Msk (0x1UL << TWI_POWER_POWER_Pos)

Bit mask of POWER field.

Definition at line 6674 of file nrf51_bitfields.h.

◆ TWI_POWER_POWER_Pos

#define TWI_POWER_POWER_Pos (0UL)

Position of POWER field.

Definition at line 6673 of file nrf51_bitfields.h.

◆ TWI_RXD_RXD_Msk

#define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos)

Bit mask of RXD field.

Definition at line 6643 of file nrf51_bitfields.h.

◆ TWI_RXD_RXD_Pos

#define TWI_RXD_RXD_Pos (0UL)

Position of RXD field.

Definition at line 6642 of file nrf51_bitfields.h.

◆ TWI_SHORTS_BB_STOP_Disabled

#define TWI_SHORTS_BB_STOP_Disabled (0UL)

Shortcut disabled.

Definition at line 6506 of file nrf51_bitfields.h.

◆ TWI_SHORTS_BB_STOP_Enabled

#define TWI_SHORTS_BB_STOP_Enabled (1UL)

Shortcut enabled.

Definition at line 6507 of file nrf51_bitfields.h.

◆ TWI_SHORTS_BB_STOP_Msk

#define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos)

Bit mask of BB_STOP field.

Definition at line 6505 of file nrf51_bitfields.h.

◆ TWI_SHORTS_BB_STOP_Pos

#define TWI_SHORTS_BB_STOP_Pos (1UL)

Position of BB_STOP field.

Definition at line 6504 of file nrf51_bitfields.h.

◆ TWI_SHORTS_BB_SUSPEND_Disabled

#define TWI_SHORTS_BB_SUSPEND_Disabled (0UL)

Shortcut disabled.

Definition at line 6512 of file nrf51_bitfields.h.

◆ TWI_SHORTS_BB_SUSPEND_Enabled

#define TWI_SHORTS_BB_SUSPEND_Enabled (1UL)

Shortcut enabled.

Definition at line 6513 of file nrf51_bitfields.h.

◆ TWI_SHORTS_BB_SUSPEND_Msk

#define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos)

Bit mask of BB_SUSPEND field.

Definition at line 6511 of file nrf51_bitfields.h.

◆ TWI_SHORTS_BB_SUSPEND_Pos

#define TWI_SHORTS_BB_SUSPEND_Pos (0UL)

Position of BB_SUSPEND field.

Definition at line 6510 of file nrf51_bitfields.h.

◆ TWI_TXD_TXD_Msk

#define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos)

Bit mask of TXD field.

Definition at line 6650 of file nrf51_bitfields.h.

◆ TWI_TXD_TXD_Pos

#define TWI_TXD_TXD_Pos (0UL)

Position of TXD field.

Definition at line 6649 of file nrf51_bitfields.h.

◆ UART_BAUDRATE_BAUDRATE_Baud115200

#define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL)

115200 baud.

Definition at line 6842 of file nrf51_bitfields.h.

◆ UART_BAUDRATE_BAUDRATE_Baud1200

#define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL)

1200 baud.

Definition at line 6832 of file nrf51_bitfields.h.

◆ UART_BAUDRATE_BAUDRATE_Baud14400

#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL)

14400 baud.

Definition at line 6836 of file nrf51_bitfields.h.

◆ UART_BAUDRATE_BAUDRATE_Baud19200

#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL)

19200 baud.

Definition at line 6837 of file nrf51_bitfields.h.

◆ UART_BAUDRATE_BAUDRATE_Baud1M

#define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL)

1M baud.

Definition at line 6847 of file nrf51_bitfields.h.

◆ UART_BAUDRATE_BAUDRATE_Baud230400

#define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL)

230400 baud.

Definition at line 6843 of file nrf51_bitfields.h.

◆ UART_BAUDRATE_BAUDRATE_Baud2400

#define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL)

2400 baud.

Definition at line 6833 of file nrf51_bitfields.h.

◆ UART_BAUDRATE_BAUDRATE_Baud250000

#define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL)

250000 baud.

Definition at line 6844 of file nrf51_bitfields.h.

◆ UART_BAUDRATE_BAUDRATE_Baud28800

#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL)

28800 baud.

Definition at line 6838 of file nrf51_bitfields.h.

◆ UART_BAUDRATE_BAUDRATE_Baud38400

#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL)

38400 baud.

Definition at line 6839 of file nrf51_bitfields.h.

◆ UART_BAUDRATE_BAUDRATE_Baud460800

#define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL)

460800 baud.

Definition at line 6845 of file nrf51_bitfields.h.

◆ UART_BAUDRATE_BAUDRATE_Baud4800

#define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL)

4800 baud.

Definition at line 6834 of file nrf51_bitfields.h.

◆ UART_BAUDRATE_BAUDRATE_Baud57600

#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL)

57600 baud.

Definition at line 6840 of file nrf51_bitfields.h.

◆ UART_BAUDRATE_BAUDRATE_Baud76800

#define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL)

76800 baud.

Definition at line 6841 of file nrf51_bitfields.h.

◆ UART_BAUDRATE_BAUDRATE_Baud921600

#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL)

921600 baud.

Definition at line 6846 of file nrf51_bitfields.h.

◆ UART_BAUDRATE_BAUDRATE_Baud9600

#define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL)

9600 baud.

Definition at line 6835 of file nrf51_bitfields.h.

◆ UART_BAUDRATE_BAUDRATE_Msk

#define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos)

Bit mask of BAUDRATE field.

Definition at line 6831 of file nrf51_bitfields.h.

◆ UART_BAUDRATE_BAUDRATE_Pos

#define UART_BAUDRATE_BAUDRATE_Pos (0UL)

Position of BAUDRATE field.

Definition at line 6830 of file nrf51_bitfields.h.

◆ UART_CONFIG_HWFC_Disabled

#define UART_CONFIG_HWFC_Disabled (0UL)

Hardware flow control disabled.

Definition at line 6861 of file nrf51_bitfields.h.

◆ UART_CONFIG_HWFC_Enabled

#define UART_CONFIG_HWFC_Enabled (1UL)

Hardware flow control enabled.

Definition at line 6862 of file nrf51_bitfields.h.

◆ UART_CONFIG_HWFC_Msk

#define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos)

Bit mask of HWFC field.

Definition at line 6860 of file nrf51_bitfields.h.

◆ UART_CONFIG_HWFC_Pos

#define UART_CONFIG_HWFC_Pos (0UL)

Position of HWFC field.

Definition at line 6859 of file nrf51_bitfields.h.

◆ UART_CONFIG_PARITY_Excluded

#define UART_CONFIG_PARITY_Excluded (0UL)

Parity bit excluded.

Definition at line 6855 of file nrf51_bitfields.h.

◆ UART_CONFIG_PARITY_Included

#define UART_CONFIG_PARITY_Included (7UL)

Parity bit included.

Definition at line 6856 of file nrf51_bitfields.h.

◆ UART_CONFIG_PARITY_Msk

#define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos)

Bit mask of PARITY field.

Definition at line 6854 of file nrf51_bitfields.h.

◆ UART_CONFIG_PARITY_Pos

#define UART_CONFIG_PARITY_Pos (1UL)

Position of PARITY field.

Definition at line 6853 of file nrf51_bitfields.h.

◆ UART_ENABLE_ENABLE_Disabled

#define UART_ENABLE_ENABLE_Disabled (0x00UL)

UART disabled.

Definition at line 6809 of file nrf51_bitfields.h.

◆ UART_ENABLE_ENABLE_Enabled

#define UART_ENABLE_ENABLE_Enabled (0x04UL)

UART enabled.

Definition at line 6810 of file nrf51_bitfields.h.

◆ UART_ENABLE_ENABLE_Msk

#define UART_ENABLE_ENABLE_Msk (0x7UL << UART_ENABLE_ENABLE_Pos)

Bit mask of ENABLE field.

Definition at line 6808 of file nrf51_bitfields.h.

◆ UART_ENABLE_ENABLE_Pos

#define UART_ENABLE_ENABLE_Pos (0UL)

Position of ENABLE field.

Definition at line 6807 of file nrf51_bitfields.h.

◆ UART_ERRORSRC_BREAK_Clear

#define UART_ERRORSRC_BREAK_Clear (1UL)

Clear error on write.

Definition at line 6780 of file nrf51_bitfields.h.

◆ UART_ERRORSRC_BREAK_Msk

#define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos)

Bit mask of BREAK field.

Definition at line 6777 of file nrf51_bitfields.h.

◆ UART_ERRORSRC_BREAK_NotPresent

#define UART_ERRORSRC_BREAK_NotPresent (0UL)

Error not present.

Definition at line 6778 of file nrf51_bitfields.h.

◆ UART_ERRORSRC_BREAK_Pos

#define UART_ERRORSRC_BREAK_Pos (3UL)

Position of BREAK field.

Definition at line 6776 of file nrf51_bitfields.h.

◆ UART_ERRORSRC_BREAK_Present

#define UART_ERRORSRC_BREAK_Present (1UL)

Error present.

Definition at line 6779 of file nrf51_bitfields.h.

◆ UART_ERRORSRC_FRAMING_Clear

#define UART_ERRORSRC_FRAMING_Clear (1UL)

Clear error on write.

Definition at line 6787 of file nrf51_bitfields.h.

◆ UART_ERRORSRC_FRAMING_Msk

#define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos)

Bit mask of FRAMING field.

Definition at line 6784 of file nrf51_bitfields.h.

◆ UART_ERRORSRC_FRAMING_NotPresent

#define UART_ERRORSRC_FRAMING_NotPresent (0UL)

Error not present.

Definition at line 6785 of file nrf51_bitfields.h.

◆ UART_ERRORSRC_FRAMING_Pos

#define UART_ERRORSRC_FRAMING_Pos (2UL)

Position of FRAMING field.

Definition at line 6783 of file nrf51_bitfields.h.

◆ UART_ERRORSRC_FRAMING_Present

#define UART_ERRORSRC_FRAMING_Present (1UL)

Error present.

Definition at line 6786 of file nrf51_bitfields.h.

◆ UART_ERRORSRC_OVERRUN_Clear

#define UART_ERRORSRC_OVERRUN_Clear (1UL)

Clear error on write.

Definition at line 6801 of file nrf51_bitfields.h.

◆ UART_ERRORSRC_OVERRUN_Msk

#define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos)

Bit mask of OVERRUN field.

Definition at line 6798 of file nrf51_bitfields.h.

◆ UART_ERRORSRC_OVERRUN_NotPresent

#define UART_ERRORSRC_OVERRUN_NotPresent (0UL)

Error not present.

Definition at line 6799 of file nrf51_bitfields.h.

◆ UART_ERRORSRC_OVERRUN_Pos

#define UART_ERRORSRC_OVERRUN_Pos (0UL)

Position of OVERRUN field.

Definition at line 6797 of file nrf51_bitfields.h.

◆ UART_ERRORSRC_OVERRUN_Present

#define UART_ERRORSRC_OVERRUN_Present (1UL)

Error present.

Definition at line 6800 of file nrf51_bitfields.h.

◆ UART_ERRORSRC_PARITY_Clear

#define UART_ERRORSRC_PARITY_Clear (1UL)

Clear error on write.

Definition at line 6794 of file nrf51_bitfields.h.

◆ UART_ERRORSRC_PARITY_Msk

#define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos)

Bit mask of PARITY field.

Definition at line 6791 of file nrf51_bitfields.h.

◆ UART_ERRORSRC_PARITY_NotPresent

#define UART_ERRORSRC_PARITY_NotPresent (0UL)

Error not present.

Definition at line 6792 of file nrf51_bitfields.h.

◆ UART_ERRORSRC_PARITY_Pos

#define UART_ERRORSRC_PARITY_Pos (1UL)

Position of PARITY field.

Definition at line 6790 of file nrf51_bitfields.h.

◆ UART_ERRORSRC_PARITY_Present

#define UART_ERRORSRC_PARITY_Present (1UL)

Error present.

Definition at line 6793 of file nrf51_bitfields.h.

◆ UART_INTENCLR_CTS_Clear

#define UART_INTENCLR_CTS_Clear (1UL)

Disable interrupt on write.

Definition at line 6770 of file nrf51_bitfields.h.

◆ UART_INTENCLR_CTS_Disabled

#define UART_INTENCLR_CTS_Disabled (0UL)

Interrupt disabled.

Definition at line 6768 of file nrf51_bitfields.h.

◆ UART_INTENCLR_CTS_Enabled

#define UART_INTENCLR_CTS_Enabled (1UL)

Interrupt enabled.

Definition at line 6769 of file nrf51_bitfields.h.

◆ UART_INTENCLR_CTS_Msk

#define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos)

Bit mask of CTS field.

Definition at line 6767 of file nrf51_bitfields.h.

◆ UART_INTENCLR_CTS_Pos

#define UART_INTENCLR_CTS_Pos (0UL)

Position of CTS field.

Definition at line 6766 of file nrf51_bitfields.h.

◆ UART_INTENCLR_ERROR_Clear

#define UART_INTENCLR_ERROR_Clear (1UL)

Disable interrupt on write.

Definition at line 6742 of file nrf51_bitfields.h.

◆ UART_INTENCLR_ERROR_Disabled

#define UART_INTENCLR_ERROR_Disabled (0UL)

Interrupt disabled.

Definition at line 6740 of file nrf51_bitfields.h.

◆ UART_INTENCLR_ERROR_Enabled

#define UART_INTENCLR_ERROR_Enabled (1UL)

Interrupt enabled.

Definition at line 6741 of file nrf51_bitfields.h.

◆ UART_INTENCLR_ERROR_Msk

#define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos)

Bit mask of ERROR field.

Definition at line 6739 of file nrf51_bitfields.h.

◆ UART_INTENCLR_ERROR_Pos

#define UART_INTENCLR_ERROR_Pos (9UL)

Position of ERROR field.

Definition at line 6738 of file nrf51_bitfields.h.

◆ UART_INTENCLR_NCTS_Clear

#define UART_INTENCLR_NCTS_Clear (1UL)

Disable interrupt on write.

Definition at line 6763 of file nrf51_bitfields.h.

◆ UART_INTENCLR_NCTS_Disabled

#define UART_INTENCLR_NCTS_Disabled (0UL)

Interrupt disabled.

Definition at line 6761 of file nrf51_bitfields.h.

◆ UART_INTENCLR_NCTS_Enabled

#define UART_INTENCLR_NCTS_Enabled (1UL)

Interrupt enabled.

Definition at line 6762 of file nrf51_bitfields.h.

◆ UART_INTENCLR_NCTS_Msk

#define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos)

Bit mask of NCTS field.

Definition at line 6760 of file nrf51_bitfields.h.

◆ UART_INTENCLR_NCTS_Pos

#define UART_INTENCLR_NCTS_Pos (1UL)

Position of NCTS field.

Definition at line 6759 of file nrf51_bitfields.h.

◆ UART_INTENCLR_RXDRDY_Clear

#define UART_INTENCLR_RXDRDY_Clear (1UL)

Disable interrupt on write.

Definition at line 6756 of file nrf51_bitfields.h.

◆ UART_INTENCLR_RXDRDY_Disabled

#define UART_INTENCLR_RXDRDY_Disabled (0UL)

Interrupt disabled.

Definition at line 6754 of file nrf51_bitfields.h.

◆ UART_INTENCLR_RXDRDY_Enabled

#define UART_INTENCLR_RXDRDY_Enabled (1UL)

Interrupt enabled.

Definition at line 6755 of file nrf51_bitfields.h.

◆ UART_INTENCLR_RXDRDY_Msk

#define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos)

Bit mask of RXDRDY field.

Definition at line 6753 of file nrf51_bitfields.h.

◆ UART_INTENCLR_RXDRDY_Pos

#define UART_INTENCLR_RXDRDY_Pos (2UL)

Position of RXDRDY field.

Definition at line 6752 of file nrf51_bitfields.h.

◆ UART_INTENCLR_RXTO_Clear

#define UART_INTENCLR_RXTO_Clear (1UL)

Disable interrupt on write.

Definition at line 6735 of file nrf51_bitfields.h.

◆ UART_INTENCLR_RXTO_Disabled

#define UART_INTENCLR_RXTO_Disabled (0UL)

Interrupt disabled.

Definition at line 6733 of file nrf51_bitfields.h.

◆ UART_INTENCLR_RXTO_Enabled

#define UART_INTENCLR_RXTO_Enabled (1UL)

Interrupt enabled.

Definition at line 6734 of file nrf51_bitfields.h.

◆ UART_INTENCLR_RXTO_Msk

#define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos)

Bit mask of RXTO field.

Definition at line 6732 of file nrf51_bitfields.h.

◆ UART_INTENCLR_RXTO_Pos

#define UART_INTENCLR_RXTO_Pos (17UL)

Position of RXTO field.

Definition at line 6731 of file nrf51_bitfields.h.

◆ UART_INTENCLR_TXDRDY_Clear

#define UART_INTENCLR_TXDRDY_Clear (1UL)

Disable interrupt on write.

Definition at line 6749 of file nrf51_bitfields.h.

◆ UART_INTENCLR_TXDRDY_Disabled

#define UART_INTENCLR_TXDRDY_Disabled (0UL)

Interrupt disabled.

Definition at line 6747 of file nrf51_bitfields.h.

◆ UART_INTENCLR_TXDRDY_Enabled

#define UART_INTENCLR_TXDRDY_Enabled (1UL)

Interrupt enabled.

Definition at line 6748 of file nrf51_bitfields.h.

◆ UART_INTENCLR_TXDRDY_Msk

#define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos)

Bit mask of TXDRDY field.

Definition at line 6746 of file nrf51_bitfields.h.

◆ UART_INTENCLR_TXDRDY_Pos

#define UART_INTENCLR_TXDRDY_Pos (7UL)

Position of TXDRDY field.

Definition at line 6745 of file nrf51_bitfields.h.

◆ UART_INTENSET_CTS_Disabled

#define UART_INTENSET_CTS_Disabled (0UL)

Interrupt disabled.

Definition at line 6723 of file nrf51_bitfields.h.

◆ UART_INTENSET_CTS_Enabled

#define UART_INTENSET_CTS_Enabled (1UL)

Interrupt enabled.

Definition at line 6724 of file nrf51_bitfields.h.

◆ UART_INTENSET_CTS_Msk

#define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos)

Bit mask of CTS field.

Definition at line 6722 of file nrf51_bitfields.h.

◆ UART_INTENSET_CTS_Pos

#define UART_INTENSET_CTS_Pos (0UL)

Position of CTS field.

Definition at line 6721 of file nrf51_bitfields.h.

◆ UART_INTENSET_CTS_Set

#define UART_INTENSET_CTS_Set (1UL)

Enable interrupt on write.

Definition at line 6725 of file nrf51_bitfields.h.

◆ UART_INTENSET_ERROR_Disabled

#define UART_INTENSET_ERROR_Disabled (0UL)

Interrupt disabled.

Definition at line 6695 of file nrf51_bitfields.h.

◆ UART_INTENSET_ERROR_Enabled

#define UART_INTENSET_ERROR_Enabled (1UL)

Interrupt enabled.

Definition at line 6696 of file nrf51_bitfields.h.

◆ UART_INTENSET_ERROR_Msk

#define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos)

Bit mask of ERROR field.

Definition at line 6694 of file nrf51_bitfields.h.

◆ UART_INTENSET_ERROR_Pos

#define UART_INTENSET_ERROR_Pos (9UL)

Position of ERROR field.

Definition at line 6693 of file nrf51_bitfields.h.

◆ UART_INTENSET_ERROR_Set

#define UART_INTENSET_ERROR_Set (1UL)

Enable interrupt on write.

Definition at line 6697 of file nrf51_bitfields.h.

◆ UART_INTENSET_NCTS_Disabled

#define UART_INTENSET_NCTS_Disabled (0UL)

Interrupt disabled.

Definition at line 6716 of file nrf51_bitfields.h.

◆ UART_INTENSET_NCTS_Enabled

#define UART_INTENSET_NCTS_Enabled (1UL)

Interrupt enabled.

Definition at line 6717 of file nrf51_bitfields.h.

◆ UART_INTENSET_NCTS_Msk

#define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos)

Bit mask of NCTS field.

Definition at line 6715 of file nrf51_bitfields.h.

◆ UART_INTENSET_NCTS_Pos

#define UART_INTENSET_NCTS_Pos (1UL)

Position of NCTS field.

Definition at line 6714 of file nrf51_bitfields.h.

◆ UART_INTENSET_NCTS_Set

#define UART_INTENSET_NCTS_Set (1UL)

Enable interrupt on write.

Definition at line 6718 of file nrf51_bitfields.h.

◆ UART_INTENSET_RXDRDY_Disabled

#define UART_INTENSET_RXDRDY_Disabled (0UL)

Interrupt disabled.

Definition at line 6709 of file nrf51_bitfields.h.

◆ UART_INTENSET_RXDRDY_Enabled

#define UART_INTENSET_RXDRDY_Enabled (1UL)

Interrupt enabled.

Definition at line 6710 of file nrf51_bitfields.h.

◆ UART_INTENSET_RXDRDY_Msk

#define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos)

Bit mask of RXDRDY field.

Definition at line 6708 of file nrf51_bitfields.h.

◆ UART_INTENSET_RXDRDY_Pos

#define UART_INTENSET_RXDRDY_Pos (2UL)

Position of RXDRDY field.

Definition at line 6707 of file nrf51_bitfields.h.

◆ UART_INTENSET_RXDRDY_Set

#define UART_INTENSET_RXDRDY_Set (1UL)

Enable interrupt on write.

Definition at line 6711 of file nrf51_bitfields.h.

◆ UART_INTENSET_RXTO_Disabled

#define UART_INTENSET_RXTO_Disabled (0UL)

Interrupt disabled.

Definition at line 6688 of file nrf51_bitfields.h.

◆ UART_INTENSET_RXTO_Enabled

#define UART_INTENSET_RXTO_Enabled (1UL)

Interrupt enabled.

Definition at line 6689 of file nrf51_bitfields.h.

◆ UART_INTENSET_RXTO_Msk

#define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos)

Bit mask of RXTO field.

Definition at line 6687 of file nrf51_bitfields.h.

◆ UART_INTENSET_RXTO_Pos

#define UART_INTENSET_RXTO_Pos (17UL)

Position of RXTO field.

Definition at line 6686 of file nrf51_bitfields.h.

◆ UART_INTENSET_RXTO_Set

#define UART_INTENSET_RXTO_Set (1UL)

Enable interrupt on write.

Definition at line 6690 of file nrf51_bitfields.h.

◆ UART_INTENSET_TXDRDY_Disabled

#define UART_INTENSET_TXDRDY_Disabled (0UL)

Interrupt disabled.

Definition at line 6702 of file nrf51_bitfields.h.

◆ UART_INTENSET_TXDRDY_Enabled

#define UART_INTENSET_TXDRDY_Enabled (1UL)

Interrupt enabled.

Definition at line 6703 of file nrf51_bitfields.h.

◆ UART_INTENSET_TXDRDY_Msk

#define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos)

Bit mask of TXDRDY field.

Definition at line 6701 of file nrf51_bitfields.h.

◆ UART_INTENSET_TXDRDY_Pos

#define UART_INTENSET_TXDRDY_Pos (7UL)

Position of TXDRDY field.

Definition at line 6700 of file nrf51_bitfields.h.

◆ UART_INTENSET_TXDRDY_Set

#define UART_INTENSET_TXDRDY_Set (1UL)

Enable interrupt on write.

Definition at line 6704 of file nrf51_bitfields.h.

◆ UART_POWER_POWER_Disabled

#define UART_POWER_POWER_Disabled (0UL)

Module power disabled.

Definition at line 6870 of file nrf51_bitfields.h.

◆ UART_POWER_POWER_Enabled

#define UART_POWER_POWER_Enabled (1UL)

Module power enabled.

Definition at line 6871 of file nrf51_bitfields.h.

◆ UART_POWER_POWER_Msk

#define UART_POWER_POWER_Msk (0x1UL << UART_POWER_POWER_Pos)

Bit mask of POWER field.

Definition at line 6869 of file nrf51_bitfields.h.

◆ UART_POWER_POWER_Pos

#define UART_POWER_POWER_Pos (0UL)

Position of POWER field.

Definition at line 6868 of file nrf51_bitfields.h.

◆ UART_RXD_RXD_Msk

#define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos)

Bit mask of RXD field.

Definition at line 6817 of file nrf51_bitfields.h.

◆ UART_RXD_RXD_Pos

#define UART_RXD_RXD_Pos (0UL)

Position of RXD field.

Definition at line 6816 of file nrf51_bitfields.h.

◆ UART_TXD_TXD_Msk

#define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos)

Bit mask of TXD field.

Definition at line 6824 of file nrf51_bitfields.h.

◆ UART_TXD_TXD_Pos

#define UART_TXD_TXD_Pos (0UL)

Position of TXD field.

Definition at line 6823 of file nrf51_bitfields.h.

◆ UICR_FWID_FWID_Msk

#define UICR_FWID_FWID_Msk (0xFFFFUL << UICR_FWID_FWID_Pos)

Bit mask of FWID field.

Definition at line 6906 of file nrf51_bitfields.h.

◆ UICR_FWID_FWID_Pos

#define UICR_FWID_FWID_Pos (0UL)

Position of FWID field.

Definition at line 6905 of file nrf51_bitfields.h.

◆ UICR_RBPCONF_PALL_Disabled

#define UICR_RBPCONF_PALL_Disabled (0xFFUL)

Disabled.

Definition at line 6884 of file nrf51_bitfields.h.

◆ UICR_RBPCONF_PALL_Enabled

#define UICR_RBPCONF_PALL_Enabled (0x00UL)

Enabled.

Definition at line 6883 of file nrf51_bitfields.h.

◆ UICR_RBPCONF_PALL_Msk

#define UICR_RBPCONF_PALL_Msk (0xFFUL << UICR_RBPCONF_PALL_Pos)

Bit mask of PALL field.

Definition at line 6882 of file nrf51_bitfields.h.

◆ UICR_RBPCONF_PALL_Pos

#define UICR_RBPCONF_PALL_Pos (8UL)

Position of PALL field.

Definition at line 6881 of file nrf51_bitfields.h.

◆ UICR_RBPCONF_PR0_Disabled

#define UICR_RBPCONF_PR0_Disabled (0xFFUL)

Disabled.

Definition at line 6890 of file nrf51_bitfields.h.

◆ UICR_RBPCONF_PR0_Enabled

#define UICR_RBPCONF_PR0_Enabled (0x00UL)

Enabled.

Definition at line 6889 of file nrf51_bitfields.h.

◆ UICR_RBPCONF_PR0_Msk

#define UICR_RBPCONF_PR0_Msk (0xFFUL << UICR_RBPCONF_PR0_Pos)

Bit mask of PR0 field.

Definition at line 6888 of file nrf51_bitfields.h.

◆ UICR_RBPCONF_PR0_Pos

#define UICR_RBPCONF_PR0_Pos (0UL)

Position of PR0 field.

Definition at line 6887 of file nrf51_bitfields.h.

◆ UICR_XTALFREQ_XTALFREQ_16MHz

#define UICR_XTALFREQ_XTALFREQ_16MHz (0xFFUL)

16MHz Xtal is used.

Definition at line 6899 of file nrf51_bitfields.h.

◆ UICR_XTALFREQ_XTALFREQ_32MHz

#define UICR_XTALFREQ_XTALFREQ_32MHz (0x00UL)

32MHz Xtal is used.

Definition at line 6898 of file nrf51_bitfields.h.

◆ UICR_XTALFREQ_XTALFREQ_Msk

#define UICR_XTALFREQ_XTALFREQ_Msk (0xFFUL << UICR_XTALFREQ_XTALFREQ_Pos)

Bit mask of XTALFREQ field.

Definition at line 6897 of file nrf51_bitfields.h.

◆ UICR_XTALFREQ_XTALFREQ_Pos

#define UICR_XTALFREQ_XTALFREQ_Pos (0UL)

Position of XTALFREQ field.

Definition at line 6896 of file nrf51_bitfields.h.

◆ WDT_CONFIG_HALT_Msk

#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos)

Bit mask of HALT field.

Definition at line 7048 of file nrf51_bitfields.h.

◆ WDT_CONFIG_HALT_Pause

#define WDT_CONFIG_HALT_Pause (0UL)

Pause watchdog while the CPU is halted by the debugger.

Definition at line 7049 of file nrf51_bitfields.h.

◆ WDT_CONFIG_HALT_Pos

#define WDT_CONFIG_HALT_Pos (3UL)

Position of HALT field.

Definition at line 7047 of file nrf51_bitfields.h.

◆ WDT_CONFIG_HALT_Run

#define WDT_CONFIG_HALT_Run (1UL)

Do not pause watchdog while the CPU is halted by the debugger.

Definition at line 7050 of file nrf51_bitfields.h.

◆ WDT_CONFIG_SLEEP_Msk

#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos)

Bit mask of SLEEP field.

Definition at line 7054 of file nrf51_bitfields.h.

◆ WDT_CONFIG_SLEEP_Pause

#define WDT_CONFIG_SLEEP_Pause (0UL)

Pause watchdog while the CPU is asleep.

Definition at line 7055 of file nrf51_bitfields.h.

◆ WDT_CONFIG_SLEEP_Pos

#define WDT_CONFIG_SLEEP_Pos (0UL)

Position of SLEEP field.

Definition at line 7053 of file nrf51_bitfields.h.

◆ WDT_CONFIG_SLEEP_Run

#define WDT_CONFIG_SLEEP_Run (1UL)

Do not pause watchdog while the CPU is asleep.

Definition at line 7056 of file nrf51_bitfields.h.

◆ WDT_INTENCLR_TIMEOUT_Clear

#define WDT_INTENCLR_TIMEOUT_Clear (1UL)

Disable interrupt on write.

Definition at line 6930 of file nrf51_bitfields.h.

◆ WDT_INTENCLR_TIMEOUT_Disabled

#define WDT_INTENCLR_TIMEOUT_Disabled (0UL)

Interrupt disabled.

Definition at line 6928 of file nrf51_bitfields.h.

◆ WDT_INTENCLR_TIMEOUT_Enabled

#define WDT_INTENCLR_TIMEOUT_Enabled (1UL)

Interrupt enabled.

Definition at line 6929 of file nrf51_bitfields.h.

◆ WDT_INTENCLR_TIMEOUT_Msk

#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos)

Bit mask of TIMEOUT field.

Definition at line 6927 of file nrf51_bitfields.h.

◆ WDT_INTENCLR_TIMEOUT_Pos

#define WDT_INTENCLR_TIMEOUT_Pos (0UL)

Position of TIMEOUT field.

Definition at line 6926 of file nrf51_bitfields.h.

◆ WDT_INTENSET_TIMEOUT_Disabled

#define WDT_INTENSET_TIMEOUT_Disabled (0UL)

Interrupt disabled.

Definition at line 6918 of file nrf51_bitfields.h.

◆ WDT_INTENSET_TIMEOUT_Enabled

#define WDT_INTENSET_TIMEOUT_Enabled (1UL)

Interrupt enabled.

Definition at line 6919 of file nrf51_bitfields.h.

◆ WDT_INTENSET_TIMEOUT_Msk

#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos)

Bit mask of TIMEOUT field.

Definition at line 6917 of file nrf51_bitfields.h.

◆ WDT_INTENSET_TIMEOUT_Pos

#define WDT_INTENSET_TIMEOUT_Pos (0UL)

Position of TIMEOUT field.

Definition at line 6916 of file nrf51_bitfields.h.

◆ WDT_INTENSET_TIMEOUT_Set

#define WDT_INTENSET_TIMEOUT_Set (1UL)

Enable interrupt on write.

Definition at line 6920 of file nrf51_bitfields.h.

◆ WDT_POWER_POWER_Disabled

#define WDT_POWER_POWER_Disabled (0UL)

Module power disabled.

Definition at line 7072 of file nrf51_bitfields.h.

◆ WDT_POWER_POWER_Enabled

#define WDT_POWER_POWER_Enabled (1UL)

Module power enabled.

Definition at line 7073 of file nrf51_bitfields.h.

◆ WDT_POWER_POWER_Msk

#define WDT_POWER_POWER_Msk (0x1UL << WDT_POWER_POWER_Pos)

Bit mask of POWER field.

Definition at line 7071 of file nrf51_bitfields.h.

◆ WDT_POWER_POWER_Pos

#define WDT_POWER_POWER_Pos (0UL)

Position of POWER field.

Definition at line 7070 of file nrf51_bitfields.h.

◆ WDT_REQSTATUS_RR0_DisabledOrRequested

#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL)

RR[0] register is not enabled or has already requested reload.

Definition at line 6989 of file nrf51_bitfields.h.

◆ WDT_REQSTATUS_RR0_EnabledAndUnrequested

#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL)

RR[0] register is enabled and has not jet requested.

Definition at line 6990 of file nrf51_bitfields.h.

◆ WDT_REQSTATUS_RR0_Msk

#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos)

Bit mask of RR0 field.

Definition at line 6988 of file nrf51_bitfields.h.

◆ WDT_REQSTATUS_RR0_Pos

#define WDT_REQSTATUS_RR0_Pos (0UL)

Position of RR0 field.

Definition at line 6987 of file nrf51_bitfields.h.

◆ WDT_REQSTATUS_RR1_DisabledOrRequested

#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL)

RR[1] register is not enabled or has already requested reload.

Definition at line 6983 of file nrf51_bitfields.h.

◆ WDT_REQSTATUS_RR1_EnabledAndUnrequested

#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL)

RR[1] register is enabled and has not jet requested.

Definition at line 6984 of file nrf51_bitfields.h.

◆ WDT_REQSTATUS_RR1_Msk

#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos)

Bit mask of RR1 field.

Definition at line 6982 of file nrf51_bitfields.h.

◆ WDT_REQSTATUS_RR1_Pos

#define WDT_REQSTATUS_RR1_Pos (1UL)

Position of RR1 field.

Definition at line 6981 of file nrf51_bitfields.h.

◆ WDT_REQSTATUS_RR2_DisabledOrRequested

#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL)

RR[2] register is not enabled or has already requested reload.

Definition at line 6977 of file nrf51_bitfields.h.

◆ WDT_REQSTATUS_RR2_EnabledAndUnrequested

#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL)

RR[2] register is enabled and has not jet requested.

Definition at line 6978 of file nrf51_bitfields.h.

◆ WDT_REQSTATUS_RR2_Msk

#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos)

Bit mask of RR2 field.

Definition at line 6976 of file nrf51_bitfields.h.

◆ WDT_REQSTATUS_RR2_Pos

#define WDT_REQSTATUS_RR2_Pos (2UL)

Position of RR2 field.

Definition at line 6975 of file nrf51_bitfields.h.

◆ WDT_REQSTATUS_RR3_DisabledOrRequested

#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL)

RR[3] register is not enabled or has already requested reload.

Definition at line 6971 of file nrf51_bitfields.h.

◆ WDT_REQSTATUS_RR3_EnabledAndUnrequested

#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL)

RR[3] register is enabled and has not jet requested.

Definition at line 6972 of file nrf51_bitfields.h.

◆ WDT_REQSTATUS_RR3_Msk

#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos)

Bit mask of RR3 field.

Definition at line 6970 of file nrf51_bitfields.h.

◆ WDT_REQSTATUS_RR3_Pos

#define WDT_REQSTATUS_RR3_Pos (3UL)

Position of RR3 field.

Definition at line 6969 of file nrf51_bitfields.h.

◆ WDT_REQSTATUS_RR4_DisabledOrRequested

#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL)

RR[4] register is not enabled or has already requested reload.

Definition at line 6965 of file nrf51_bitfields.h.

◆ WDT_REQSTATUS_RR4_EnabledAndUnrequested

#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL)

RR[4] register is enabled and has not jet requested.

Definition at line 6966 of file nrf51_bitfields.h.

◆ WDT_REQSTATUS_RR4_Msk

#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos)

Bit mask of RR4 field.

Definition at line 6964 of file nrf51_bitfields.h.

◆ WDT_REQSTATUS_RR4_Pos

#define WDT_REQSTATUS_RR4_Pos (4UL)

Position of RR4 field.

Definition at line 6963 of file nrf51_bitfields.h.

◆ WDT_REQSTATUS_RR5_DisabledOrRequested

#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL)

RR[5] register is not enabled or has already requested reload.

Definition at line 6959 of file nrf51_bitfields.h.

◆ WDT_REQSTATUS_RR5_EnabledAndUnrequested

#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL)

RR[5] register is enabled and has not jet requested.

Definition at line 6960 of file nrf51_bitfields.h.

◆ WDT_REQSTATUS_RR5_Msk

#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos)

Bit mask of RR5 field.

Definition at line 6958 of file nrf51_bitfields.h.

◆ WDT_REQSTATUS_RR5_Pos

#define WDT_REQSTATUS_RR5_Pos (5UL)

Position of RR5 field.

Definition at line 6957 of file nrf51_bitfields.h.

◆ WDT_REQSTATUS_RR6_DisabledOrRequested

#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL)

RR[6] register is not enabled or has already requested reload.

Definition at line 6953 of file nrf51_bitfields.h.

◆ WDT_REQSTATUS_RR6_EnabledAndUnrequested

#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL)

RR[6] register is enabled and has not jet requested.

Definition at line 6954 of file nrf51_bitfields.h.

◆ WDT_REQSTATUS_RR6_Msk

#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos)

Bit mask of RR6 field.

Definition at line 6952 of file nrf51_bitfields.h.

◆ WDT_REQSTATUS_RR6_Pos

#define WDT_REQSTATUS_RR6_Pos (6UL)

Position of RR6 field.

Definition at line 6951 of file nrf51_bitfields.h.

◆ WDT_REQSTATUS_RR7_DisabledOrRequested

#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL)

RR[7] register is not enabled or has already requested reload.

Definition at line 6947 of file nrf51_bitfields.h.

◆ WDT_REQSTATUS_RR7_EnabledAndUnrequested

#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL)

RR[7] register is enabled and has not jet requested.

Definition at line 6948 of file nrf51_bitfields.h.

◆ WDT_REQSTATUS_RR7_Msk

#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos)

Bit mask of RR7 field.

Definition at line 6946 of file nrf51_bitfields.h.

◆ WDT_REQSTATUS_RR7_Pos

#define WDT_REQSTATUS_RR7_Pos (7UL)

Position of RR7 field.

Definition at line 6945 of file nrf51_bitfields.h.

◆ WDT_RR_RR_Msk

#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos)

Bit mask of RR field.

Definition at line 7063 of file nrf51_bitfields.h.

◆ WDT_RR_RR_Pos

#define WDT_RR_RR_Pos (0UL)

Position of RR field.

Definition at line 7062 of file nrf51_bitfields.h.

◆ WDT_RR_RR_Reload

#define WDT_RR_RR_Reload (0x6E524635UL)

Value to request a reload of the watchdog timer.

Definition at line 7064 of file nrf51_bitfields.h.

◆ WDT_RREN_RR0_Disabled

#define WDT_RREN_RR0_Disabled (0UL)

RR[0] register is disabled.

Definition at line 7040 of file nrf51_bitfields.h.

◆ WDT_RREN_RR0_Enabled

#define WDT_RREN_RR0_Enabled (1UL)

RR[0] register is enabled.

Definition at line 7041 of file nrf51_bitfields.h.

◆ WDT_RREN_RR0_Msk

#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos)

Bit mask of RR0 field.

Definition at line 7039 of file nrf51_bitfields.h.

◆ WDT_RREN_RR0_Pos

#define WDT_RREN_RR0_Pos (0UL)

Position of RR0 field.

Definition at line 7038 of file nrf51_bitfields.h.

◆ WDT_RREN_RR1_Disabled

#define WDT_RREN_RR1_Disabled (0UL)

RR[1] register is disabled.

Definition at line 7034 of file nrf51_bitfields.h.

◆ WDT_RREN_RR1_Enabled

#define WDT_RREN_RR1_Enabled (1UL)

RR[1] register is enabled.

Definition at line 7035 of file nrf51_bitfields.h.

◆ WDT_RREN_RR1_Msk

#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos)

Bit mask of RR1 field.

Definition at line 7033 of file nrf51_bitfields.h.

◆ WDT_RREN_RR1_Pos

#define WDT_RREN_RR1_Pos (1UL)

Position of RR1 field.

Definition at line 7032 of file nrf51_bitfields.h.

◆ WDT_RREN_RR2_Disabled

#define WDT_RREN_RR2_Disabled (0UL)

RR[2] register is disabled.

Definition at line 7028 of file nrf51_bitfields.h.

◆ WDT_RREN_RR2_Enabled

#define WDT_RREN_RR2_Enabled (1UL)

RR[2] register is enabled.

Definition at line 7029 of file nrf51_bitfields.h.

◆ WDT_RREN_RR2_Msk

#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos)

Bit mask of RR2 field.

Definition at line 7027 of file nrf51_bitfields.h.

◆ WDT_RREN_RR2_Pos

#define WDT_RREN_RR2_Pos (2UL)

Position of RR2 field.

Definition at line 7026 of file nrf51_bitfields.h.

◆ WDT_RREN_RR3_Disabled

#define WDT_RREN_RR3_Disabled (0UL)

RR[3] register is disabled.

Definition at line 7022 of file nrf51_bitfields.h.

◆ WDT_RREN_RR3_Enabled

#define WDT_RREN_RR3_Enabled (1UL)

RR[3] register is enabled.

Definition at line 7023 of file nrf51_bitfields.h.

◆ WDT_RREN_RR3_Msk

#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos)

Bit mask of RR3 field.

Definition at line 7021 of file nrf51_bitfields.h.

◆ WDT_RREN_RR3_Pos

#define WDT_RREN_RR3_Pos (3UL)

Position of RR3 field.

Definition at line 7020 of file nrf51_bitfields.h.

◆ WDT_RREN_RR4_Disabled

#define WDT_RREN_RR4_Disabled (0UL)

RR[4] register is disabled.

Definition at line 7016 of file nrf51_bitfields.h.

◆ WDT_RREN_RR4_Enabled

#define WDT_RREN_RR4_Enabled (1UL)

RR[4] register is enabled.

Definition at line 7017 of file nrf51_bitfields.h.

◆ WDT_RREN_RR4_Msk

#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos)

Bit mask of RR4 field.

Definition at line 7015 of file nrf51_bitfields.h.

◆ WDT_RREN_RR4_Pos

#define WDT_RREN_RR4_Pos (4UL)

Position of RR4 field.

Definition at line 7014 of file nrf51_bitfields.h.

◆ WDT_RREN_RR5_Disabled

#define WDT_RREN_RR5_Disabled (0UL)

RR[5] register is disabled.

Definition at line 7010 of file nrf51_bitfields.h.

◆ WDT_RREN_RR5_Enabled

#define WDT_RREN_RR5_Enabled (1UL)

RR[5] register is enabled.

Definition at line 7011 of file nrf51_bitfields.h.

◆ WDT_RREN_RR5_Msk

#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos)

Bit mask of RR5 field.

Definition at line 7009 of file nrf51_bitfields.h.

◆ WDT_RREN_RR5_Pos

#define WDT_RREN_RR5_Pos (5UL)

Position of RR5 field.

Definition at line 7008 of file nrf51_bitfields.h.

◆ WDT_RREN_RR6_Disabled

#define WDT_RREN_RR6_Disabled (0UL)

RR[6] register is disabled.

Definition at line 7004 of file nrf51_bitfields.h.

◆ WDT_RREN_RR6_Enabled

#define WDT_RREN_RR6_Enabled (1UL)

RR[6] register is enabled.

Definition at line 7005 of file nrf51_bitfields.h.

◆ WDT_RREN_RR6_Msk

#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos)

Bit mask of RR6 field.

Definition at line 7003 of file nrf51_bitfields.h.

◆ WDT_RREN_RR6_Pos

#define WDT_RREN_RR6_Pos (6UL)

Position of RR6 field.

Definition at line 7002 of file nrf51_bitfields.h.

◆ WDT_RREN_RR7_Disabled

#define WDT_RREN_RR7_Disabled (0UL)

RR[7] register is disabled.

Definition at line 6998 of file nrf51_bitfields.h.

◆ WDT_RREN_RR7_Enabled

#define WDT_RREN_RR7_Enabled (1UL)

RR[7] register is enabled.

Definition at line 6999 of file nrf51_bitfields.h.

◆ WDT_RREN_RR7_Msk

#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos)

Bit mask of RR7 field.

Definition at line 6997 of file nrf51_bitfields.h.

◆ WDT_RREN_RR7_Pos

#define WDT_RREN_RR7_Pos (7UL)

Position of RR7 field.

Definition at line 6996 of file nrf51_bitfields.h.

◆ WDT_RUNSTATUS_RUNSTATUS_Msk

#define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos)

Bit mask of RUNSTATUS field.

Definition at line 6937 of file nrf51_bitfields.h.

◆ WDT_RUNSTATUS_RUNSTATUS_NotRunning

#define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL)

Watchdog timer is not running.

Definition at line 6938 of file nrf51_bitfields.h.

◆ WDT_RUNSTATUS_RUNSTATUS_Pos

#define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL)

Position of RUNSTATUS field.

Definition at line 6936 of file nrf51_bitfields.h.

◆ WDT_RUNSTATUS_RUNSTATUS_Running

#define WDT_RUNSTATUS_RUNSTATUS_Running (1UL)

Watchdog timer is running.

Definition at line 6939 of file nrf51_bitfields.h.

Macros

Macro Definition Documentation

◆ AAR_ENABLE_ENABLE_Disabled

◆ AAR_ENABLE_ENABLE_Enabled

◆ AAR_ENABLE_ENABLE_Msk

◆ AAR_ENABLE_ENABLE_Pos

◆ AAR_INTENCLR_END_Clear

◆ AAR_INTENCLR_END_Disabled

◆ AAR_INTENCLR_END_Enabled

◆ AAR_INTENCLR_END_Msk

◆ AAR_INTENCLR_END_Pos

◆ AAR_INTENCLR_NOTRESOLVED_Clear

◆ AAR_INTENCLR_NOTRESOLVED_Disabled

◆ AAR_INTENCLR_NOTRESOLVED_Enabled

◆ AAR_INTENCLR_NOTRESOLVED_Msk

◆ AAR_INTENCLR_NOTRESOLVED_Pos

◆ AAR_INTENCLR_RESOLVED_Clear

◆ AAR_INTENCLR_RESOLVED_Disabled

◆ AAR_INTENCLR_RESOLVED_Enabled

◆ AAR_INTENCLR_RESOLVED_Msk

◆ AAR_INTENCLR_RESOLVED_Pos

◆ AAR_INTENSET_END_Disabled

◆ AAR_INTENSET_END_Enabled

◆ AAR_INTENSET_END_Msk

◆ AAR_INTENSET_END_Pos

◆ AAR_INTENSET_END_Set

◆ AAR_INTENSET_NOTRESOLVED_Disabled

◆ AAR_INTENSET_NOTRESOLVED_Enabled

◆ AAR_INTENSET_NOTRESOLVED_Msk

◆ AAR_INTENSET_NOTRESOLVED_Pos

◆ AAR_INTENSET_NOTRESOLVED_Set

◆ AAR_INTENSET_RESOLVED_Disabled

◆ AAR_INTENSET_RESOLVED_Enabled

◆ AAR_INTENSET_RESOLVED_Msk

◆ AAR_INTENSET_RESOLVED_Pos

◆ AAR_INTENSET_RESOLVED_Set

◆ AAR_NIRK_NIRK_Msk

◆ AAR_NIRK_NIRK_Pos

◆ AAR_POWER_POWER_Disabled

◆ AAR_POWER_POWER_Enabled

◆ AAR_POWER_POWER_Msk

◆ AAR_POWER_POWER_Pos

◆ AAR_STATUS_STATUS_Msk

◆ AAR_STATUS_STATUS_Pos

◆ ADC_BUSY_BUSY_Busy

◆ ADC_BUSY_BUSY_Msk

◆ ADC_BUSY_BUSY_Pos

◆ ADC_BUSY_BUSY_Ready

◆ ADC_CONFIG_EXTREFSEL_AnalogReference0

◆ ADC_CONFIG_EXTREFSEL_AnalogReference1

◆ ADC_CONFIG_EXTREFSEL_Msk

◆ ADC_CONFIG_EXTREFSEL_None

◆ ADC_CONFIG_EXTREFSEL_Pos

◆ ADC_CONFIG_INPSEL_AnalogInputNoPrescaling

◆ ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling

◆ ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling

◆ ADC_CONFIG_INPSEL_Msk

◆ ADC_CONFIG_INPSEL_Pos

◆ ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling

◆ ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling

◆ ADC_CONFIG_PSEL_AnalogInput0

◆ ADC_CONFIG_PSEL_AnalogInput1

◆ ADC_CONFIG_PSEL_AnalogInput2

◆ ADC_CONFIG_PSEL_AnalogInput3

◆ ADC_CONFIG_PSEL_AnalogInput4

◆ ADC_CONFIG_PSEL_AnalogInput5

◆ ADC_CONFIG_PSEL_AnalogInput6

◆ ADC_CONFIG_PSEL_AnalogInput7

◆ ADC_CONFIG_PSEL_Disabled

◆ ADC_CONFIG_PSEL_Msk

◆ ADC_CONFIG_PSEL_Pos

◆ ADC_CONFIG_REFSEL_External

◆ ADC_CONFIG_REFSEL_Msk

◆ ADC_CONFIG_REFSEL_Pos

◆ ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling

◆ ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling

◆ ADC_CONFIG_REFSEL_VBG

◆ ADC_CONFIG_RES_10bit

◆ ADC_CONFIG_RES_8bit

◆ ADC_CONFIG_RES_9bit